Circuit board and manufacturing method thereof

Abstract

A circuit board comprises a board body, a plurality of chips, a filling layer and a signal line layer. The plate body is provided with a cavity. The chips are arranged in the cavity, each chip is provided with an electric connection surface and a magnetic suction surface opposite to the electric connection surface, each electric connection surface comprises a connection pad, and each magnetic suction surface comprises a magnetic layer. The filling layer is filled in the cavity and among the chips and covers the electrical connection surfaces. The signal line layer is arranged on the filling layer and penetrates through the filling layer to be electrically connected with the connecting pads on the electric connecting surfaces. The circuit board can improve the yield.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, and particularly to a circuit board having a cavity with a chip disposed in the cavity and a manufacturing method thereof. Background Art

[0002] With the development of electronic products towards lighter and smaller sizes, more and more products have chips disposed in the cavities of circuit boards. Currently, one of the manufacturing methods is to first dispose the chips in the cavities of the circuit boards, and then fill the cavities with resin and perform lamination. However, during the resin filling process, the flowing resin may drive the chips, causing the chips to shift, so that the chips cannot form effective electrical connections with the circuit layers in the circuit boards, resulting in poor electrical performance after encapsulation, and thus making it difficult to improve the yield rate, or even causing the yield rate to decrease. Summary of the Invention

[0003] At least one embodiment of the present invention provides a circuit board with a chip having a magnetic attraction surface disposed in a cavity, which can improve the yield rate of the circuit board.

[0004] At least one embodiment of the present invention provides a manufacturing method of the above circuit board to help improve the yield rate of the above circuit board.

[0005] A circuit board provided by at least one embodiment of the present invention includes a board body, a plurality of chips, a filling layer, and a signal line layer. The board body has a cavity. These chips are disposed in the cavity. Each chip has an electrical connection surface and a magnetic attraction surface opposite to the electrical connection surface. Each electrical connection surface includes pads, and each magnetic attraction surface includes a magnetic layer. The filling layer fills the cavity and is between these chips, and covers these electrical connection surfaces. The signal line layer is disposed on the filling layer and electrically connects these pads through the filling layer to these electrical connection surfaces.

[0006] In at least one embodiment of the present invention, the magnetic layer includes ferromagnetic material or ferrimagnetic material.

[0007] In at least one embodiment of the present invention, the ferromagnetic material includes iron, cobalt, and nickel.

[0008] In at least one embodiment of the present invention, the board body includes a substrate and a dielectric layer. The substrate has an upper surface and a lower surface opposite to the upper surface. The dielectric layer is disposed on the upper surface and defines the cavity with the substrate.

[0009] In at least one embodiment of the present invention, each of the magnetic attraction surfaces is closer to the upper surface than each of the electrical connection surfaces.

[0010] In at least one embodiment of the present invention, each of the magnetic attraction surfaces contacts the upper surface.

[0011] In at least one embodiment of the present invention, the circuit board further includes a power line layer disposed on the lower surface.

[0012] A method for manufacturing a circuit board according to at least one embodiment of the present invention includes providing an initial board body having a plurality of board positioning holes; providing an adhesive layer having a first side and a second side opposite to the first side, and attaching the initial board body to the first side; forming an initial cavity in the initial board body, with a part of the first side exposed by the initial cavity; providing a carrier board having a plurality of carrier board positioning holes and a plurality of through holes; providing a plurality of magnets respectively disposed in these through holes; after these magnets are respectively disposed in these through holes, aligning these carrier board positioning holes with these board positioning holes respectively to attach the carrier board to the second side of the adhesive layer; providing a plurality of chips, each chip having an electrically connecting surface and a magnetic attracting surface opposite to the electrically connecting surface, and these magnetic attracting surfaces respectively corresponding to these magnets and attaching to the part of the first side exposed by the initial cavity; after these magnetic attracting surfaces respectively correspond to these magnets and attach to the part of the first side exposed by the initial cavity, filling a filling layer into the initial cavity and between these chips, and covering these electrically connecting surfaces; removing the adhesive layer and the carrier board.

[0013] In at least one embodiment of the present invention, the method for manufacturing the circuit board further includes, after removing the adhesive layer and the carrier board, forming a substrate on the initial board body to form a board body, the substrate having an upper surface and a lower surface opposite to the upper surface, the board body having a cavity and a dielectric layer, the substrate and the dielectric layer defining the cavity, and each of the magnetic attracting surfaces being closer to the upper surface than each of the electrically connecting surfaces.

[0014] In at least one embodiment of the present invention, the method for manufacturing the circuit board further includes, after forming the substrate, forming a power line layer on the lower surface; forming a signal line layer on the filling layer, and the signal line layer passing through the filling layer to electrically connect the plurality of electrically connecting surfaces. Description of the Drawings

[0015] Figure 1 is a cross-sectional schematic view of a circuit board according to at least one embodiment of the present invention.

[0016] Figures 2A to 2C is a cross-sectional schematic view of the initial board body and the adhesive layer of the present invention at different process stages.

[0017] Figures 3A to 3C is a cross-sectional schematic view of the carrier board and the magnets of the present invention at different process stages.

[0018] Figures 4A to 4C is a schematic view of the chips of the present invention at different process stages.

[0019] Figure 5A and Figure 5BIt is a schematic cross-sectional view of a circuit board in different process stages of at least one embodiment of the present invention.

[0020] Figure 6A It is a schematic plan view of a chip, an initial board body and a resin of at least one embodiment of the present invention.

[0021] Figure 6B It is a schematic plan view of a carrier board and a magnet of at least one embodiment of the present invention. Detailed implementation manners

[0022] In the following text, in order to clearly present the technical features of the present invention, the dimensions (such as length, width, thickness and depth) of elements (such as layers, films, substrates and regions, etc.) in the drawings are enlarged in a non-uniform ratio, and the number of some elements is reduced. Therefore, the description and explanation of the following embodiments are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes and deviations of both caused by actual processes and / or tolerances. For example, the flat surfaces shown in the drawings may have rough and / or non-linear features, and the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the claims of the present invention.

[0023] Secondly, words such as "about", "approximately" or "substantially" used in the present invention not only cover the explicitly recorded numerical values and numerical ranges, but also cover the allowable deviation ranges that can be understood by those skilled in the art to which the invention pertains, where this deviation range can be determined by the errors generated during measurement, and this error is caused by, for example, the limitations of both the measurement system and process conditions. For example, two objects (such as the plane of a substrate or a trace) are "substantially parallel" or "substantially perpendicular", where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between these two objects can include non-parallelism and non-perpendicularity caused by the allowable deviation range.

[0024] The relative spatial terms used in the present invention, such as "below", "beneath", "above", "on top of", etc., are for the convenience of describing the relative relationship between one element or feature and another element or feature, as shown in the drawings. The true meanings of these relative spatial terms include other orientations. For example, when the drawing is flipped 180 degrees up and down, the relationship between one element and another element may change from "below", "beneath" to "above", "on top of". In addition, the relative spatial descriptions used in the present invention should also be interpreted in the same way.

[0025] It should be understood that although the present invention may use terms such as "first", "second", "third", etc. to describe various elements or features, these elements or features should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one feature from another. In addition, the term "or" used in the present invention should, depending on the actual situation, possibly include any one or a combination of more of the associated listed items.

[0026] Although a series of operations or steps are used to illustrate the manufacturing method in the present invention, the order shown by these operations or steps should not be construed as a limitation of the present invention. For example, certain operations or steps can be carried out in a different order and / or simultaneously with other steps. In addition, each operation or step described herein may include several sub-steps or actions.

[0027] In addition, the present invention can be implemented or applied through other different specific embodiments, and various details of the present invention can also be combined, modified, and changed based on different viewpoints and applications without departing from the concept of the present invention.

[0028] Figure 1 is a schematic cross-sectional view of a circuit board according to at least one embodiment of the present invention. Please refer to Figure 1 , the circuit board 1 includes a board body 10, a plurality of chips 20, a filling layer 30, and a signal line layer 40. The board body 10 has a cavity 11. These chips 20 are disposed in the cavity 11, each chip 20 has an electrical connection surface ES and a magnetic attraction surface MS opposite to the electrical connection surface ES, each electrical connection surface ES includes a pad 21, and each magnetic attraction surface MS includes a magnetic layer 22. The filling layer 30 is filled in the cavity 11 and between these chips 20, and covers these electrical connection surfaces ES. The signal line layer 40 is disposed on the filling layer 30 and electrically connects these pads 21 through the filling layer 30 to these electrical connection surfaces ES.

[0029] Since the chip 20 has a magnetic attraction surface MS, and the magnetic attraction surface MS includes a magnetic layer 22, when the chip 20 is disposed in the cavity 11 of the circuit board 1 and the filling layer 30 is filled into the cavity 11, the carrier plate provided with a magnet corresponding to the magnetic layer 22 can attract and fix the chip 20 to prevent the chip 20 from shifting during the filling process of the filling layer 30, so that the chip 20 cannot form an effective electrical connection and result in poor electrical performance after packaging. Therefore, by designing the chip disposed in the cavity of the circuit board to have a magnetic attraction surface, the yield of the circuit board can be improved.

[0030] Please continue to refer to Figure 1, the board body 10 includes a substrate 12 and a dielectric layer 13. The substrate 12 has an upper surface US and a lower surface BS opposite to the upper surface US. The dielectric layer 13 is disposed on the upper surface US and defines a cavity 11 with the substrate 12. The circuit board 1 further includes a power line layer 50 disposed on the lower surface BS. In addition, the magnetic attraction surface MS is closer to the upper surface US than the electrical connection surface ES. In some embodiments, the magnetic attraction surface MS contacts the upper surface US.

[0031] As Figure 1 shown, the filling layer 30 covers and contacts the electrical connection surface ES of the chip 20 and contacts the side surface of the chip 20, and contacts the portion of the magnetic attraction surface MS of the chip 20 that does not include the magnetic layer 22, and also contacts the side surface of the magnetic layer 22, the upper surface US of the substrate 12, and the side surface of the dielectric layer 13.

[0032] Figures 2A to 2C is a schematic cross-sectional view of the initial board body and the adhesive layer at different process stages of at least one embodiment of the present invention. Please refer to Figures 2A to 2C , the manufacturing method of the circuit board 1 includes providing an initial board body 10' having a plurality of board body positioning holes H1. Providing an adhesive layer TP having a first side S1 and a second side S2 opposite to the first side S1, and the initial board body 10' is attached to the first side S1. An initial cavity 11' is formed in the initial board body 10', and a part of the first side S1 is exposed by the initial cavity 11'.

[0033] Specifically, as Figure 2A shown, a core board CB is provided and an initial circuit layer IT is disposed on both the upper and lower sides of the core board CB. As Figure 2B shown, a plurality of board body positioning holes H1 are formed in the core board CB to form the initial board body 10'. In some embodiments, the board body positioning holes H1 can be formed between the edge of the initial circuit layer IT and the core board CB. The board body positioning holes H1 penetrate through the core board CB. In addition, the board body positioning holes H1 can be formed by a laser drilling process.

[0034] Next, as Figure 2C shown, an adhesive layer TP is provided having a first side S1 and a second side S2 opposite to the first side S1, the initial board body 10' is attached to the first side S1, and an initial cavity 11' is formed in the initial board body 10', and a part of the first side S1 is exposed by the initial cavity 11'. In some embodiments, the material of the adhesive layer TP can include polyimide (PI) or other suitable materials. In some embodiments, the initial cavity 11' penetrates through the initial board body 10'. In addition, the initial cavity 11' can be formed by a machining process, such as routing.

[0035] Figures 3A to 3C is a schematic cross-sectional view of the carrier board and the magnet at different process stages of at least one embodiment of the present invention. Please refer to Figures 3A to 3C, the method for manufacturing the circuit board 1 further includes providing a carrier board 60 having a plurality of carrier board positioning holes H2 and a plurality of through holes T. Providing a plurality of magnets 61 respectively disposed in these through holes T.

[0036] Specifically, as Figure 3A shown, providing an initial carrier board 60'. As Figure 3B shown, forming a plurality of carrier board positioning holes H2 and a plurality of through holes T in the initial carrier board 60' to form the carrier board 60. In some embodiments, the through holes T penetrate the carrier board 60. The through holes T can be formed between a plurality of carrier board positioning holes H2. In other words, the carrier board positioning holes H2 can be formed between the through holes T and the edge of the carrier board 60. In addition, the carrier board positioning holes H2 and the through holes T can be formed by a laser drilling process. Then, as Figure 3C shown, providing a plurality of magnets 61 respectively disposed in these through holes T. In some embodiments, the magnets 61 fill the through holes T.

[0037] Figures 4A to 4C are schematic diagrams of a chip in different process stages of at least one embodiment of the present invention. Please refer to Figures 4A to 4C , the method for manufacturing the circuit board 1 further includes providing a plurality of chips 20, and the chips 20 have an electrical connection surface ES and a magnetic attraction surface MS opposite to the electrical connection surface ES.

[0038] Specifically, as Figure 4A shown, providing a wafer WF, and the wafer WF has an initial electrical connection surface ES' and an opposite surface CS opposite to the initial electrical connection surface ES'. In some embodiments, the wafer WF includes a plurality of uncut chips, and the initial electrical connection surface ES' includes pads of a plurality of chips.

[0039] Then, as Figure 4B shown, forming a plurality of magnetic layers 22 on the opposite surface CS respectively corresponding to a plurality of chips. In some embodiments, the magnetic layers 22 can be formed by an electroplating process. In addition, the magnetic layers 22 include ferromagnetic materials or ferrimagnetic materials. The ferromagnetic materials include iron, cobalt, nickel or other suitable materials, and the ferrimagnetic materials include iron oxides, iron oxides and other elements or other suitable materials, and the other elements can be, for example, aluminum, cobalt, nickel, manganese, zinc or other suitable materials. In this embodiment, the magnetic layer 22 includes nickel.

[0040] After forming a plurality of magnetic layers 22 on the opposite surface CS of the wafer WF, as Figure 4C shown, cutting the wafer WF to form a plurality of chips 20, the chips 20 have an electrical connection surface ES and a magnetic attraction surface MS opposite to the electrical connection surface ES, and the electrical connection surface ES includes pads 21, and the magnetic attraction surface MS includes magnetic layers 22.

[0041] Figure 5A and Figure 5Bis a cross-sectional schematic view of a circuit board according to at least one embodiment of the present invention at different process stages. Please refer to Figure 5A and Figure 5B , the manufacturing method of the circuit board 1 further includes aligning the carrier board positioning holes H2 with these board body positioning holes H1 respectively through these board body positioning holes H1 to attach the second side S2 of the carrier board 60 with the adhesive layer TP, and these magnetic adsorption surfaces MS respectively correspond to these magnets 61 and are attached to a part of the first side S1 exposed by the initial cavity 11'. After these magnetic adsorption surfaces MS respectively correspond to these magnets 61 and are attached to a part of the first side S1 exposed by the initial cavity 11', the filling layer 30 is filled into the initial cavity 11' and between these chips 20, and covers these electrical connection surfaces ES.

[0042] Specifically, as Figure 5A shown, on the normal line of the initial board body 10', these board body positioning holes H1 respectively overlap with these carrier board positioning holes H2 for alignment with each other, and the second side S2 of the carrier board 60 is attached. Similarly, on the normal line of the initial board body 10', these magnetic adsorption surfaces MS respectively overlap with these magnets 61 for alignment with each other, and these magnetic adsorption surfaces MS are attached to a part of the first side S1 exposed by the initial cavity 11'. In some embodiments, alignment can be performed by X-ray.

[0043] As Figure 5B shown, the filling layer 30 is filled into the initial cavity 11' and between these chips 20, and covers these electrical connection surfaces ES. In addition, the filling layer 30 also extends and fills into the board body positioning holes H1, and between the part of the magnetic adsorption surface MS that does not include the magnetic layer 22 and the first side S1 of the adhesive layer TP. Specifically, the filling layer 30 covers and contacts the electrical connection surfaces ES of the chips 20 and contacts the side surfaces of the chips 20, and contacts the part of the magnetic adsorption surface MS of the chips 20 that does not include the magnetic layer 22, and also contacts the side surfaces of the magnetic layer 22 and the first side S1 of the adhesive layer TP. In some embodiments, the filling layer 30 includes resin.

[0044] Next, as Figure 1 shown, the manufacturing method of the circuit board 1 further includes removing the adhesive layer TP and the carrier board 60. After removing the adhesive layer TP and the carrier board 60, a substrate 12 is formed on the initial board body 10' to form the board body 10. The substrate 12 has an upper surface US and a lower surface BS opposite to the upper surface US. The board body 10 has a cavity 11 and a dielectric layer 13. The substrate 12 and the dielectric layer 13 define the cavity 11, and the magnetic adsorption surface MS is closer to the upper surface US than the electrical connection surface ES. In addition, after forming the substrate 12, a power line layer 50 is formed on the lower surface BS, and a signal line layer 40 is formed on the filling layer 30. The signal line layer 40 passes through the filling layer 30 to electrically connect these electrical connection surfaces ES.

[0045] Specifically, before removing the adhesive layer TP and the carrier plate 60, the filling layer 30 can be pressed and cured. While removing the adhesive layer TP and the carrier plate 60, or after that, the core board CB between the board positioning holes H1 and the edge of the initial board 10' can be removed, and the remaining core board CB forms the dielectric layer 13. In some embodiments, the signal line layer 40 and the power line layer 50 can be formed by electroless plating and electroplating, and the materials of the signal line layer 40 and the power line layer 50 can include copper.

[0046] Figure 6A is a schematic plan view of a chip, an initial board, and a resin according to at least one embodiment of the present invention. Please refer to Figure 6A , these chips 20 including the magnetic layer 22 are arranged and disposed in the initial cavity 11' along a first direction D1 perpendicular to the normal of the initial board 10'. The filling layer 30 is filled in the initial cavity 11', and these board positioning holes H1 are disposed at positions adjacent to the opposite side edges of the initial board 10' along the first direction D1 and are arranged along a second direction D2 perpendicular to the normal of the initial board 10'. The second direction D2 is different from the first direction D1. In some embodiments, the second direction D2 is perpendicular to the first direction D1. In addition, two of the board positioning holes H1 are respectively disposed on the opposite sides of the initial cavity 11' along the first direction D1.

[0047] Figure 6B is a schematic plan view of a carrier plate and a magnet according to at least one embodiment of the present invention. These through holes T are arranged and disposed in the carrier plate 60 along the first direction D1 and are located in the cavity projection area A formed by the orthographic projection of the initial cavity 11' on the carrier plate 60. These magnets 61 are respectively disposed in these through holes T, and these carrier plate positioning holes H2 are disposed at positions adjacent to the opposite side edges of the carrier plate 60 along the first direction D1 and are arranged along the second direction D2. In addition, two of the carrier plate positioning holes H2 are respectively disposed on the opposite sides of the cavity projection area A along the first direction D1.

[0048] In summary, in the above circuit board and its manufacturing method according to at least one embodiment of the present invention, since the chip has a magnetic attraction surface including a magnetic layer, during the process of disposing the chip in the cavity of the circuit board and filling the filling layer into the cavity, the carrier plate with magnets provided corresponding to the magnetic layer can attract and fix the chip to avoid the chip being offset during the filling process of the filling layer, so that the chip cannot form an effective electrical connection and result in poor electrical performance after encapsulation. Therefore, by designing the chip disposed in the cavity of the circuit board to have a magnetic attraction surface, the yield of the circuit board can be improved.

[0049] Although the present invention has been disclosed as above with embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the appended claims.

[0050]

Symbol Explanation

[0051] 1: Circuit board

[0052] 10: Board body

[0053] 10’: Initial board body

[0054] 11: Cavity

[0055] 11’: Initial cavity

[0056] 12: Substrate

[0057] 13: Dielectric layer

[0058] 20: Chip

[0059] 21: Pad

[0060] 22: Magnetic layer

[0061] 30: Filling layer

[0062] 40: Signal line layer

[0063] 50: Power line layer

[0064] 60: Carrier board

[0065] 60’: Initial carrier board

[0066] 61: Magnet

[0067] A: Cavity projection area

[0068] BS: Lower surface

[0069] CB: Core board

[0070] CS: Opposite surface

[0071] D1: First direction

[0072] D2: Second direction

[0073] ES: Electrical connection surface

[0074] ES’: Initial electrical connection surface

[0075] H1: Board body positioning hole

[0076] H2: Carrier board positioning hole

[0077] IT: Initial line layer

[0078] MS: Magnetic attraction surface

[0079] S1: First side

[0080] S2: Second side

[0081] T: Perforation

[0082] TP: Adhesive layer

[0083] US: Upper surface

[0084] WF: Wafer.

Claims

1. A circuit board, characterized in that, Comprising: A plate body having a cavity; A plurality of chips disposed in the cavity, wherein each chip has an electrical connection surface and a magnetic attraction surface opposite to the electrical connection surface, each electrical connection surface includes pads, and each magnetic attraction surface includes a magnetic layer; A filling layer filled in the cavity and between the plurality of chips and covering the plurality of electrical connection surfaces; And A signal line layer disposed on the filling layer and electrically connecting the plurality of pads through the filling layer to the plurality of electrical connection surfaces.

2. The circuit board according to claim 1, characterized in that, The magnetic layer includes ferromagnetic material or ferrimagnetic material.

3. The circuit board according to claim 2, wherein, The ferromagnetic material includes iron, cobalt, and nickel.

4. The circuit board according to claim 1, wherein The plate body includes: A substrate having an upper surface and a lower surface opposite to the upper surface; and A dielectric layer disposed on the upper surface and defining the cavity with the substrate.

5. The circuit board according to claim 4, characterized in that, Each magnetic attraction surface is closer to the upper surface than each electrical connection surface.

6. The circuit board according to claim 5, wherein, Each magnetic attraction surface contacts the upper surface.

7. The circuit board according to claim 4, wherein It further includes a power line layer disposed on the lower surface.

8. A manufacturing method of a circuit board, characterized in that, Comprising: Providing an initial plate body having a plurality of plate body positioning holes; Providing an adhesive layer having a first side and a second side opposite to the first side, wherein the initial plate body is attached to the first side; Forming an initial cavity in the initial plate body, wherein the initial cavity exposes a part of the first side; Providing a carrier plate having a plurality of carrier plate positioning holes and a plurality of through holes; Providing a plurality of magnets respectively disposed in the plurality of through holes; After the plurality of magnets are respectively disposed in the plurality of through holes, attaching the carrier plate to the second side by aligning the plurality of plate body positioning holes with the plurality of carrier plate positioning holes respectively; Providing a plurality of chips, each chip having an electrical connection surface and a magnetic attraction surface opposite to the electrical connection surface, wherein the plurality of magnetic attraction surfaces respectively correspond to the plurality of magnets and are attached to the part of the first side; After the plurality of magnetic attraction surfaces respectively correspond to the plurality of magnets and are attached to the part of the first side, filling the filling layer into the initial cavity and between the plurality of chips and covering the plurality of electrical connection surfaces; And Removing the adhesive layer and the carrier plate.

9. The manufacturing method of the circuit board according to claim 8, characterized in that, It further includes: After removing the adhesive layer and the carrier plate, forming a substrate on the initial plate body to form a plate body, the substrate having an upper surface and a lower surface opposite to the upper surface, the plate body having a cavity and a dielectric layer, wherein the substrate and the dielectric layer define the cavity, and each magnetic attraction surface is closer to the upper surface than each electrical connection surface.

10. The manufacturing method of the circuit board according to claim 9, characterized in that, It further includes: After forming the substrate, forming a power line layer on the lower surface; and Forming a signal line layer on the filling layer, the signal line layer passing through the filling layer to electrically connect the plurality of electrical connection surfaces.

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