A high-temperature resistant VDMOS power transistor for extreme environments and its preparation method

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a high-temperature resistant VDMOS power transistor for use in extreme environments and a method for preparing the same. The transistor comprises a plurality of juxtaposed MOS cells, each of which includes a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a lower P+ layer, a P-well layer, and an N-well layer. Side P+ layers are formed on both sides of the MOS cell and between the source and the lower P+ layer by ion implantation. The side P+ layers are axially symmetrical with the N-well layer, and the combined cross-sectional profile of the side P+ layers and the N-well layer is in the shape of a "concave" character. The present invention utilizes an axially symmetrical "concave" deep junction structure formed by the side P+ layers and the N-well layer to significantly enhance the lateral expansion capability of the depletion region and reduce the parasitic resistance of the P-well layer. This structure blocks the conduction path of the parasitic bipolar transistor and avoids latch-up at high temperatures.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a high-temperature resistant VDMOS power transistor for use in extreme environments and a preparation method thereof. Background Art

[0002] Traditional VDMOS power transistors exhibit significant drawbacks in extreme high-temperature environments: First, parasitic resistance in the P-well can easily trigger latch-up, leading to device failure. Second, electric field concentration in the JFET region can squeeze channel current and cause localized breakdown. Furthermore, the mismatch in thermal expansion coefficients at the metal-semiconductor interface can easily cause contact cracking during high-temperature cycling, and the right-angle structure creates stress concentration points. Furthermore, long body diode reverse recovery time, high switching losses, and excessive drain-side electric field peaks further limit device reliability and power density in high-temperature, high-voltage environments.

[0003] An existing patent discloses a high-avalanche-resistant vertical double-diffused MOS (CN215771155U). It comprises an N-type substrate region and an N-epitaxial layer arranged from bottom to top. P-well regions are located on the left and right sides of the upper N-epitaxial layer. N buried layers are located directly below the P-well regions. N+ source regions are located within each P-well region. A front metal electrode region is located on the upper surface at the junction of the two P-well regions and the central N-epitaxial layer. A metal pre-substrate (BPSG) is located below the front metal electrode region. This existing technology struggles to balance high-temperature stability, voltage resistance, and heat dissipation performance, failing to meet the demands of applications in extreme environments such as aerospace and geothermal drilling. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a high-temperature resistant VDMOS power transistor for use in extreme environments and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-temperature resistant VDMOS power transistor for use in extreme environments is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell includes a drain, a semiconductor epitaxial layer, a gate, and a source, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a lower P+ layer, a P-well layer, and an N-well layer, and side P+ layers are formed on both sides of the single MOS cell and located between the source and the lower P+ layer by ion implantation; the side P+ layers are axially symmetrically distributed with the N-well layer, wherein the cross-sectional profile of the combination of the side P+ layers and the N-well layer is in the shape of a "concave" character;

[0006] The cross-sectional profile of the source is an inverted "L" shape, wherein the source includes a transverse portion and a longitudinal portion, and the longitudinal portion of the source is adapted to the concave portion after the side P+ layer and the N well layer are combined.

[0007] Furthermore, N-type fan-shaped layers are formed on both sides of the N-drift layer in a single MOS cell and in a top region close to the P-well layer by ion implantation.

[0008] Furthermore, rectangular P- layers are formed on both sides of the N drift layer in a single MOS cell and below the lower P+ layer by ion implantation, and the rectangular P- layers are in direct contact with the lower P+ layer.

[0009] Furthermore, rectangular polysilicon layers are deposited on both sides of the N substrate layer in a single MOS cell, and the rectangular polysilicon layers are in ohmic contact with the drain.

[0010] Furthermore, the N substrate layer further includes a recessed N substrate, and the junction between the recessed N substrate and the N drift layer is recessed;

[0011] A triangular polysilicon layer is deposited on both sides of the recessed N substrate in a single MOS cell, and the triangular polysilicon layer is in ohmic contact with the drain.

[0012] Furthermore, the N substrate layer further includes a curved N substrate, and the drain further includes an arc-shaped drain.

[0013] Furthermore, the intersection of the curved N substrate and the N drift layer, and the intersection of the curved N substrate and the arc-shaped drain are both in the shape of concave arcs, and the arcs of the two intersections have the same curvature.

[0014] A method for preparing a high-temperature resistant VDMOS power transistor for use in extreme environments, comprising the following steps:

[0015] S1. The N substrate layer is etched to form a recessed N substrate or a curved N substrate structure, and an N drift layer is epitaxially grown on the substrate;

[0016] S2. Perform P-type ion implantation between the source and the lower P+ layer to form an axisymmetric "concave"-shaped profile that matches the N-well layer;

[0017] S3, implanting N-type ions into the top region of the P-well layer on both sides of the N-drift layer to form an N-type fan-shaped layer;

[0018] S4, implanting P-type ions on both sides of the N drift layer and below the lower P+ layer to form a rectangular P- layer;

[0019] S5, depositing a triangular polysilicon layer on both sides of the recessed N substrate or simultaneously preparing an arc-shaped drain for the curved N substrate;

[0020] S6, first depositing a longitudinal portion to fill the recessed area of ​​the side P+ layer and the N-well layer, and then forming a transverse portion to cover the surface of the P-well layer;

[0021] S7. The drain and source are deposited on the surface of the semiconductor epitaxial layer by vapor deposition.

[0022] The present invention provides a high-temperature resistant VDMOS power transistor for use in extreme environments and a preparation method thereof. Compared with the prior art, the present method has the following effects:

[0023] 1. The present invention significantly enhances the lateral expansion capability of the depletion region and reduces the parasitic resistance of the P-well layer through the axially symmetrical "concave"-shaped deep junction structure formed by the side P+ layer and the N-well layer. This structure blocks the conduction path of the parasitic bipolar transistor and avoids the latch-up effect at high temperatures. At the same time, the longitudinal part of the inverted L-shaped source is filled with the "concave"-shaped depression area, which increases the contact area between the source and the P+ region and reduces the contact resistance. The lateral part covers the P-well surface, optimizes the carrier lateral conduction path, and improves the current density and high-temperature stability.

[0024] 2. The present invention implants a gradually doped N-type fan-shaped layer on both sides of the top of the P-well layer. The fan-shaped profile disperses the electric field peak of the JFET region in the traditional VDMOS, avoiding the squeezing of the channel current. This design balances the electric field distribution, prevents premature breakdown caused by local high electric fields, and at the same time widens the carrier channel, improving the reliability of the device in high temperature and high pressure environments.

[0025] 3. The present invention reduces impurity mutation by injecting a lightly doped rectangular P- layer at the bottom of the N-drift layer as a concentration gradient buffer between the lower P+ layer and the N-drift layer. This effectively suppresses minority carrier injection at high temperatures, shortens the body diode reverse recovery time, reduces switching losses, reduces high-temperature leakage current, and improves dynamic performance.

[0026] 4. The present invention deposits rectangular polysilicon layers on both sides of the N substrate layer to replace the traditional metal-semiconductor direct contact. The polysilicon layer alleviates the mismatch of thermal expansion coefficients, avoids cracking of the metal / semiconductor interface during high-temperature cycles, and maintains the stability of the ohmic contact; at the same time, it increases the drain heat dissipation area, reduces thermal resistance, and improves power density.

[0027] 5. The present invention extends the lateral expansion path of the depletion region through a recessed N-substrate structure to disperse the concentrated electric field at the drain end; the deposited triangular polysilicon layer fills the recessed sidewalls to further increase the drain heat dissipation area, and the two work together to reduce the peak electric field at the drain end, increase the breakdown voltage, and optimize the high-temperature heat dissipation capability, making it suitable for high-power application scenarios.

[0028] 6. The present invention adopts a matching curvature design by bending the N substrate and the arc-shaped drain to eliminate the stress concentration points of the traditional right-angle structure, avoid interface cracking caused by high-temperature thermal expansion, and simultaneously optimize the current distribution at the arc intersection to reduce local Joule heat generation, thereby improving the structural integrity and long-term reliability of the device under extreme temperature cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the second embodiment of the present invention;

[0031] Figure 3 Schematic diagram of implementation three of the present invention;

[0032] Figure 4 Schematic diagram of the fourth embodiment of the present invention;

[0033] Figure 5 is a schematic diagram of a fifth embodiment of the present invention;

[0034] Figure 6 Schematic diagram of implementation six of the present invention.

[0035] In the figure: 1. drain; 2. gate; 3. source; 4. N substrate layer; 5. N drift layer; 6. side P+ layer; 7. lower P+ layer; 8. P well layer; 9. N well layer; 10. N-type fan-shaped layer; 11. rectangular P- layer; 12. rectangular polysilicon layer; 13. triangular polysilicon layer; 41. recessed N substrate; 42. curved N substrate; 101. arc-shaped drain. DETAILED DESCRIPTION

[0036] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1-6 As shown, a method for preparing a high-temperature resistant VDMOS power transistor for use in extreme environments comprises the following steps:

[0038] Step 1: The N substrate layer 4 is etched to form a recessed N substrate 41 or a curved N substrate 42 structure, and an N drift layer 5 is epitaxially grown on the substrate; the recessed or curved N substrate structure (recessed N substrate 41 / curved N substrate 42) is formed by etching, which extends the lateral extension path of the depletion region and disperses the electric field concentration ( Figure 5-6 The curved substrate matches the arc of the arc-shaped drain to eliminate right-angle stress points and prevent interface cracking caused by high-temperature thermal expansion (Example 6). The epitaxially grown N drift layer 5 provides the main voltage-resistant region.

[0039] Step 2: P-type ion implantation is performed between the source 3 and the lower P+ layer 7 to form an axisymmetric "concave" shaped profile that matches the N-well layer 9. The axisymmetric "concave" shaped side P+ layer 6 and the N-well layer 9 form a deep junction structure ( Figure 1 ), enhance the expansion of the depletion region, reduce the parasitic resistance (Rsb) of the P-well layer 8, and block the conduction path of the parasitic bipolar transistor (Example 1). The groove structure provides an adaptation space for the subsequent inverted L-shaped source;

[0040] Step 3: Inject N-type ions into the top area of ​​the P-well layer 8 on both sides of the N-drift layer 5 to form an N-type fan-shaped layer 10; Inject the N-type fan-shaped layer 10 with a gradient doping on both sides of the P-well top ( Figure 2 ), whose fan-shaped profile disperses the electric field peak of the JFET region in the traditional VDMOS, avoids the channel current from being squeezed, and optimizes the electric field distribution to prevent local breakdown (Example 2).

[0041] Step 4: Inject P-type ions on both sides of the N drift layer 5 and below the lower P+ layer 7 to form a rectangular P- layer 11; Inject lightly doped rectangular P- layer 11 below the lower P+ layer 7 ( Figure 3 ), serving as a concentration gradient buffer, reduces the impurity mutation between the N drift layer 5 and the lower P+ layer 7. It suppresses minority carrier injection at high temperatures and shortens the body diode reverse recovery time (trr) (Example 3).

[0042] Step 5: Deposit a triangular polysilicon layer 13 on both sides of the recessed N substrate 41 or simultaneously prepare an arc-shaped drain 101 for the curved N substrate 42; deposit a triangular polysilicon layer 13 in the recessed N substrate 41 to fill the sidewalls ( Figure 5 ), increasing the drain heat dissipation area, and cooperating with the recessed structure to reduce the drain end electric field peak (Example 5). In the curved N substrate 42, a curved drain 101 is simultaneously prepared, and the curvature matches the substrate curvature ( Figure 6 ), eliminating stress concentration, optimizing current distribution and reducing Joule heat (Example 6).

[0043] Step 6: Deposit a longitudinal portion to fill the recessed areas between the P+ layer 6 and the N-well layer 9, then deposit a transverse portion to cover the surface of the P-well layer 8. Deposit the longitudinal portion to fill the "concave"-shaped recessed area, increasing the contact area between the source 3 and the P+ region and reducing contact resistance. Then, deposit a transverse portion to cover the surface of the P-well layer 8, providing a low-resistance lateral conduction path (Example 1). The inverted L-shaped structure is perfectly compatible with the concave P+ / N-well.

[0044] Step 7: Vapor-deposit the drain 1 and source 3 on the surface of the semiconductor epitaxial layer. Vapor deposition of the drain 1 and source 3 on the semiconductor surface, combined with the aforementioned polysilicon buffer layer (Step 5) and the curved design (Example 6), prevents cracking at the metal-semiconductor interface during high-temperature cycling and maintains ohmic contact reliability.

[0045] Example 1

[0046] like Figure 1As shown, according to one aspect of the present invention, a high-temperature resistant VDMOS power transistor for use in extreme environments is provided, comprising a plurality of MOS cells arranged in parallel, wherein a single MOS cell comprises a drain 1, a semiconductor epitaxial layer, a gate 2, and a source 3, the semiconductor epitaxial layer comprises an N substrate layer 4, an N drift layer 5, a lower P+ layer 7, a P well layer 8, and an N well layer 9, side P+ layers 6 are formed on both sides of the single MOS cell and located between the source 3 and the lower P+ layer 7 by ion implantation; the side P+ layers 6 and the N well layer 9 are axially symmetrically distributed, wherein the cross-sectional profile of the side P+ layers 6 and the N well layer 9 after combination is in the shape of a "concave"; the cross-sectional profile of the source 3 is an inverted "L" shape, wherein the source 3 comprises a transverse portion and a longitudinal portion, and the longitudinal portion of the source 3 is adapted to the concave portion after the side P+ layers 6 and the N well layer 9 are combined. The side P+ layer 6 and the N-well layer 9 form an axisymmetric "concave" shape, and the deep junction structure of the P+ / N-well is used to enhance the expansion of the depletion region, reduce the parasitic resistance (Rsb) of the P-well layer (8), inhibit the conduction of the parasitic bipolar transistor, and avoid high-temperature latch-up.

[0047] At the same time, the longitudinal part of the inverted L-shaped source 3 is filled with the "concave" depression area, which expands the contact area between the source and the P+ region and reduces the source contact resistance; the transverse part covers the P-well surface, optimizes the carrier transverse conduction path, and improves the current capacity.

[0048] Example 2

[0049] like Figure 2 As shown, N-type fan-shaped layers 10 are formed by ion implantation on both sides of the N-drift layer 5 in a single MOS cell, near the top of the P-well layer 8. N-type fan-shaped layers 10 are located on both sides of the top of the P-well and are implanted in a gradient-doped fan-shaped pattern. This weakens the JFET effect on channel current in traditional VDMOS and widens the carrier channel. The fan-shaped profile disperses electric field peaks, preventing localized breakdown and improving high-temperature reliability.

[0050] Example 3

[0051] like Figure 3 As shown, rectangular P-layers 11 are formed on both sides of the N-drift layer 5 in a single MOS cell, beneath the lower P+ layer 7, through ion implantation. These rectangular P-layers 11 are in direct contact with the lower P+ layer 7. These rectangular P-layers 11, placed in close contact with the lower P+ layer 7, act as a lightly doped buffer zone, reducing the impurity concentration gradient between the N-drift layer 5 and the lower P+ layer 7. This suppresses minority carrier injection at high temperatures, shortens the body diode reverse recovery time (trr), and reduces switching losses.

[0052] Example 4

[0053] like Figure 4As shown, rectangular polysilicon layers 12 are deposited on both sides of the N substrate layer 4 in a single MOS cell. These rectangular polysilicon layers 12 form an ohmic contact with the drain electrode 1. These rectangular polysilicon layers 12 are deposited on both sides of the N substrate 4, forming an ohmic contact with the metal drain electrode 1, replacing the traditional direct metal-semiconductor contact. The polysilicon layer mitigates thermal expansion coefficient mismatch, prevents cracking at the contact interface during high-temperature cycling, and improves thermal stability.

[0054] Example 5

[0055] like Figure 5 As shown, the N substrate layer 4 also includes a recessed N substrate 41, with the junction between the recessed N substrate 41 and the N drift layer 5 forming a concave shape. In a single MOS cell, a triangular polysilicon layer 13 is deposited on both sides of the recessed N substrate 41, making ohmic contact with the drain 1. The recessed structure in the recessed N substrate 41 and the triangular polysilicon layer 13 extends the lateral extension path of the depletion region, dispersing the electric field concentration. The triangular polysilicon layer 13 fills the sidewalls of the recess, increasing the drain heat dissipation area. These two structures work together to reduce the peak electric field at the drain, improving the breakdown voltage (BVdss) and high-temperature heat dissipation capability.

[0056] Example 6

[0057] like Figure 6 As shown, the N substrate layer 4 also includes a curved N substrate 42, and the drain 1 also includes a curved drain 101. The intersections of the curved N substrate 42 with the N drift layer 5 and the curved drain 101 are both concave arcs, with the curvature of the two intersections being identical. The curved N substrate 42 and the curved drain 101 match their curvatures, and the curved intersection eliminates stress concentration points found in traditional right-angle structures, preventing interfacial cracks caused by differential thermal expansion at high temperatures. The curved drain 101 also optimizes current distribution and reduces local Joule heating.

[0058] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A high-temperature resistant VDMOS power transistor for use in extreme environments, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a gate (2) and a source (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), a lower P+ layer (7), a P well layer (8) and an N well layer (9), and wherein: Side P+ layers (6) are formed on both sides of a single MOS cell and located between the source (3) and the lower P+ layer (7) by ion implantation; the side P+ layers (6) and the N-well layer (9) are axially symmetrically distributed, wherein the cross-sectional profile of the side P+ layers (6) and the N-well layer (9) after being combined is in a "concave" shape; The cross-sectional profile of the source electrode (3) is an inverted "L" shape, wherein the source electrode (3) comprises a transverse portion and a longitudinal portion, and the longitudinal portion of the source electrode (3) is adapted to a recessed portion formed by combining the side P+ layer (6) and the N well layer (9).

2. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 1, characterized in that: An N-type fan-shaped layer (10) is formed on both sides of the N drift layer (5) in a single MOS cell and in a top region close to the P well layer (8) by ion implantation.

3. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 1, characterized in that: A rectangular P-layer (11) is formed on both sides of the N drift layer (5) in a single MOS cell and below the lower P+ layer (7) by ion implantation, and the rectangular P-layer (11) is in direct contact with the lower P+ layer (7).

4. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 1, characterized in that: Rectangular polysilicon layers (12) are deposited on both sides of the N substrate layer (4) in a single MOS cell, and the rectangular polysilicon layer (12) is in ohmic contact with the drain (1).

5. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 1, characterized in that: The N substrate layer (4) further includes a recessed N substrate (41), and the junction between the recessed N substrate (41) and the N drift layer (5) is recessed; A triangular polysilicon layer (13) is deposited on both sides of the recessed N substrate (41) in a single MOS cell, and the triangular polysilicon layer (13) is in ohmic contact with the drain (1).

6. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 1, characterized in that: The N substrate layer (4) further includes a curved N substrate (42), and the drain (1) further includes an arc-shaped drain (101).

7. The high temperature resistant VDMOS power transistor for use in extreme environments according to claim 6, characterized in that: The intersection of the curved N substrate (42) and the N drift layer (5), and the intersection of the curved N substrate (42) and the arc-shaped drain (101) are both in the shape of a concave arc, and the arcs of the two intersections are the same.

8. A method for preparing a high-temperature resistant VDMOS power transistor for use in extreme environments, characterized in that: The method for preparing the VDMOS power transistor according to any one of claims 1 to 7, wherein the method comprises the following steps: S1, N substrate layer (4) is formed into a recessed N substrate (41) or a curved N substrate (42) structure through an etching process, and an N drift layer (5) is epitaxially grown on the substrate; S2, performing P-type ion implantation between the source (3) and the lower P+ layer (7) to form an axisymmetric "concave"-shaped profile that matches the N-well layer (9); S3, injecting N-type ions into the top region of the P-well layer (8) on both sides of the N-drift layer (5) to form an N-type fan-shaped layer (10); S4, implanting P-type ions on both sides of the N drift layer (5) and below the lower P+ layer (7) to form a rectangular P- layer (11); S5, depositing a triangular polysilicon layer (13) on both sides of the recessed N substrate (41) or simultaneously preparing an arc-shaped drain (101) for the curved N substrate (42); S6, first depositing a longitudinal portion to fill the recessed area of ​​the side P+ layer (6) and the N well layer (9), and then forming a lateral portion to cover the surface of the P well layer (8); S7. The drain electrode (1) and the source electrode (3) are deposited on the surface of the semiconductor epitaxial layer by vapor deposition.

Images