Method for optimizing SiGe-SMT process
The optimized SiGe-SMT process simplifies the SiGe-SMT process by using a tensile stress silicon nitride layer as an etch mask for PMOS processing, reducing steps and enhancing device performance while avoiding PMOS stress transfer issues.
Patent Information
- Application Number
- CN202510331284.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-15
AI Technical Summary
There are many processes in the existing SiGe-SMT process, resulting in high manufacturing costs and the tensile stress silicon nitride layer covers the PMOS region and affects its performance.
The tensile stress silicon nitride layer is used as the etching mask, and diamond trench etching and silicon germanium growth are performed after removal of the PMOS area. After rapid heat treatment, the tensile stress is transferred to the NMOS area, eliminating the SMT process steps after source/drain ion implantation.
Simplifies the process flow, improves device performance, avoids negative impacts on the PMOS area, and reduces manufacturing costs.
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a method for optimizing the SiGe-SMT process. Background Art
[0002] In the 28nm and below process nodes, the gate structure of CMOS devices usually adopts a high-k metal gate (HKMG ， High-K Metal Gate). In order to obtain high-performance CMOS devices, the SiGe-SMT process is usually adopted in the prior art, that is, the SiGe process (embedded germanium silicon process) is used to apply compressive stress to the PMOS to improve the hole mobility, and the SMT process (Stress Memorization Technique) is used to apply tensile stress to the NMOS to improve the electron mobility, so as to achieve the purpose of improving the electrical performance of the device.
[0003] In the traditional high-performance SiGe CMOS process, generally the SiGe process is carried out first and then the SMT process. The SiGe process is to form a hard mask layer on the surface of the substrate with the gate structure formed, remove the hard mask layer in the PMOS region, and then carry out the etching of diamond trenches (Sigma type) and the germanium silicon growth process; after that, the SMT process will be carried out after the source / drain ion implantation, that is, a layer of silicon nitride layer with tensile stress (SMT SiN) is deposited on the NMOS and PMOS regions as a whole, and then the tensile stress is applied to the channel of the device through rapid thermal annealing (RTA), and then the silicon nitride layer is removed.
[0004] In the above SiGe-SMT process flow, it is necessary to carry out multiple processes of growing and removing the silicon nitride layer, and the process steps are more, resulting in a relatively high manufacturing cost; on the other hand, a tensile stress silicon nitride layer will also be formed on the PMOS region in the SMT process, and the stress will also be transmitted to the PMOS after rapid thermal annealing, which will also affect the performance of the PMOS device to a certain extent.
[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of this application. Summary of the Invention
[0006] The purpose of the present invention is to provide a method for optimizing the SiGe-SMT process to reduce the preparation process in the prior art and improve the device performance.
[0007] To solve the above problems, the following provides a method for optimizing the SiGe-SMT process, including the following steps:
[0008] S1. Provide a substrate to be subjected to the SiGe process. An isolation structure, a gate structure, and a first sidewall are formed on the substrate. The substrate includes a PMOS region and an NMOS region;
[0009] S2. Deposit a tensile stress silicon nitride layer on the surface of the substrate;
[0010] S3. Remove the tensile stress silicon nitride layer on the PMOS region. Using the remaining tensile stress silicon nitride layer as an etching mask, form diamond trenches in the PMOS region through an etching process and then perform germanium silicon growth;
[0011] S4. Perform rapid thermal annealing on the substrate to apply the stress of the remaining tensile stress silicon nitride layer to the NMOS region;
[0012] S5. Remove the remaining tensile stress silicon nitride layer;
[0013] S6. Form source and drain electrodes.
[0014] In this application, by improving the existing SiGe process flow and using the tensile stress silicon nitride layer as an etching mask, the etching of diamond trenches and the growth of germanium silicon can be carried out according to the existing SiGe process flow, realizing the application of compressive stress to the PMOS region; on the other hand, after the germanium silicon growth is completed, rapid thermal annealing is directly performed, and the tensile stress of the tensile stress silicon nitride layer can be transferred to the NMOS region without affecting the PMOS region. Compared with the prior art, the process steps are reduced, and at the same time, the side effects of the tensile stress silicon nitride layer on the PMOS are avoided.
[0015] In step S1, the formation process of the substrate to be subjected to the SiGe process includes: providing a silicon substrate, forming an isolation structure in the silicon substrate; performing well ion implantation to form an N-type well and a P-type well in the silicon substrate; respectively forming gate structures on the N-type well region and the P-type well region; forming a first sidewall; performing light doping implantation and thermal annealing treatment.
[0016] In step S2, the tensile stress silicon nitride layer is formed by chemical vapor deposition.
[0017] In step S3, the process of removing the tensile stress silicon nitride layer on the PMOS region includes: coating a photoresist layer on the surface of the substrate; performing patterning treatment on the photoresist layer to obtain a photoresist mask; using the photoresist mask as an etching mask and removing the tensile stress silicon nitride layer on the PMOS region by dry etching.
[0018] In step S3, the process of forming diamond trenches in the PMOS region through an etching process includes: using the remaining tensile stress silicon nitride layer as an etching mask, first performing a first etching to form U-shaped or spherical trenches; then performing a second etching to further etch the U-shaped or spherical trenches to form diamond trenches.
[0019] The first etching is a dry etching; the second etching is a wet etching, and the etching solution for the wet etching is a tetramethylammonium hydroxide etching solution.
[0020] After forming the diamond trenches, germanium-silicon growth is carried out through an epitaxial process to fill the diamond trenches.
[0021] In step S5, the remaining tensile stress silicon nitride layer is removed through wet etching with a hot phosphoric acid solution.
[0022] In step S6, the process of forming the source and drain includes: forming a second sidewall; performing heavy doping implantation for the source and drain; performing a thermal annealing treatment.
[0023] The second sidewall includes a silicon dioxide layer and a silicon nitride layer.
[0024] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) Simplifying the process flow: By using the tensile stress silicon nitride layer as an etching mask layer in the SiGe process, the etching of diamond trenches and the growth of germanium-silicon can be carried out normally, realizing the application of compressive stress to the PMOS region. After the germanium-silicon growth is completed, through rapid thermal processing, the tensile stress of the tensile stress silicon nitride layer can be transferred to the NMOS region without affecting the PMOS region. Therefore, the SMT process step after the source / drain ion implantation process in the original process can be omitted, realizing the simplification of the process; 2) Improving the performance of the device: The tensile stress silicon nitride grown by the SMT process in the prior art will cover the PMOS region and thus have certain side effects on it, while this is improved in the present application. When performing stress transfer, the tensile stress silicon nitride only covers the NMOS region, so the performance of the device can be improved. Description of the Drawings
[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for use in the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0026] Figure 1 It is a schematic diagram of the SiGe process flow in the prior art.
[0027] Figure 2It is a schematic diagram of the SMT process flow in the prior art.
[0028] Figure 3 It is a flowchart of an optimized SiGe-SMT process provided by the present invention.
[0029] Figure 4 It is a schematic diagram of an optimized SiGe-SMT process flow provided by the present invention. Detailed implementation manners
[0030] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.
[0031] The following will elaborate on the embodiments of the present application in conjunction with the drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed for the better understanding of the present application by readers. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be realized.
[0032] The steps in the following embodiments do not correspond one by one to the content of the invention.
[0033] Reference Figure 1 - Figure 2 What is shown is the SiGe-SMT process in the prior art. Reference Figure 1 As shown, at this time, the preparation of the gate structure has been completed, and the SiGe process (embedded germanium silicon process) flow is to be carried out.
[0034] For the convenience of understanding, the previous steps are briefly introduced, but it should not be regarded as a limitation to the technical solution provided by the present invention. Specifically, the previous steps generally include the following: 1) providing a substrate 1 and forming an isolation structure 2 in the substrate 1; 2) performing well ion implantation to form an N-type well and a P-type well respectively; 3) correspondingly forming a gate structure 3 in the N-type well and P-type well regions, and the gate structure 3 usually includes a gate oxide dielectric layer and a gate material layer, or it can also be an HKMG structure; 4) forming a first sidewall 4; 5) performing light doping implantation (LDD process) and thermal annealing treatment.
[0035] When the above previous steps are completed, that is, when the SiGe process is to be carried out. Specifically, reference Figure 1 As shown, the SiGe process generally includes the following steps: 1) depositing a layer of silicon nitride on the substrate surface as a germanium silicon hard mask layer 5, and the result is shown in reference Figure 1a in; 2) Using photolithography and etching processes, remove the germanium-silicon hard mask layer 5 in the PMOS region, and the result is shown in Figure 1 b as shown in; 3) Using the remaining germanium-silicon hard mask layer 5 as an etching mask, form diamond trenches 6 (Sigma-type trenches) on both sides of the gate structure of the PMOS through the etching process, and the result is shown in Figure 1 b as shown in; 4) Perform germanium-silicon epitaxial growth to fill the diamond trenches 6, and the result is shown in Figure 1 b as shown in; 5) Remove the remaining germanium-silicon hard mask layer 5, and the result is shown in Figure 1 c as shown in. So far, the SiGe process is completed.
[0036] After the SiGe process is completed, a source / drain ion implantation process is generally performed, that is, heavy doping is performed again on the basis of the LDD region to form a source 8 and a drain 9. This step usually includes forming a second sidewall 7 and then performing heavy doping and thermal annealing treatments.
[0037] After the source / drain ion implantation is completed, the SMT process is performed. Specifically, referring to Figure 2 as shown, the SMT process generally includes the following steps: 1) Deposit a tensile stress silicon nitride layer 10 (Tensile stress SiN) on the surface of the substrate 1, and this tensile stress silicon nitride layer 10 covers both the NMOS region and the PMOS region at the same time, and the result is shown in Figure 2 a as shown in; 2) Perform rapid thermal annealing (RTA ， Rapid Thermal Annealing) on the substrate 1 to apply the stress of the tensile stress silicon nitride layer 10 to the channel of the device; 3) Remove the tensile stress silicon nitride layer 10, and the result is shown in Figure 2 b as shown in. So far, the SMT process is completed.
[0038] In summary, in order to improve the device performance, in the existing SiGe-SMT process flow, there are at least two depositions and removals of silicon nitride (including the deposition and removal of the germanium-silicon hard mask layer 5 in the SiGe process, and the deposition and removal of the tensile stress silicon nitride layer 10 in the SMT process). The process steps are numerous, resulting in a relatively high manufacturing cost; on the other hand, in the SMT process, the tensile stress silicon nitride layer 10 will cover the PMOS region, and the stress will also be transmitted to the PMOS after rapid thermal annealing, which will also affect the performance of the PMOS device to a certain extent.
[0039] Example 1:
[0040] Referring to Figure 3 and Figure 4 , in order to reduce the existing process flow and improve the device performance, a method for optimizing the SiGe-SMT process is provided in this application, including the following steps:
[0041] Step 1: Provide a substrate 1 to be subjected to a SiGe process. An isolation structure 2, a gate structure 3, and a first sidewall 4 are formed on the substrate 1. The substrate 1 includes a PMOS region and an NMOS region.
[0042] Reference Figure 4 As shown in a of [reference], it can be understood that the substrate 1 provided in this Step 1 is the substrate that has completed the previous steps. The previous steps generally include the following: 1) Provide the substrate 1 and form a shallow trench isolation structure in the substrate 1; 2) Perform well ion implantation to form an N-type well and a P-type well respectively; 3) Correspondingly form the gate structure 3 in the N-type well and P-type well regions. The gate structure 3 generally includes a gate oxide dielectric layer and a gate material layer, or can also be an HKMG structure; 4) Form the first sidewall 4; 5) Perform light doping implantation (LDD process) and thermal annealing treatment.
[0043] Step 2: Deposit a tensile stress silicon nitride layer 10 on the surface of the substrate 1 as a hard mask layer.
[0044] Reference Figure 4 As shown in a of [reference], deposit a layer of tensile stress silicon nitride layer 10 (Tensile stress SiN) on the surface of the substrate 1 as a hard mask layer for subsequent processes. The tensile stress silicon nitride layer 10 covers both the NMOS region and the PMOS region at the same time. In this application, the formation process (such as using chemical vapor deposition process) and specific structure of the tensile stress silicon nitride layer 10 are not limited. Specific process parameters can be determined according to actual situations. Generally, the thickness of the tensile stress silicon nitride layer 10 can be between 200 and 250 Å (angstroms).
[0045] Step 3: Remove the tensile stress silicon nitride layer 10 in the PMOS region.
[0046] Reference Figure 4 As shown in a and b of [reference], use photolithography and etching processes to remove the tensile stress silicon nitride layer 10 in the PMOS region, so as to etch the silicon substrate and grow germanium silicon in the opened area of the hard mask layer in the subsequent steps, and at the same time, it can also avoid negative impacts on the PMOS region during the subsequent strain memory process.
[0047] Specifically, coat a photoresist layer on the surface of the substrate 1. The photoresist layer covers the tensile stress silicon nitride layer 10, and the surface of the photoresist layer extends beyond the surface of the gate structure 3; perform patterning on the photoresist layer to obtain a photoresist mask. The patterning process includes: using a suitable photomask, first perform exposure treatment on the photoresist layer, and then perform development treatment to remove the photoresist layer on the surface of the tensile stress silicon nitride layer 10 in the PMOS region and other steps. The result is as Figure 4as shown in a of [reference]; using the photoresist mask as the etching mask, the tensile stress silicon nitride layer 10 in the PMOS region is removed by dry etching process, and the result is as shown in Figure 4 b of [reference].
[0048] Step 4: Etch diamond trenches 6 in the PMOS region.
[0049] Continue to refer to Figure 4 b of [reference]. Using the remaining tensile stress silicon nitride layer 10 as the etching mask, diamond trenches 6 (Sigma-type trenches) are formed on both sides of the gate structure 3 of the PMOS through the etching process. This etching process usually includes two etching steps. First, the first etching is carried out to form a U-shaped or spherical trench; then the second etching is carried out to further etch the U-shaped or spherical trench to form a Sigma-type trench. Among them, the first etching can be dry etching; the second etching is anisotropic etching, and the side surfaces of the U-shaped or spherical trench are gradually expanded by using the etching rate difference of different crystal planes of the substrate to form a Sigma-type profile, usually wet etching is carried out using an etching solution such as TMAH (tetramethylammonium hydroxide).
[0050] Step 5: Perform GeSi deposition.
[0051] Perform GeSi epitaxial growth to fill the diamond trenches 6, and the result is as shown in b of reference Figure 4 shown.
[0052] Step 6: Perform rapid thermal annealing on the substrate.
[0053] Perform rapid thermal annealing (RTA ， Rapid Thermal Annealing) on the substrate 1 to apply the stress of the tensile stress silicon nitride layer 10 to the channel of the device. During this process, since the tensile stress silicon nitride layer 10 in the PMOS region has been removed in Step 3, the stress of the tensile stress silicon nitride layer 10 will only be applied to the channel of the NMOS and will not affect the PMOS region, thereby achieving performance improvement.
[0054] Step 7: Remove the remaining tensile stress silicon nitride layer 10.
[0055] Refer to Figure 3 c of [reference]. After rapid thermal annealing, the remaining tensile stress silicon nitride layer 10 can be removed, and the removal method can be wet etching using a hot phosphoric acid solution.
[0056] So far, the main processes of a method for optimizing the SiGe-SMT process provided by this application have been completed. Subsequently, the source and drain can be formed, and there is no need to perform the SMT process in the existing process anymore.
[0057] The process of forming the source and drain generally includes: forming a second sidewall; performing source and drain heavy doping implantation; and performing a thermal annealing treatment. The second sidewall may include a silicon dioxide layer and a silicon nitride layer.
[0058] In order to reduce the existing processes and improve device performance, the existing SiGe-SMT process flow is optimized. First, the existing SiGe process is improved by using a tensile stress silicon nitride layer as the etching mask layer in the SiGe process. Then, the diamond trench can be etched and the germanium silicon can be grown according to the existing SiGe process flow, realizing the application of compressive stress to the PMOS region. On the other hand, after the germanium silicon growth is completed, a rapid thermal treatment is directly performed, and the tensile stress of the tensile stress silicon nitride layer can be transferred to the NMOS region without affecting the PMOS region (the tensile stress silicon nitride layer on this region has been removed). Secondly, since the effects of the SiGe-SMT process in the prior art have been achieved after the above steps, the SMT process step after the source / drain ion implantation process in the original process flow can be omitted, and the simplification of the process is realized.
[0059] Some commonly used English nouns or letters adopted in the present invention for the convenience of clear description are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.
[0060] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
Claims
1. A method for optimizing the SiGe - SMT process, characterized in that, The method includes the following steps: S1. Provide a substrate to be processed with SiGe process. An isolation structure, a gate structure and a first sidewall are formed on the substrate. The substrate includes a PMOS region and an NMOS region. S2. Deposit a tensile stress silicon nitride layer on the surface of the substrate. S3. Remove the tensile stress silicon nitride layer on the PMOS region. Using the remaining tensile stress silicon nitride layer as an etching mask, form diamond trenches in the PMOS region through an etching process and then perform GeSi growth. S4. Perform rapid thermal annealing on the substrate to apply the stress of the remaining tensile stress silicon nitride layer to the NMOS region. S5. Remove the remaining tensile stress silicon nitride layer. S6. Form source and drain electrodes.
2. The method for optimizing the SiGe-SMT process according to claim 1, wherein In step S1, the formation process of the substrate to be processed with SiGe process includes: Provide a silicon substrate and form an isolation structure in the silicon substrate. Perform well ion implantation to form an N-type well and a P-type well in the silicon substrate. Respectively form gate structures on the N-type well region and the P-type well region. Form a first sidewall. Perform light doping implantation and thermal annealing treatment.
3. A method for optimizing the SiGe-SMT process according to claim 1, characterized in that, In step S2, the tensile stress silicon nitride layer is formed by chemical vapor deposition process.
4. A method for optimizing the SiGe - SMT process according to claim 1, characterized in that, In step S3, the process of removing the tensile stress silicon nitride layer on the PMOS region includes: Coat a photoresist layer on the surface of the substrate. Perform patterning on the photoresist layer to obtain a photoresist mask. Using the photoresist mask as an etching mask, remove the tensile stress silicon nitride layer on the PMOS region by dry etching process.
5. A method for optimizing the SiGe-SMT process according to claim 1, characterized in that, In step S3, the process of forming diamond trenches in the PMOS region through an etching process includes: Using the remaining tensile stress silicon nitride layer as an etching mask, first perform a first etching to form a U-shaped or spherical trench. Then perform a second etching to further etch the U-shaped or spherical trench to form diamond trenches.
6. A method for optimizing the SiGe-SMT process according to claim 5, characterized in that, The first etching is dry etching. The second etching is wet etching, and the etching solution for the wet etching is tetramethylammonium hydroxide etching solution.
7. A method for optimizing the SiGe-SMT process according to claim 6, characterized in that After forming the diamond trenches, perform GeSi growth by epitaxial process to fill the diamond trenches.
8. A method for optimizing the SiGe-SMT process according to claim 1, characterized in that, In step S5, remove the remaining tensile stress silicon nitride layer by wet etching with hot phosphoric acid solution.
9. A method for optimizing the SiGe-SMT process according to claim 2, characterized in that, In step S6, the process of forming source and drain electrodes includes: Form a second sidewall. Perform source and drain heavy doping implantation. Perform thermal annealing treatment.
10. A method for optimizing the SiGe-SMT process according to claim 9, characterized in that, The second sidewall includes a silicon dioxide layer and a silicon nitride layer.