Integrated circuit device

Abstract

The integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; a nanosheet stack including a plurality of nanosheets on the fin-type active region; a gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction; and a vertical structure at least partially overlapping the gate line in the second horizontal direction, and including a sidewall in contact with each of the plurality of nanosheets. The vertical structure also includes a recess on a sidewall of the vertical structure.

Description

[0001] This application is based on and claims the priority of Korean Patent Application No. 10-2024-0005676, filed with the Korean Intellectual Property Office on January 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept generally relates to an integrated circuit device, and more particularly, to an integrated circuit device including a field effect transistor. Background Art

[0003] With the rapid development of the miniaturization of integrated circuit devices, it is necessary to ensure not only high-speed operation but also operation accuracy in integrated circuit devices. In addition, as the integration degree of integrated circuit devices increases and their size decreases, the possibility of process defects occurring during the manufacturing process of nanosheet field effect transistors may increase. Accordingly, it is necessary to develop an integrated circuit device having a new structure capable of eliminating (or reducing) the possibility of process defects and improving the performance and reliability of nanosheet field effect transistors. Summary of the Invention

[0004] As demonstrated by embodiments of the inventive concept, the inventive concept provides an integrated circuit device capable of providing stable performance and improved reliability in a nanosheet field effect transistor.

[0005] According to an aspect of the inventive concept, there is provided an integrated circuit device including: a fin-shaped active region extending in a first horizontal direction on a substrate; a nanosheet stack including a plurality of nanosheets disposed above the fin-shaped active region; a gate line extending above the fin-shaped active region around each of the plurality of nanosheets (i.e., extending around each of the plurality of nanosheets) and extending in a second horizontal direction crossing the first horizontal direction; and a vertical structure at least partially overlapping with the gate line in the second horizontal direction and including sidewalls in contact with each of the plurality of nanosheets, wherein the vertical structure further includes recesses on the sidewalls of the vertical structure.

[0006] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a substrate including a first region and a second region; a first fin-type active region extending in a first horizontal direction on the first region; a second fin-type active region extending in the first horizontal direction on the second region and separated from the first fin-type active region in a second horizontal direction intersecting the first horizontal direction; a plurality of first nanosheets facing a top surface of the first fin-type active region at a position separated from the top surface of the first fin-type active region; a plurality of second nanosheets facing a top surface of the second fin-type active region at a position separated from the top surface of the second fin-type active region; a first gate line surrounding each of the plurality of first nanosheets above the first fin-type active region and extending in the second horizontal direction; a second gate line surrounding each of the plurality of second nanosheets above the second fin-type active region and extending in the second horizontal direction; and a vertical structure between the first gate line and the second gate line and having two sidewalls respectively contacting each of the plurality of first nanosheets and each of the plurality of second nanosheets, wherein each of the two sidewalls of the vertical structure includes a recess recessed into the vertical structure, and each of the first gate line and the second gate line includes a protrusion extending into the recess.

[0007] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a substrate including a first region and a second region; a first fin-type active region extending in a first horizontal direction over the first region; a second fin-type active region extending in the first horizontal direction over the second region and spaced apart from the first fin-type active region in a second horizontal direction intersecting the first horizontal direction; a first nanosheet stack including a plurality of first nanosheets at different vertical heights each facing the top surface of the first fin-type active region at a position separated from the top surface of the first fin-type active region; a second nanosheet stack including a plurality of second nanosheets at different vertical heights each facing the top surface of the second fin-type active region at a position separated from the top surface of the second fin-type active region with respect to the upper surface of the substrate as a reference layer; a first gate line extending in the second horizontal direction around each of the plurality of first nanosheets above the first fin-type active region; a second gate line extending in the second horizontal direction around each of the plurality of second nanosheets above the second fin-type active region; a vertical structure between the first gate line and the second gate line and in contact with each of the plurality of first nanosheets and each of the plurality of second nanosheets; a first source / drain region adjacent to the first gate line and in contact with each of the plurality of first nanosheets; and a second source / drain region adjacent to the second gate line and in contact with each of the plurality of second nanosheets, wherein the first gate line includes: a first main metal layer; and a first work function metal layer between the first main metal layer and each of the plurality of first nanosheets and between the first main metal layer and the vertical structure, the second gate line includes: a second main metal layer; and a second work function metal layer between the second main metal layer and each of the plurality of second nanosheets and between the second main metal layer and the vertical structure, the vertical structure includes: an air space in the vertical structure, the vertical structure further includes a first sidewall and a second sidewall, the first sidewall faces the first gate line, the second sidewall faces the second gate line, the first sidewall includes a first recess, the second sidewall includes a second recess, the first work function metal layer includes a portion disposed in the first recess and at least partially overlapping the vertical structure in the vertical direction, and the second work function metal layer includes a portion in the second recess and at least partially overlapping the vertical structure in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which like reference numerals (when used) indicate corresponding elements in multiple views.

[0009] Figure 1 is a schematic plan layout diagram of some components of an integrated circuit device according to an embodiment.

[0010] Figure 2Ataken along line X1-X1 Figure 1 Schematic cross-sectional view of an integrated circuit device.

[0011] Figure 2B taken along line Y1-Y1 Figure 1 Schematic cross-sectional view of an integrated circuit device.

[0012] Figure 3 is Figure 2B An enlarged schematic cross-sectional view of region EX1 of the integrated circuit device shown in

[0013] Figures 4 to 6 An enlarged schematic cross-sectional view of an integrated circuit device according to an embodiment.

[0014] Figure 7 A schematic cross-sectional view of an integrated circuit device according to an embodiment.

[0015] Figure 8 A schematic cross-sectional view of an integrated circuit device according to an embodiment.

[0016] Figure 9 is Figure 8 An enlarged schematic cross-sectional view of region EX2 of the integrated circuit device shown in

[0017] Figure 10 and Figure 11 A schematic cross-sectional view of an integrated circuit device according to an embodiment.

[0018] Figures 12A to 12F A schematic cross-sectional view showing an intermediate process in an exemplary method of manufacturing an integrated circuit device according to an embodiment.

[0019] Figure 13A and Figure 13B A schematic cross-sectional view showing an intermediate process in an exemplary method of manufacturing an integrated circuit device according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

[0021] Figure 1 is a schematic plan layout of some components of an integrated circuit device 100 according to an embodiment. Figure 2A is taken along Figure 1 line X1-X1 of the integrated circuit device 100. Schematic cross-sectional view. Figure 2B is taken along Figure 1 line Y1-Y1 of the integrated circuit device 100. Schematic cross-sectional view. Figure 3 is Figure 2BSchematic enlarged cross-sectional view of the region EX1.

[0022] Hereinafter, with reference to Figure 1 , Figure 2A , Figure 2B and Figure 3 , an integrated circuit device 100 including a field effect transistor TR is described. The field effect transistor TR has a gate-all-around structure including an active region having a shape of a nanowire or a nanosheet and a gate surrounding the active region. As used herein, the term "surround" (or its variations, or similar terms) is intended to broadly refer to an element, structure, or layer that extends, encloses, surrounds, or closes another element, structure, or layer on all sides, but there may be interruptions or gaps. Thus, for example, a material layer having voids or gaps may still "surround" another layer it surrounds.

[0023] With reference to Figure 1 , Figure 2A and Figure 2B , the integrated circuit device 100 may include a plurality of fin-shaped active regions FA and a plurality of nanosheet stacks NSS disposed above the plurality of fin-shaped active regions FA. The plurality of fin-shaped active regions FA project (i.e., extend) upward from the substrate 110 in a vertical direction (Z direction) perpendicular to the upper surface of the substrate 110 and extend longitudinally in a first horizontal direction (X direction) parallel to the upper surface of the substrate 110. As used herein, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. "Nanosheet" should be understood to include nanowires.

[0024] The substrate 110 may include a semiconductor (such as silicon (Si) or germanium (Ge)) or a compound semiconductor (such as SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), or indium phosphide (InP)). As used herein, the terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" refer to materials including the elements contained in each term, rather than chemical formulas representing stoichiometric relationships. The substrate 110 may include a first region 110_1 and a second region 110_2, which are separated from each other in a second horizontal direction (Y direction) parallel to the upper surface of the substrate 110 and intersecting the first horizontal direction (X direction).

[0025] In some embodiments, the first fin-type active region FA1 may be disposed on a first region 110_1 of the substrate 110. The second fin-type active region FA2 may be disposed on a second region 110_2 of the substrate 110. The first fin-type active region FA1 and the second fin-type active region FA2 may each extend in a first horizontal direction (X direction) and may be spaced apart from each other in a second horizontal direction (Y direction).

[0026] In some embodiments, the device isolation film 114 may be disposed on the substrate 110 to cover two sidewalls of each of the plurality of fin-type active regions FA. As used herein, the term "cover" (or its variations, or similar terms) is intended to broadly refer to such an element, structure, or layer: directly or in the case of one or more other intermediate elements, structures, or layers therebetween, and without requiring the element, structure, or layer to completely cover the other element, structure, or layer, on or above the other element, structure, or layer. The device isolation film 114 may include an oxide film, a nitride film, or a combination thereof, but the embodiments are not limited thereto.

[0027] In some embodiments, a plurality of gate lines 160 may be disposed above the plurality of fin-type active regions FA. The plurality of gate lines 160 may each extend longitudinally in a second horizontal direction (Y direction).

[0028] Specifically, the plurality of gate lines 160 may each include a first gate line 161 and a second gate line 162 spaced apart from each other in a second horizontal direction (Y direction). The first gate line 161 may be disposed above the first fin-type active region FA1 above the first region 110_1 of the substrate 110. The second gate line 162 may be disposed above the second fin-type active region FA2 above the second region 110_2 of the substrate 110.

[0029] In some embodiments, in a region where the plurality of fin-type active regions FA and the plurality of gate lines 160 cross each other, a plurality of nanosheet stacks NSS may be disposed on the fin top surface FT of each of the plurality of fin-type active regions FA.

[0030] Specifically, the plurality of nanosheet stacks NSS may include a first nanosheet stack NSS1 and a second nanosheet stack NSS2 spaced apart from each other in a second horizontal direction (Y direction). The first nanosheet stack NSS1 may be disposed in a region where the first fin-type active region FA1 and the first gate line 161 cross each other above the first region 110_1 of the substrate 110. The second nanosheet stack NSS2 may be disposed in a region where the second fin-type active region FA2 and the second gate line 162 cross each other above the second region 110_2 of the substrate 110.

[0031] In some embodiments, the vertical structure 180 may be disposed between the first gate line 161 and the second gate line 162. The vertical structure 180 may be disposed between the first gate line 161 and the second gate line 162 in the second horizontal direction (Y direction). The vertical structure 180 may extend between the first gate line 161 and the second gate line 162 in the first horizontal direction (X direction). In some other embodiments not explicitly shown, the vertical structure 180 may not extend between the first gate line 161 and the second gate line 162 in the first horizontal direction (X direction), but may be only disposed between the first gate line 161 and the second gate line 162.

[0032] In some embodiments, with respect to the upper surface of the substrate 110 as a reference layer, the vertical structure 180 may have a top surface disposed at the same vertical height as the top surfaces of the first gate line 161 and the second gate line 162. The vertical structure 180 may include a portion disposed between the first fin-type active region FA1 and the second fin-type active region FA2 in the second horizontal direction (Y direction).

[0033] In some embodiments, the device isolation film 114 may be disposed under the vertical structure 180 to completely fill the space between the first fin-type active region FA1 and the second fin-type active region FA2. As used herein, the term "fill" (or its variations, or similar terms) is intended to broadly refer to completely filling the defined space (e.g., the space between the first fin-type active region FA1 and the second fin-type active region FA2) or partially filling the defined space; that is, the defined space does not have to be completely filled, but may be, for example, partially filled or have voids or other spaces therethrough. In some other embodiments not explicitly shown, the device isolation film 114 may not be disposed under the vertical structure 180, and the vertical structure 180 may further extend in the vertically downward direction (-Z direction). In some other embodiments not explicitly shown, the device isolation film 114 may not be disposed under the vertical structure 180, and the first fin-type active region FA1 and the second fin-type active region FA2 may be connected to each other and disposed under the vertical structure 180.

[0034] In some embodiments, the vertical structure 180 may be in contact with each of the plurality of nanosheet stacks NSS. As used herein, the term "contact" (or its variations, or similar terms such as "connect" or its variations) is intended to refer to physical and / or electrical contact between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. Specifically, the vertical structure 180 may be in contact with the first nanosheet stack NSS1 and the second nanosheet stack NSS2, and may be disposed between the first nanosheet stack NSS1 and the second nanosheet stack NSS2. For example, the first nanosheet stack NSS1 and the second nanosheet stack NSS2 may be spaced apart from each other, and the vertical structure 180 is between the first nanosheet stack NSS1 and the second nanosheet stack NSS2.

[0035] In some embodiments, the vertical structure 180 may include an air space 185 therein. For example, the vertical structure 180 may include one or more air spaces 185 therein. The air space 185 will be described in detail below with reference to Figure 3 Detailed description of the air space 185.

[0036] In some embodiments, each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT of the fin-type active region FA at a position separated from the fin top surface FT in the vertical direction (Z direction). Specifically, the first nanosheet stack NSS1 may include at least one nanosheet facing the first fin top surface FT1 of the first fin-type active region FA1 at a position separated from the first fin top surface FT1 in the vertical direction (Z direction). Specifically, the second nanosheet stack NSS2 may include at least one nanosheet facing the second fin top surface FT2 of the second fin-type active region FA2 at a position separated from the second fin top surface FT2 in the vertical direction (Z direction).

[0037] As Figure 2A and Figure 2B As shown in, the first nanosheet stack NSS1 may include a first nanosheet N11, a second nanosheet N12, and a third nanosheet N13 stacked on top of each other in the vertical direction (Z direction) above the first fin-type active region FA1. As used herein, the term "stacked" (or its variations, or similar terms) is intended to broadly refer to at least a portion of a first element crossing a second element in the vertical direction (i.e., the Z direction), but does not require the first element and the second element to be completely aligned with each other in a horizontal plane (i.e., in the first horizontal direction and / or the second horizontal direction). The first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may have different vertical distances (Z-direction distances) from the first fin top surface FT1 of the first fin-type active region FA1.

[0038] Similarly, the second nanosheet stack NSS2 may include a first nanosheet N21, a second nanosheet N22, and a third nanosheet N23 that are stacked on top of each other in the vertical direction (Z direction) above the second fin-type active region FA2. The first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 may have different vertical distances (Z-direction distances) from the second fin top surface FT2 of the second fin-type active region FA2.

[0039] Although Figure 2A and Figure 2B illustrate the case where each of the plurality of nanosheet stacks NSS includes three nanosheets, the inventive concept is not limited thereto, and each of the plurality of nanosheet stacks NSS may include four or more nanosheets or less than three nanosheets.

[0040] Although Figure 1 illustrate the case where the nanosheet stack NSS has an approximately quadrilateral planar shape, the embodiments are not limited thereto. Depending on the planar shape of each of the fin-type active region FA and the gate line 160, the nanosheet stack NSS may have various planar shapes. Here, a configuration is described in which a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are arranged above one fin-type active region FA, and the plurality of nanosheet stacks NSS are arranged in rows in the first horizontal direction (X direction) above one fin-type active region FA. However, the number of nanosheet stacks NSS and gate lines 160 arranged on one fin-type active region FA is not particularly limited.

[0041] In some embodiments, the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 may each include a channel region. Here, the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may each be referred to as a channel region. In some embodiments, the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may each have a cross-sectional thickness in the range of about 4 nm to about 6 nm, but the embodiments are not limited thereto. Here, the thickness of each of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 refers to its size in the vertical direction (Z direction). In some embodiments, the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may have substantially the same thickness in the vertical direction (Z direction). In some other embodiments, at least a portion of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may have different thicknesses in the vertical direction (Z direction).

[0042] In some embodiments, this may also be applied to the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2. For example, the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 may each be referred to as a channel region.

[0043] In some embodiments, at least a portion of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 may have different sizes in a first horizontal direction (X direction). In some other embodiments, at least some of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 may have the same size in the first horizontal direction (X direction). In some embodiments, this may also be applied to the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2.

[0044] In some embodiments, multiple nanosheets may each be in contact with the vertical structure 180. Specifically, the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 may be in contact with the vertical structure 180. Specifically, the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2 may be in contact with the vertical structure 180.

[0045] As described above, since the vertical structure 180 is arranged to be in contact with multiple nanosheets, the multiple gate lines 160 may not extend further than the multiple nanosheets in a second horizontal direction (Y direction). Specifically, since the vertical structure 180 is arranged to be in contact with the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1, the first gate line 161 may not extend further than the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 in the second horizontal direction (Y direction) toward the second fin active region FA2. Specifically, since the vertical structure 180 is arranged to be in contact with the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2, the second gate line 162 may not extend further than the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2 in the second horizontal direction (Y direction) toward the first fin active region FA1.

[0046] As Figure 2A and Figure 2BAs shown, multiple gate lines 160 may each include a main gate portion and multiple sub-gate portions. Specifically, the first gate line 161 may include a first main gate portion 161M and multiple first sub-gate portions 161S. The first main gate portion 161M may cover the top surface of the first nanosheet stack NSS1 and may extend in the second horizontal direction (Y direction). The multiple first sub-gate portions 161S may be integrally connected to the first main gate portion 161M, and one may be disposed between the first nanosheet N11 and the second nanosheet N12, between the second nanosheet N12 and the third nanosheet N13, and between the first nanosheet N11 and the first fin-type active region FA1, respectively. In the vertical direction (Z direction), the thickness of each of the multiple first sub-gate portions 161S may be less than the thickness of the first main gate portion 161M.

[0047] Similarly, the second gate line 162 may include a second main gate portion 162M and multiple second sub-gate portions 162S. The second main gate portion 162M may cover the top surface of the second nanosheet stack NSS2 and may extend in the second horizontal direction (Y direction). The multiple second sub-gate portions 162S may be integrally connected to the second main gate portion 162M, and one may be disposed between the first nanosheet N21 and the second nanosheet N22, between the second nanosheet N22 and the third nanosheet N23, and between the first nanosheet N21 and the second fin-type active region FA2, respectively. In the vertical direction (Z direction), the thickness of each of the multiple second sub-gate portions 162S may be less than the thickness of the second main gate portion 162M.

[0048] The multiple gate lines 160 may each include a metal, a metal nitride, a metal carbide, or a combination thereof, but the embodiments are not limited thereto. The metal may be selected from, for example, titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide may be titanium aluminum carbide (TiAlC). However, the materials constituting the multiple gate lines 160 are not limited to the above examples.

[0049] The first gate dielectric film 151 and the second gate dielectric film 152 may be disposed between the nanosheet stack NSS and the gate line 160, and between the gate line 160 and the vertical structure 180. Specifically, the first gate dielectric film 151 may be disposed between the first nanosheet stack NSS1 and the first gate line 161, and between the first gate line 161 and the vertical structure 180. For example, the first gate dielectric film 151 may be disposed between each of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 and the first gate line 161, between the first main gate portion 161M and the vertical structure 180, and between the plurality of first sub-gate portions 161S and the vertical structure 180. Specifically, the second gate dielectric film 152 may be disposed between the second nanosheet stack NSS2 and the second gate line 162, and between the second gate line 162 and the vertical structure 180. For example, the second gate dielectric film 152 may be disposed between each of the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2 and the second gate line 162, between the second main gate portion 162M and the vertical structure 180, and between the plurality of second sub-gate portions 162S and the vertical structure 180.

[0050] In some embodiments, above the fin-type active region FA, a pair of source / drain regions 130 may be respectively disposed on both sides of a gate line 160, and the gate line 160 is between the pair of source / drain regions 130. Specifically, above the first fin-type active region FA1, a pair of first source / drain regions 131 may be respectively disposed on both sides of the first gate line 161, and the first gate line 161 is between the pair of first source / drain regions 131. One of the first source / drain regions 131 may be disposed on the first fin-type active region FA1 between a pair of adjacent first nanosheet stacks NSS1. The first source / drain region 131 may be in contact with the sidewall of the first nanosheet stack NSS1 surrounded by the adjacent first gate line 161. Similarly, above the second fin-type active region FA2, a pair of second source / drain regions 132 may be respectively disposed on both sides of the second gate line 162, and the second gate line 162 is between the pair of second source / drain regions 132. One of the second source / drain regions 132 may be disposed on the second fin-type active region FA2 between a pair of adjacent second nanosheet stacks NSS2. The second source / drain region 132 may be in contact with the sidewall of the second nanosheet stack NSS2 surrounded by the adjacent second gate line 162.

[0051] In some embodiments, two sidewalls (i.e., opposite sidewalls) of each of the plurality of gate lines 160 may be covered with an outer insulating spacer 118. Specifically, two sidewalls (opposite sidewalls) of the first gate line 161 may be covered with the outer insulating spacer 118. The outer insulating spacer 118 may cover two sidewalls of the first main gate portion 161M on the top surface of the first nanosheet stack NSS1. The outer insulating spacer 118 may be separated from the first gate line 161, and a first gate dielectric film 151 is between the outer insulating spacer 118 and the first gate line 161. The outer insulating spacer 118 may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. As used herein, the terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" refer to materials including the elements included in each term, rather than chemical formulas representing stoichiometric relationships. Although not shown, this may also apply to the second gate line 162.

[0052] In some embodiments, each of the plurality of source / drain regions 130 may include a portion that overlaps with the outer insulating spacer 118 in the vertical direction (Z direction). For example, the first source / drain region 131 may include a portion that overlaps with the outer insulating spacer 118 in the vertical direction (Z direction). In some embodiments, each of the plurality of source / drain regions 130 may not include a portion that overlaps with the main gate portion in the vertical direction (Z direction). For example, the first source / drain region 131 may not include a portion that overlaps with the first main gate portion 161M in the vertical direction (Z direction). Although not shown, this may also apply to the second source / drain region 132.

[0053] In some embodiments, two sidewalls of each of the plurality of sub-gate portions may be separated from the source / drain region 130, and a gate dielectric film is between two sidewalls of each of the plurality of sub-gate portions and the source / drain region 130. For example, two sidewalls of each of the plurality of first sub-gate portions 161S may be separated from the first source / drain region 131, and a first gate dielectric film 151 is between two sidewalls of each of the plurality of first sub-gate portions 161S and the first source / drain region 131. The gate dielectric film may include a portion in contact with the first semiconductor layer of the source / drain region 130. For example, the first gate dielectric film 151 may include a portion in contact with the first semiconductor layer 133 of the first source / drain region 131. Although not shown, this may also apply to the second source / drain region 132.

[0054] In some embodiments, a plurality of source / drain regions 130 may be disposed on the fin-type active region FA. With respect to the upper surface of the substrate 110 as a reference layer, the vertical height of the bottom surface of each of the plurality of source / drain regions 130 may be lower than the vertical height of the fin top surface FT of the fin-type active region FA. Specifically, the plurality of first source / drain regions 131 may each be disposed adjacent to at least one first gate line 161 selected from among the plurality of first gate lines 161. The plurality of first source / drain regions 131 may each have sidewalls facing the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 adjacent thereto. The plurality of first source / drain regions 131 may each be in contact with the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 adjacent thereto. The plurality of first source / drain regions 131 may have bottom surfaces in contact with the plurality of first fin-type active regions FA1. Although not shown, this may also be applied to the second source / drain region 132.

[0055] In some embodiments, the plurality of source / drain regions 130 may include a plurality of semiconductor layers. Specifically, the plurality of semiconductor layers included in the first source / drain region 131 may include a first semiconductor layer 133, a second semiconductor layer 135 formed on the first semiconductor layer 133, and a third semiconductor layer 137 formed on the second semiconductor layer 135. In some embodiments, the plurality of semiconductor layers may further include a capping layer 139 formed on the third semiconductor layer 137. Although not shown, this may also be applied to the second source / drain region 132.

[0056] In some embodiments, in each of the plurality of first source / drain regions 131, the first semiconductor layer 133 may include a portion in contact with the channel region and a portion in contact with the first fin-type active region FA1. That is, the first semiconductor layer 133 may include a portion in contact with the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13, a portion in contact with the plurality of first sub-gate portions 161S, and a portion in contact with the first fin-type active region FA1. Although not shown, this may also be applied to the second source / drain region 132.

[0057] In some embodiments, the top surfaces of each of the first gate dielectric film 151, the second gate dielectric film 152, the gate line 160, and the outer insulating spacer 118 may be covered with a capping insulating pattern 165. The capping insulating pattern 165 may include a silicon nitride film.

[0058] In some embodiments, the plurality of outer insulating spacers 118 and the plurality of source / drain regions 130 may be covered with an insulating liner 142. The insulating liner 142 may include silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. In some embodiments, the insulating liner 142 may be omitted. An inter-gate insulating film 144 may be disposed on the insulating liner 142. The inter-gate insulating film 144 may include a silicon nitride film, a silicon oxide film, SiON, SiOCN, or a combination thereof. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may be in contact with the plurality of source / drain regions 130.

[0059] As Figure 1 shown, a plurality of field effect transistors TR may be formed in portions where a plurality of fin active regions FA on a substrate 110 and a plurality of gate lines 160 cross each other. The plurality of field effect transistors TR may constitute a logic circuit or a memory device.

[0060] Referring together to Figure 2B and Figure 3 , the vertical structure 180 may include a first sidewall 180_S1 facing the first gate line 161 and a second sidewall 180_S2 facing the second gate line 162. The first sidewall 180_S1 and the second sidewall 180_S2 face each other laterally (i.e., in a second horizontal direction).

[0061] In some embodiments, the first sidewall 180_S1 may include a first recess R1 recessed into the vertical structure 180. The second sidewall 180_S2 may include a second recess R2 recessed into the vertical structure 180. The first recess R1 and the second recess R2 may be (e.g., at least partially) superimposed on the vertical structure 180 in the vertical direction (Z direction).

[0062] In some embodiments, a portion of the first gate dielectric film 151 and a portion of the first gate line 161 may be disposed in the first recess R1. Specifically, the first gate dielectric film 151 may include a sub-portion 151_S disposed in the first recess R1. Specifically, the first gate line 161 may include a first protrusion 161_P disposed in the first recess R1. The first gate line 161 may include a first protrusion 161_P protruding (i.e., horizontally extending) into the first recess R1. For example, the first main gate portion 161M of the first gate line 161 may include a first protrusion 161_P protruding into the first recess R1. For example, each of the plurality of first sub-gate portions 161S of the first gate line 161 may include a first protrusion 161_P protruding into the first recess R1. For example, a portion of the plurality of first sub-gate portions 161S of the first gate line 161 may include a first protrusion 161_P protruding into the first recess R1.

[0063] In some embodiments, a sub - portion 151_S of the first gate dielectric film 151 may be (at least partially) stacked with the vertical structure 180 in the vertical direction (Z - direction). In some embodiments, a first protrusion 161_P of the first gate line 161 may be (at least partially) stacked with the vertical structure 180 in the vertical direction (Z - direction).

[0064] Similarly, a part of the second gate dielectric film 152 and a part of the second gate line 162 may be disposed in the second recess R2. Specifically, the second gate dielectric film 152 may include a sub - portion 152_S disposed in the second recess R2. Specifically, the second gate line 162 may include a second protrusion 162_P disposed in the second recess R2. The second gate line 162 may include a second protrusion 162_P that protrudes (i.e., extends horizontally) into the second recess R2. For example, each of the second main gate portion 162M and the plurality of second sub - gate portions 162S of the second gate line 162 may include a second protrusion 162_P that protrudes into the second recess R2.

[0065] In some embodiments, a sub - portion 152_S of the second gate dielectric film 152 may be (at least partially) stacked with the vertical structure 180 in the vertical direction (Z - direction). In some embodiments, a second protrusion 162_P of the second gate line 162 may be (at least partially) stacked with the vertical structure 180 in the vertical direction (Z - direction).

[0066] As Figure 2B and Figure 3 As shown in [reference], the first recess R1 and the second recess R2 may each have two sidewalls that are not parallel to each other and a bottom surface that is substantially parallel to the sidewall of the vertical structure 180. Accordingly, the first protrusion 161_P and the second protrusion 162_P disposed in the first recess R1 and the second recess R2, respectively, may each have a quadrilateral shape. For example, the first protrusion 161_P and the second protrusion 162_P may each have a trapezoidal shape.

[0067] As Figure 3 As shown in [reference], the first recess R1 may have a first width W1 in the vertical direction (Z - direction). Specifically, the opening of the first recess R1 may have a first width W1 in the vertical direction (Z - direction). For example, the first width W1 of the first recess R1 may be the width of the portion of the first recess R1 that has the maximum width in the vertical direction (Z - direction).

[0068] In some embodiments, the first width W1 of the first recess R1 may be equal to or less than the distance between two adjacent nanosheets among the plurality of nanosheets of the first nanosheet stack NSS1. For example, the first width W1 of the first recess R1 may be equal to or less than the first distance D1 between two adjacent nanosheets (e.g., the first nanosheet N11 and the second nanosheet N12). In other words, the first recess R1 may be disposed between two adjacent nanosheets. For example, the first recess R1 may not overlap with two adjacent nanosheets in the second horizontal direction (Y direction). Here, the two nanosheets adjacent to the first recess R1 may refer to the two nanosheets adjacent to the first recess R1 in the vertical direction (Z direction).

[0069] In some embodiments, the sub - portion 151_S of the first gate dielectric film 151 disposed in the first recess R1 and the first protrusion 161_P of the first gate line 161 may be disposed between two adjacent nanosheets. For example, the sub - portion 151_S of the first gate dielectric film 151 and the first protrusion 161_P of the first gate line 161 may not overlap with two adjacent nanosheets in the second horizontal direction (Y direction).

[0070] Similarly, the width of the second recess R2 in the vertical direction (i.e., the width of the opening of the second recess R2 in the vertical direction (Z direction)) may be equal to or less than the distance between two adjacent nanosheets among the plurality of nanosheets of the second nanosheet stack NSS2. For example, the second recess R2 may not overlap with two adjacent nanosheets in the second horizontal direction (Y direction).

[0071] In some embodiments, the sub - portion 152_S of the second gate dielectric film 152 disposed in the second recess R2 and the second protrusion 162_P of the second gate line 162 may be disposed between two adjacent nanosheets. For example, the sub - portion 152_S of the second gate dielectric film 152 disposed in the second recess R2 and the second protrusion 162_P of the second gate line 162 may not overlap with two adjacent nanosheets in the second horizontal direction (Y direction).

[0072] As Figure 2B and Figure 3 shown, the vertical structure 180 may further include an air space 185 therein. For example, the vertical structure 180 may further include one or more air spaces 185.

[0073] In some embodiments, the air space 185 may be stacked with a plurality of nanosheets in a second horizontal direction (Y direction). Specifically, the air space 185 may be at least partially stacked with a plurality of nanosheets of the first nanosheet stack NSS1 in the second horizontal direction (Y direction). For example, a plurality of air spaces 185 may be respectively stacked with the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 of the first nanosheet stack NSS1 in the second horizontal direction (Y direction). The air space 185 may be stacked with a plurality of nanosheets of the second nanosheet stack NSS2 in the second horizontal direction (Y direction). For example, a plurality of air spaces 185 may be respectively stacked with the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 of the second nanosheet stack NSS2 in the second horizontal direction (Y direction).

[0074] In some embodiments, the air space 185 may be stacked with a top portion of the first fin-type active region FA1 in the second horizontal direction (Y direction). For example, a part of a plurality of air spaces 185 may be stacked with a top portion of the first fin-type active region FA1 in the second horizontal direction (Y direction). In some embodiments, the air space 185 may be stacked with a top portion of the second fin-type active region FA2 in the second horizontal direction (Y direction). For example, a part of a plurality of air spaces 185 may be stacked with a top portion of the second fin-type active region FA2 in the second horizontal direction (Y direction).

[0075] In some embodiments, the air space 185 may include a portion that does not overlap with the first recess R1 in the second horizontal direction (Y direction). For example, each of a plurality of air spaces 185 may include a portion that does not overlap with the adjacent first recess R1 in the second horizontal direction (Y direction). In some embodiments, the air space 185 may include a portion that does not overlap with the second recess R2 in the second horizontal direction (Y direction). For example, each of a plurality of air spaces 185 may include a portion that does not overlap with the adjacent second recess R2 in the second horizontal direction (Y direction). Here, the first recess R1 and the second recess R2 adjacent to the air space 185 may refer to the first recess R1 and the second recess R2 adjacent to the air space 185 in the vertical direction (Z direction).

[0076] In some embodiments, the air space 185 disposed in the vertical structure 180 may be formed by the first recess R1 and the second recess R2 on two sidewalls of the vertical structure 180. This aspect will be described in detail below with reference to Figures 12A to 12F Detailed description of this aspect will be provided.

[0077] According to an inventive concept, an integrated circuit device 100 including a vertical structure 180 may be provided. The vertical structure 180 includes a first recess R1 and a second recess R2 on its sidewall. Since portions of a first gate dielectric film 151, a second gate dielectric film 152, a first gate line 161, and a second gate line 162 are respectively disposed in the first recess R1 and the second recess R2 of the integrated circuit device 100, an effective channel width may be increased. That is, according to the inventive concept, an integrated circuit device 100 having improved performance and reliability may be provided.

[0078] According to an inventive concept, an integrated circuit device 100 including a vertical structure 180 may be provided. The vertical structure 180 includes one or more air spaces 185 therein. Since the vertical structure 180 includes one or more air spaces 185 therein, a parasitic capacitance may be reduced. That is, according to the inventive concept, an integrated circuit device 100 having improved performance and reliability may be provided.

[0079] Figures 4 to 6 are enlarged schematic cross-sectional views of integrated circuit devices 101, 102, and 103 according to embodiments, respectively. Specifically, Figures 4 to 6 is related to Figure 2B a portion corresponding to a region EX1 of the integrated circuit device 100 shown in, which is an enlarged schematic cross-sectional view. Hereinafter, differences from the integrated circuit device 100 described with reference to Figure 1 , Figure 2A , Figure 2B and Figure 3 will be mainly described.

[0080] Referring to Figure 4 , the integrated circuit device 101 may include a vertical structure 180 in contact with a plurality of nanosheets. The vertical structure 180 may include one or more air spaces 185 therein. The vertical structure 180 may include a third recess R3 on its sidewall facing the plurality of nanosheets.

[0081] In some embodiments, the third recess R3 of the integrated circuit device 101 may include an opening and two sidewalls that are not parallel to each other. For example, the third recess R3 may have a triangular shape. Accordingly, a first protrusion 161_P of the first gate line 161 in the third recess R3 may have a triangular shape.

[0082] Referring to Figure 5 , the integrated circuit device 102 may include a vertical structure 180 in contact with a plurality of nanosheets. The vertical structure 180 may include one or more air spaces 185 therein. The vertical structure 180 may include a fourth recess R4 on its sidewall facing the plurality of nanosheets.

[0083] In some embodiments, the fourth recess R4 of the integrated circuit device 102 may have a second width W2 in the vertical direction (Z direction). Specifically, the opening of the fourth recess R4 may have a second width W2 in the vertical direction (Z direction). For example, the second width W2 of the fourth recess R4 may be the width of the portion of the fourth recess R4 that has the maximum width in the vertical direction (Z direction).

[0084] In some embodiments, the second width W2 of the fourth recess R4 may be greater than the distance between two adjacent nanosheets among the plurality of nanosheets of the first nanosheet stack NSS1. For example, the second width W2 of the fourth recess R4 may be greater than the first distance D1 between two adjacent nanosheets (e.g., the first nanosheet N11 and the second nanosheet N12). In other words, the fourth recess R4 may include a portion that is not between two adjacent nanosheets. For example, the fourth recess R4 may include a portion that overlaps two adjacent nanosheets in the second horizontal direction (Y direction).

[0085] In some embodiments, the sub - portion 151_S of the first gate dielectric film 151 in the fourth recess R4 and / or the first protrusion 161_P of the first gate line 161 in the fourth recess R4 may each include a portion that is not between two adjacent nanosheets. For example, the sub - portion 151_S of the first gate dielectric film 151 and the first protrusion 161_P of the first gate line 161 may each include a portion that overlaps two adjacent nanosheets in the second horizontal direction (Y direction).

[0086] Here, the shape of the first protrusion 161_P of the first gate line 161 of the integrated circuit device 102 is not limited to Figure 5 the shape shown in

[0087] Referring to Figure 6 , the integrated circuit device 103 may include a vertical structure 180 that contacts the plurality of nanosheets. The vertical structure 180 may include one or more air spaces 185 therein. The vertical structure 180 may include a fifth recess R5 on the sidewall facing the plurality of nanosheets.

[0088] In some embodiments, the fifth recess R5 of the integrated circuit device 103 may include an opening and two sidewalls that are not parallel to each other. For example, the fifth recess R5 may have a triangular shape. Accordingly, the first protrusion 161_P of the first gate line 161 in the fifth recess R5 may have a triangular shape.

[0089] In some embodiments, the width of the fifth recess R5 of the integrated circuit device 103 at the widest point in the vertical direction (Z direction) may be greater than the distance between two adjacent nanosheets among the plurality of nanosheets of the first nanosheet stack NSS1. For example, the width of the fifth recess R5 may be greater than the distance between two adjacent nanosheets (e.g., the first nanosheet N11 and the second nanosheet N12). In other words, the fifth recess R5 may include a portion that is not between two adjacent nanosheets. For example, the fifth recess R5 may include a portion that overlaps with two adjacent nanosheets (e.g., at least a portion of the two adjacent nanosheets) in the second horizontal direction (Y direction).

[0090] In some embodiments, the sub - portion 151_S of the first gate dielectric film 151 in the fifth recess R5 may include a portion that is not between two adjacent nanosheets, while the first protrusion 161_P of the first gate line 161 in the fifth recess R5 may not include a portion that is not between two adjacent nanosheets. For example, the sub - portion 151_S of the first gate dielectric film 151 may include a portion that overlaps with two adjacent nanosheets in the second horizontal direction (Y direction), while the first protrusion 161_P of the first gate line 161 may not include a portion that overlaps with two adjacent nanosheets in the second horizontal direction (Y direction).

[0091] Figure 7 is a schematic cross - sectional view of an integrated circuit device 100A according to an embodiment. Hereinafter, the differences from the integrated circuit device 100 described with reference to Figure 1 、 Figure 2A 、 Figure 2B and Figure 3 will be mainly described.

[0092] Referring to Figure 7 , the integrated circuit device 100A may include a substrate 110 including a first region 110_1 and a second region 110_2, a first fin - type active region FA1 extending in the first horizontal direction (X direction) on the first region 110_1, and a second fin - type active region FA2 extending in the first horizontal direction (X direction) on the second region 110_2.

[0093] In some embodiments, a first gate line 161 extending in the second horizontal direction (Y direction) may be disposed above the first fin - type active region FA1, and a second gate line 162 extending in the second horizontal direction (Y direction) may be disposed above the second fin - type active region FA2. A vertical structure 180 may be disposed between the first gate line 161 and the second gate line 162. One or more air spaces 185 may be disposed in the vertical structure 180.

[0094] In some embodiments, the vertical structure 180 may include a first sidewall 180_S1 facing the first gate line 161 and a second sidewall 180_S2 facing the second gate line 162. The vertical structure 180 may include a sixth recess R6 on the first sidewall 180_S1 and a seventh recess R7 on the second sidewall 180_S2.

[0095] In some embodiments, the width of the sixth recess R6 in the vertical direction (Z direction) may be different from the width of the seventh recess R7 in the vertical direction (Z direction).

[0096] Specifically, the sixth recess R6 may have a third width W3 in the vertical direction (Z direction). The opening of the sixth recess R6 may have a third width W3 in the vertical direction (Z direction). For example, the third width W3 of the sixth recess R6 may be the width of the portion of the sixth recess R6 having the maximum width in the vertical direction (Z direction).

[0097] In some embodiments, the third width W3 of the sixth recess R6 may be equal to or less than the distance between two adjacent nanosheets among the plurality of nanosheets of the first nanosheet stack NSS1. For example, the sixth recess R6 may not overlap two adjacent nanosheets in the second horizontal direction (Y direction).

[0098] Specifically, the seventh recess R7 may have a fourth width W4 in the vertical direction (Z direction). The opening of the seventh recess R7 may have a fourth width W4 in the vertical direction (Z direction). For example, the fourth width W4 of the seventh recess R7 may be the width of the portion of the seventh recess R7 having the maximum width in the vertical direction (Z direction).

[0099] In some embodiments, the fourth width W4 of the seventh recess R7 may be greater than the distance between two adjacent nanosheets among the plurality of nanosheets of the second nanosheet stack NSS2. For example, the seventh recess R7 may include a portion that overlaps two adjacent nanosheets in the second horizontal direction (Y direction).

[0100] In some embodiments, the third width W3 of the sixth recess R6 of the integrated circuit device 100A may be less than the fourth width W4 of the seventh recess R7 of the integrated circuit device 100A.

[0101] Figure 8 is a schematic cross-sectional view of an integrated circuit device 200 according to an embodiment. Figure 9 is Figure 8 an enlarged schematic cross-sectional view of the region EX2 of the integrated circuit device 200 shown in. Hereinafter, mainly described with reference to Figure 1 、 Figure 2A 、 Figure 2B andFigure 3 Differences of the described integrated circuit device 100.

[0102] Referring to Figure 8 and Figure 9 , the integrated circuit device 200 may include a substrate 210 including a first region 210_1 and a second region 210_2, a first fin-type active region FA1 extending in a first horizontal direction (X direction) over the first region 210_1, and a second fin-type active region FA2 extending in the first horizontal direction (X direction) over the second region 210_2.

[0103] In some embodiments, the first region 210_1 and the second region 210_2 of the integrated circuit device 200 may be doped with impurities of different conductive types. For example, the first region 210_1 of the integrated circuit device 200 may be an n-type field effect transistor (nFET) region, and the second region 210_2 of the integrated circuit device 200 may be a p-type field effect transistor (pFET) region. That is, the transistor formed in the portion of the integrated circuit device 200 where the first fin-type active region FA1 and the first gate line 261 cross each other above the first region 210_1 may be an nFET, and the transistor formed in the portion of the integrated circuit device 200 where the second fin-type active region FA2 and the second gate line 262 cross each other above the second region 210_2 may be a pFET.

[0104] In some embodiments, a first gate line 261 extending in a second horizontal direction (Y direction) may be disposed above the first fin-type active region FA1, and a second gate line 262 extending in the second horizontal direction (Y direction) may be disposed above the second fin-type active region FA2.

[0105] In some embodiments, the first gate line 261 may include a first main gate portion 261M and a plurality of first sub-gate portions 261S. Similarly, the second gate line 262 may include a second main gate portion 262M and a plurality of second sub-gate portions 262S. A covering insulating pattern 265 may cover the top surfaces of each of the vertical structures 280 and the gate lines 260.

[0106] In some embodiments, the first gate line 261 may include a first main metal layer 261_1 and a first work function metal layer 261_2N. The first main metal layer 261_1 may be disposed on the first work function metal layer 261_2N. The first work function metal layer 261_2N may be disposed between the first main metal layer 261_1 and the first nanosheet stack NSS1 and between the first main metal layer 261_1 and the vertical structure 280. For example, the first work function metal layer 261_2N may be disposed between each of the first nanosheet N11, the second nanosheet N12, and the third nanosheet N13 included in the first nanosheet stack NSS1 and the first main metal layer 261_1 and between the first main metal layer 261_1 and the vertical structure 280.

[0107] In some embodiments, the first main gate portion 261M of the first gate line 261 may include a portion in contact with the first gate dielectric film 251. In other words, the first work function metal layer 261_2N may not be disposed between a portion of the first main gate portion 261M of the first gate line 261 and the vertical structure 280.

[0108] In some embodiments, the second gate line 262 may include a second main metal layer 262_1 and a second work function metal layer 262_2P. The second main metal layer 262_1 may be disposed on the second work function metal layer 262_2P. The second work function metal layer 262_2P may be disposed between the second main metal layer 262_1 and the second nanosheet stack NSS2 and between the second main metal layer 262_1 and the vertical structure 280. For example, the second work function metal layer 262_2P may be disposed between each of the first nanosheet N21, the second nanosheet N22, and the third nanosheet N23 included in the second nanosheet stack NSS2 and the second main metal layer 262_1 and between the second main metal layer 262_1 and the vertical structure 280.

[0109] In some embodiments, the first work function metal layer 261_2N of the first gate line 261 and the second work function metal layer 262_2P of the second gate line 262 may include different metal layers. For example, the first work function metal layer 261_2N may include a metal for forming an nFET. For example, the second work function metal layer 262_2P may include a metal for forming a pFET.

[0110] In some embodiments, the second main gate portion 262M of the second gate line 262 may include a portion in contact with the second gate dielectric film 252. In other words, the second work function metal layer 262_2P may not be disposed between a portion of the second main gate portion 262M of the second gate line 262 and the vertical structure 280.

[0111] In some embodiments, the first gate dielectric film 251 and the second gate dielectric film 252 may be disposed between the nanosheet stack NSS and the gate line 260, and between the gate line 260 and the vertical structure 280. Specifically, the first gate dielectric film 251 may be disposed between the first nanosheet stack NSS1 and the first gate line 261, and between the first gate line 261 and the vertical structure 280. For example, the first gate dielectric film 251 may be disposed between the first nanosheet stack NSS1 and the first work function metal layer 261_2N, and between the first work function metal layer 261_2N and the vertical structure 280. Specifically, the second gate dielectric film 252 may be disposed between the second nanosheet stack NSS2 and the second gate line 262, and between the second gate line 262 and the vertical structure 280. For example, the second gate dielectric film 252 may be disposed between the second nanosheet stack NSS2 and the second work function metal layer 262_2P, and between the second work function metal layer 262_2P and the vertical structure 280.

[0112] In some embodiments, the vertical structure 280 may be disposed between the first gate line 261 and the second gate line 262. The vertical structure 280 may include a dielectric material. One or more air spaces 285 may be disposed in the vertical structure 280.

[0113] In some embodiments, the vertical structure 280 may include a first sidewall 280_S1 facing the first gate line 261 and a second sidewall 280_S2 facing the second gate line 262. The vertical structure 280 may include a first recess R1 on the first sidewall 280_S1 and a second recess R2 on the second sidewall 280_S2.

[0114] In some embodiments, a portion of the first gate dielectric film 251 and a portion of the first gate line 261 may be in the first recess R1. Specifically, the first gate dielectric film 251 may include a sub-portion 251_S in the first recess R1. Specifically, a portion 261_2S of the first work function metal layer 261_2N may be in the first recess R1. In some embodiments, the portion 261_2S of the first work function metal layer 261_2N in the first recess R1 may be stacked with the vertical structure 280 in the vertical direction (Z direction).

[0115] In some embodiments, a portion of the second gate dielectric film 252 and a portion of the second gate line 262 may be in the second recess R2. Specifically, the second gate dielectric film 252 may include a sub-portion 252_S in the second recess R2. Specifically, a portion 262_2S of the second work function metal layer 262_2P may be in the second recess R2. In some embodiments, the portion 262_2S of the second work function metal layer 262_2P in the second recess R2 may be stacked with the vertical structure 280 in the vertical direction (Z direction).

[0116] According to the inventive concept, an integrated circuit device 200 including a vertical structure 280 may be provided. The vertical structure 280 includes a first recess R1 and a second recess R2 on its sidewalls 280_S1 and 280_S2, respectively. Since portions of the first gate dielectric film 251, the second gate dielectric film 252, the first gate line 261, and the second gate line 262 are respectively disposed in the first recess R1 and the second recess R2 of the integrated circuit device 200, the effective channel width may be increased. Specifically, since the portion 261_2S of the first work function metal layer 261_2N and the portion 262_2S of the second work function metal layer 262_2P are respectively disposed in the first recess R1 and the second recess R2 of the integrated circuit device 200, the effective channel width may be increased. That is, according to the inventive concept, an integrated circuit device 200 having improved performance and reliability may be provided.

[0117] According to the inventive concept, an integrated circuit device 200 including a vertical structure 280 may be provided. The vertical structure 280 includes one or more air spaces 285 therein. Since the vertical structure 280 includes one or more air spaces 285 therein, the parasitic capacitance may be reduced. That is, according to the inventive concept, an integrated circuit device 200 having improved performance and reliability may be provided.

[0118] Figure 10 and Figure 11 are schematic cross-sectional views of an integrated circuit device 201 and 202 according to embodiments, respectively. Hereinafter, differences from the integrated circuit device 200 described with reference to Figure 8 and Figure 9 will be mainly described.

[0119] Referring to Figure 10 , the integrated circuit device 201 may include a substrate 210 including a first region 210_1 and a second region 210_2, a first fin-type active region FA1 extending in a first horizontal direction (X direction) on the first region 210_1, and a second fin-type active region FA2 extending in the first horizontal direction (X direction) on the second region 210_2.

[0120] In some embodiments, the first region 210_1 and the second region 210_2 of the integrated circuit device 201 may be doped with impurities of the same conduction type. For example, the first region 210_1 and the second region 210_2 of the integrated circuit device 201 may each be an nFET region. That is, the transistors formed in the portion of the integrated circuit device 201 where the first fin-type active region FA1 and the first gate line 261 cross each other above the first region 210_1 and the transistors formed in the portion of the integrated circuit device 201 where the second fin-type active region FA2 and the second gate line 262 cross each other above the second region 210_2 may each be an nFET.

[0121] In some embodiments, the first gate line 261 extending in the second horizontal direction (Y direction) may be disposed above the first fin-type active region FA1, and the second gate line 262 extending in the second horizontal direction (Y direction) may be disposed above the second fin-type active region FA2.

[0122] In some embodiments, the first gate line 261 may include a first main metal layer 261_1 and a first work function metal layer 261_2N. The second gate line 262 may include a second main metal layer 262_1 and a second work function metal layer 262_2N.

[0123] In some embodiments, the first work function metal layer 261_2N of the first gate line 261 and the second work function metal layer 262_2N of the second gate line 262 may include the same metal layer. For example, the first work function metal layer 261_2N and the second work function metal layer 262_2N may each include a metal for forming an nFET.

[0124] In some embodiments, the vertical structure 280 may be disposed between the first gate line 261 and the second gate line 262. The vertical structure 280 may include an insulating material. One or more air spaces 285 may be disposed in the vertical structure 280.

[0125] In some embodiments, the vertical structure 280 may include a first recess R1 on the first sidewall 280_S1 and a second recess R2 on the second sidewall 280_S2. In some embodiments, a sub-portion 251_S of the first gate dielectric film 251 and a portion of the first gate line 261 may be in the first recess R1. Specifically, a portion 261_2S of the first work function metal layer 261_2N may be in the first recess R1. In some embodiments, a sub-portion 252_S of the second gate dielectric film 252 and a portion of the second gate line 262 may be in the second recess R2. Specifically, a portion 262_2S of the second work function metal layer 262_2N may be in the second recess R2.

[0126] Refer toFigure 11 The integrated circuit device 202 may include a substrate 210 including a first region 210_1 and a second region 210_2, a first fin-type active region FA1 extending in a first horizontal direction (X direction) over the first region 210_1, and a second fin-type active region FA2 extending in the first horizontal direction (X direction) over the second region 210_2.

[0127] In some embodiments, the first region 210_1 and the second region 210_2 of the integrated circuit device 202 may be doped with impurities of the same conductivity type. For example, the first region 210_1 and the second region 210_2 of the integrated circuit device 202 may each be a pFET region. That is, the transistors formed in the portion of the integrated circuit device 202 where the first fin-type active region FA1 and the first gate line 261 cross each other above the first region 210_1 and the transistors formed in the portion of the integrated circuit device 202 where the second fin-type active region FA2 and the second gate line 262 cross each other above the second region 210_2 may each be a pFET.

[0128] In some embodiments, a first gate line 261 extending in a second horizontal direction (Y direction) may be disposed over the first fin-type active region FA1, and a second gate line 262 extending in the second horizontal direction (Y direction) may be disposed over the second fin-type active region FA2.

[0129] In some embodiments, the first gate line 261 may include a first main metal layer 261_1 and a first work function metal layer 261_2P. The second gate line 262 may include a second main metal layer 262_1 and a second work function metal layer 262_2P.

[0130] In some embodiments, the first work function metal layer 261_2P of the first gate line 261 and the second work function metal layer 262_2P of the second gate line 262 may include the same metal layer. For example, the first work function metal layer 261_2P and the second work function metal layer 262_2P may each include a metal for forming a pFET.

[0131] In some embodiments, a vertical structure 280 may be disposed between the first gate line 261 and the second gate line 262. The vertical structure 280 may include an insulating material. One or more air spaces 285 may be disposed in the vertical structure 280.

[0132] In some embodiments, the vertical structure 280 may include a first recess R1 on a first sidewall 280_S1 facing the first gate line 261 and a second recess R2 on a second sidewall 280_S2 facing the second gate line 262. In some embodiments, a sub-portion 251_S of the first gate dielectric film 251 and a portion of the first gate line 261 may be in the first recess R1. Specifically, a portion 261_2S of the first work function metal layer 261_2P may be in the first recess R1. In some embodiments, a sub-portion 252_S of the second gate dielectric film 252 and a portion of the second gate line 262 may be in the second recess R2. Specifically, a portion 262_2S of the second work function metal layer 262_2P may be in the second recess R2.

[0133] Figures 12A to 12F is a schematic cross-sectional view showing an intermediate process in an exemplary method of manufacturing an integrated circuit device 100 according to one or more embodiments.

[0134] Referring Figure 12A , a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers may be alternately stacked one by one in a vertical direction (i.e., the Z direction) on a substrate 110, and then, by etching portions of the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers, and the substrate 110, a plurality of fin-type active regions FA may be defined in the substrate 110. Thereafter, a device isolation film 114 may be formed to cover sidewalls of each of the plurality of fin-type active regions FA.

[0135] The plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers may include semiconductor materials having different etching selectivities. In some embodiments, the plurality of nanosheet semiconductor layers may include Si layers, and the plurality of sacrificial semiconductor layers 104 may include SiGe layers. In some embodiments, the Ge content in the plurality of sacrificial semiconductor layers 104 may be constant. The SiGe layers constituting the plurality of sacrificial semiconductor layers 104 may have a constant Ge content selected from a range of about 5 atomic percent (at%) to about 60 at% (e.g., about 10 at% to about 40 at%). The Ge content in the SiGe layers constituting the plurality of sacrificial semiconductor layers 104 may be selected in various ways as needed.

[0136] Subsequently, by etching a portion of each of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers and a portion of the fin-type active regions FA, the plurality of nanosheet semiconductor layers may be divided into a plurality of nanosheet stacks NSS. Thereafter, a portion of the device isolation film 114 between the plurality of fin-type active regions FA may be etched to form a trench.

[0137] Referring Figure 12B, semiconductor material can be epitaxially grown from the sidewalls of a plurality of sacrificial semiconductor layers 104 exposed through the trenches. As a result, a plurality of dummy blocks 105 can be formed to protrude respectively from the sidewalls of the plurality of sacrificial semiconductor layers 104 in the second horizontal direction (Y direction).

[0138] In some embodiments, an Si source and a Ge source can be used to form the plurality of dummy blocks 105. The plurality of dummy blocks 105 can include SiGe layers.

[0139] In some embodiments, the width of the plurality of dummy blocks 105 in the vertical direction (Z direction) can be less than or equal to the width of the plurality of sacrificial semiconductor layers 104 in the vertical direction (Z direction).

[0140] In some other embodiments not explicitly shown, the width of each of the plurality of dummy blocks 105 in the vertical direction (Z direction) can be greater than the width of each of the plurality of sacrificial semiconductor layers 104 in the vertical direction (Z direction). In this case, the integrated circuit device 102 described with reference to Figure 5 can be manufactured.

[0141] With reference to Figure 12C , a vertical structure 180 can be formed in the trench. Specifically, the trench can be filled with a dielectric material to form the vertical structure 180 disposed between the first fin-type active region FA1 and the second fin-type active region FA2, and between the first nanosheet stack NSS1 and the second nanosheet stack NSS2.

[0142] In some embodiments, in the process of forming the vertical structure 180, due to the presence of the plurality of dummy blocks 105, one or more air spaces 185 can be formed in the vertical structure 180. Specifically, due to the presence of the plurality of dummy blocks 105, the dielectric material can be folded to form one or more air spaces 185 in the vertical structure 180. The one or more air spaces 185 can be formed to overlap with the plurality of nanosheets in the second horizontal direction (Y direction).

[0143] With reference to Figure 12D , the plurality of sacrificial semiconductor layers 104 and the plurality of dummy blocks 105 can be removed to expose the plurality of nanosheet stacks NSS. Specifically, the plurality of nanosheets included in the plurality of nanosheet stacks NSS, the fin top surface FT, and the two sidewalls (i.e., opposite sidewalls) of the vertical structure 180 can be exposed.

[0144] A first recess R1 and a second recess R2 can be formed on the two exposed sidewalls of the vertical structure 180. The first recess R1 and the second recess R2 can be formed as some regions of the trench that are not filled with the dielectric material due to the plurality of dummy blocks 105 (see Figure 12C ).

[0145] With reference toFigure 12E , a first gate dielectric film 151 and a second gate dielectric film 152 can be formed to cover sidewalls of the vertical structure 180 and sidewalls of the plurality of nanosheet stacks NSS.

[0146] Specifically, the first gate dielectric film 151 can be formed on top surfaces, bottom surfaces, and sidewalls of the first to third nanosheets N11, N12, and N13 included in the first nanosheet stack NSS1, the top surface of the first fin FT1, the device isolation film 114, and sidewalls of the vertical structure 180 (including exposed surfaces of the first recess R1). Specifically, the second gate dielectric film 152 can be formed on top surfaces, bottom surfaces, and sidewalls of the first to third nanosheets N21, N22, and N23 included in the second nanosheet stack NSS2, the top surface of the second fin FT2, the device isolation film 114, and sidewalls of the vertical structure 180 (including exposed surfaces of the second recess R2).

[0147] As described above, the first gate dielectric film 151 and the second gate dielectric film 152 can include sub - portions respectively disposed in the first recess R1 and the second recess R2. For example, the first gate dielectric film 151 can include a sub - portion 151_S disposed in the first recess R1. The second gate dielectric film 152 can include a sub - portion 152_S disposed in the second recess R2.

[0148] Referring to Figure 12F , a gate line 160 can be formed on the first gate dielectric film 151 and the second gate dielectric film 152. Specifically, a first gate line 161 can be formed above the first fin - type active region FA1, and a second gate line 162 can be formed above the second fin - type active region FA2.

[0149] By performing Figures 12A to 12F 's manufacturing method, an integrated circuit device 100 (see Figures 1 to 3 ) can be manufactured.

[0150] Figure 13A and Figure 13B are schematic cross - sectional views showing intermediate processes in an example method for manufacturing an integrated circuit device 200 (see Figure 8 ). Specifically, according to some embodiments, it can be performed after the process described with reference to Figure 12E the example method for manufacturing the integrated circuit device 200 ( Figure 13A and Figure 13B ) shown in Figure 8 .

[0151] Referring to Figure 13A, a first work function metal layer 261_2N and a second work function metal layer 262_2P can be formed on the first gate dielectric film 251 and the second gate dielectric film 252, respectively. Specifically, above the first fin-type active region FA1, the first work function metal layer 261_2N can be formed on the first gate dielectric film 251, and above the second fin-type active region FA2, the second work function metal layer 262_2P can be formed on the second gate dielectric film 252.

[0152] Specifically, the first work function metal layer 261_2N can be formed on the top surfaces, bottom surfaces, and sidewalls of the first to third nanosheets N11, N12, and N13 included in the first nanosheet stack NSS1, the first fin top surface FT1, the device isolation film 214, and the sidewalls of the vertical structure 280. Specifically, the second work function metal layer 262_2P can be formed on the top surfaces, bottom surfaces, and sidewalls of the first to third nanosheets N21, N22, and N23 included in the second nanosheet stack NSS2, the second fin top surface FT2, the device isolation film 214, and the sidewalls of the vertical structure 280.

[0153] As described above, the first work function metal layer 261_2N and the second work function metal layer 262_2P can include portions respectively disposed in the first recess R1 and the second recess R2. For example, the first work function metal layer 261_2N can include a portion 261_2S in the first recess R1. The second work function metal layer 262_2P can include a portion 262_2S in the second recess R2.

[0154] Referring to Figure 13B , a first main metal layer 261_1 and a second main metal layer 262_1 can be formed on the first work function metal layer 261_2N and the second work function metal layer 262_2P, respectively. Specifically, by forming the first main metal layer 261_1 on the first work function metal layer 261_2N, the first gate line 261 can be formed. By forming the second main metal layer 262_1 on the second work function metal layer 262_2P, the second gate line 262 can be formed.

[0155] By performing Figure 13A and Figure 13B 's manufacturing method, the integrated circuit device 200 (see Figure 8 ) can be manufactured.

[0156] According to the inventive concept, an integrated circuit device having improved performance and reliability can be provided.

[0157] Although the inventive concept has been specifically shown and described with reference to the embodiments of the inventive concept, it should be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: A fin-type active region extending in a first horizontal direction on a substrate, the first horizontal direction being parallel to the upper surface of the substrate; A nanosheet stack including a plurality of nanosheets on the fin-type active region; A gate line extending around each of the plurality of nanosheets on the fin-type active region and extending in a second horizontal direction parallel to the upper surface of the substrate and intersecting the first horizontal direction; And A vertical structure at least partially overlapping the gate line in the second horizontal direction and including sidewalls in contact with each of the plurality of nanosheets, Wherein the vertical structure further includes a recess on the sidewalls of the vertical structure.

2. The integrated circuit device according to claim 1, wherein, The gate line includes a protrusion extending into the recess.

3. The integrated circuit device according to claim 2, wherein, The protrusion at least partially overlaps the vertical structure in a vertical direction perpendicular to the upper surface of the substrate.

4. The integrated circuit device according to claim 1, wherein, The recess includes a portion overlapping at least a part of the plurality of nanosheets in the second horizontal direction.

5. The integrated circuit device according to claim 1, wherein The gate line includes: A main metal layer; and A work function metal layer between the main metal layer and each of the plurality of nanosheets and between the main metal layer and the vertical structure, Wherein the work function metal layer includes a portion in the recess.

6. The integrated circuit device according to claim 1, wherein, The vertical structure further includes: an air space within the vertical structure.

7. The integrated circuit device according to claim 6, wherein, The air space overlaps at least a part of the plurality of nanosheets in the second horizontal direction.

8. An integrated circuit device, comprising: A substrate including a first region and a second region; A first fin-type active region extending in a first horizontal direction parallel to the upper surface of the substrate on the first region; A second fin-type active region extending in the first horizontal direction on the second region and spaced apart from the first fin-type active region in a second horizontal direction parallel to the upper surface of the substrate and intersecting the first horizontal direction; A plurality of first nanosheets facing the top surface of the first fin-type active region and spaced apart from the top surface of the first fin-type active region in a vertical direction perpendicular to the upper surface of the substrate; A plurality of second nanosheets facing the top surface of the second fin-type active region and spaced apart from the top surface of the second fin-type active region in the vertical direction; A first gate line extending around each of the plurality of first nanosheets on the first fin-type active region and extending in the second horizontal direction; A second gate line extending around each of the plurality of second nanosheets on the second fin-type active region and extending in the second horizontal direction; And A vertical structure between the first gate line and the second gate line and having two sidewalls respectively in contact with each of the plurality of first nanosheets and each of the plurality of second nanosheets, Wherein each of the two sidewalls of the vertical structure includes a recess extending into the vertical structure, and Each of the first gate line and the second gate line includes a protrusion extending into the recess.

9. The integrated circuit device according to claim 8, wherein, The first gate line includes: a first main metal layer; and a first work function metal layer between the first main metal layer and each of the plurality of first nanosheets and between the first main metal layer and the vertical structure, and The second gate line includes: a second main metal layer; and a second work function metal layer, between the second main metal layer and each of the plurality of second nanosheets and between the second main metal layer and the vertical structure, wherein each of the first work function metal layer and the second work function metal layer includes a portion in the recess.

10. The integrated circuit device according to claim 8, wherein, The vertical structure further includes: an air space, within the vertical structure.

11. The integrated circuit device according to claim 10, wherein, The air space at least partially overlaps at least a portion of the first plurality of nanosheets and the second plurality of nanosheets in a second horizontal direction.

12. The integrated circuit device according to claim 8, wherein, The recess includes a portion that at least partially overlaps at least a portion of the first plurality of nanosheets and the second plurality of nanosheets in a second horizontal direction.

13. The integrated circuit device according to any one of claims 8 to 12, further comprising: a first gate dielectric film, between the first gate line and each of the plurality of first nanosheets and between the first gate line and the vertical structure; and a second gate dielectric film, between the second gate line and each of the plurality of second nanosheets and between the second gate line and the vertical structure, wherein each of the first gate dielectric film and the second gate dielectric film includes a sub-portion in the recess.

14. The integrated circuit device according to claim 13, wherein, The sub-portion of each of the first gate dielectric film and the second gate dielectric film at least partially overlaps the vertical structure in a vertical direction.

15. The integrated circuit device according to claim 8, wherein, Two sidewalls of the vertical structure include a first sidewall and a second sidewall, the first sidewall faces the first gate line, and the second sidewall faces the second gate line, wherein the first sidewall includes a first recess, the second sidewall includes a second recess, and a first width of the first recess in a vertical direction is different from a second width of the second recess in a vertical direction.

16. The integrated circuit device according to claim 8, wherein, The first fin-type active region and the second fin-type active region have different conductivity types, and the vertical structure includes a dielectric material.

17. An integrated circuit device, comprising: a substrate, including a first region and a second region; a first fin-type active region, extending in a first horizontal direction parallel to an upper surface of the substrate on the first region; a second fin-type active region, extending in the first horizontal direction on the second region and spaced apart from the first fin-type active region in a second horizontal direction parallel to the upper surface of the substrate and intersecting the first horizontal direction; a first nanosheet stack, including a plurality of first nanosheets at different heights in a vertical direction perpendicular to the upper surface of the substrate with respect to the upper surface of the substrate as a reference layer, each of the plurality of first nanosheets faces a top surface of the first fin-type active region and is spaced apart from the top surface of the first fin-type active region in a vertical direction; a second nanosheet stack, including a plurality of second nanosheets at different heights in a vertical direction with respect to the upper surface of the substrate, each of the plurality of second nanosheets faces a top surface of the second fin-type active region and is spaced apart from the top surface of the second fin-type active region in a vertical direction; a first gate line, extending around each of the plurality of first nanosheets on the first fin-type active region and extending in the second horizontal direction; a second gate line, extending around each of the plurality of second nanosheets on the second fin-type active region and extending in the second horizontal direction; A vertical structure, between the first gate line and the second gate line, and in contact with each of the plurality of first nanosheets and each of the plurality of second nanosheets; A first source / drain region, adjacent to the first gate line, and in contact with each of the plurality of first nanosheets; And A second source / drain region, adjacent to the second gate line, and in contact with each of the plurality of second nanosheets, Wherein, the first gate line includes: a first main metal layer; and a first work function metal layer, between the first main metal layer and each of the plurality of first nanosheets and between the first main metal layer and the vertical structure, The second gate line includes: a second main metal layer; and a second work function metal layer, between the second main metal layer and each of the plurality of second nanosheets and between the second main metal layer and the vertical structure, The vertical structure includes: an air space, within the vertical structure, The vertical structure further includes a first sidewall and a second sidewall, the first sidewall faces the first gate line, and the second sidewall faces the second gate line, The first sidewall includes a first recess, The second sidewall includes a second recess, The first work function metal layer includes a portion that is within the first recess and at least partially overlaps the vertical structure in the vertical direction, and The second work function metal layer includes a portion that is within the second recess and at least partially overlaps the vertical structure in the vertical direction.

18. The integrated circuit device according to claim 17, wherein, Both the first region and the second region include an n-type field effect transistor region or a p-type field effect transistor region, and The vertical structure includes an insulating material.

19. The integrated circuit device according to claim 17, wherein, The first region includes an n-type field effect transistor region, The second region includes a p-type field effect transistor region, The vertical structure includes a dielectric material, The first work function metal layer includes an n-type metal layer, and The second work function metal layer includes a p-type metal layer.

20. The integrated circuit device according to claim 17, wherein, The air space at least partially overlaps each of the plurality of first nanosheets and each of the plurality of second nanosheets in the second horizontal direction.

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