Preparation method of composite optical waveguide modulator and composite optical waveguide modulator

Abstract

The invention relates to the technical field of semiconductors, and discloses a preparation method of a composite optical waveguide modulator and the composite optical waveguide modulator.The preparation method comprises the steps that a waveguide wafer is provided, and the waveguide wafer comprises a substrate layer, a first wrapping layer and a plurality of waveguide structures; the surface of the side, away from the substrate layer, of the first cladding is etched, and grooves are formed in the two sides of the waveguide structure; forming a first conductive layer in the groove; forming a second cladding on the surface of one side, far away from the first cladding, of the first conductive layer, wherein the thickness of the second cladding is greater than the target thickness required by the bonding layer; polishing the second cladding to form a bonding layer; a plurality of second conductive layers arranged at intervals are formed on the surface of the side, away from the first wrapping layer, of the bonding layer, and the first conductive layer and the second conductive layers are electrically connected; and carrying out bonding processing on the modulator chip and the surface of one side, far away from the first cladding, of the bonding layer to obtain the composite optical waveguide modulator. Compared with the prior art, the flatness of the bonding interface is higher.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a preparation method of a composite optical waveguide modulator and a composite optical waveguide modulator. Background Art

[0002] A composite optical waveguide modulator is an optical waveguide modulator composed of multiple materials or structures, which can achieve efficient transmission and regulation of optical signals, and is thus widely used in the fields of optical communication, integrated photonics, and sensing technology. A composite optical waveguide modulator generally includes a modulator chip, a waveguide structure, and a conductive structure. Related technologies can bond the modulator chip to the wafer of the waveguide structure through the chip-to-wafer bonding method, and realize the preparation of the composite optical waveguide modulator by reasonably regulating the distance between the optical waveguide and the modulator chip.

[0003] When preparing a composite optical waveguide modulator by the above bonding method, in order to ensure the efficiency of the composite optical waveguide, it is necessary to strictly control the surface quality of the bonding layer. However, when preparing the conductive structure in the grooves on both sides of the waveguide structure by dry etching, it is easy to cause etching residues of the conductive material in the grooves. When removing the dry etching residues by wet etching, it is easy to cause damage to the conductive structure and affect the electrical performance. At the same time, the patterned conductive structure and the grooves have a step fluctuation caused by the height difference. After covering the cladding and polishing, this step fluctuation will be transmitted to the bonding interface, causing the problem of uneven bonding interface, and further reducing the bonding reliability. Summary of the Invention

[0004] In view of this, the present invention provides a preparation method of a composite optical waveguide modulator and a composite optical waveguide modulator to solve the problem of low flatness of the bonding layer surface in related technologies.

[0005] In a first aspect, the present invention provides a preparation method of a composite optical waveguide modulator, the method comprising: providing a waveguide wafer, wherein the waveguide wafer includes a substrate layer, a first cladding layer, and a plurality of waveguide structures, the first cladding layer is located on one side surface of the substrate layer, and the plurality of waveguide structures are arranged at intervals in the first cladding layer; etching the side surface of the first cladding layer away from the substrate layer to form grooves on both sides of the waveguide structure; forming a first conductive layer in the grooves; forming a second cladding layer on the side surface of the first conductive layer away from the first cladding layer, wherein the thickness of the second cladding layer is greater than the target thickness required for the bonding layer; polishing the second cladding layer to form a bonding layer; forming a plurality of second conductive layers arranged at intervals on the side surface of the bonding layer away from the first cladding layer, wherein the first conductive layer and the second conductive layer are electrically connected; bonding the modulator chip to the side surface of the bonding layer away from the first cladding layer to obtain a composite optical waveguide modulator.

[0006] The preparation method of the composite optical waveguide adjuster provided by the present invention is as follows: after forming the first conductive layer, a second cladding layer is formed on the surface of the first conductive layer away from the first cladding layer, and the second cladding layer is polished to form a bonding layer. Using the polished second cladding layer as the bonding layer, the flatness of the bonding interface can be flexibly adjusted according to requirements, thereby improving the stability of the subsequent bonding process, as well as controlling the stability and efficiency of the optical performance of the composite optical waveguide adjuster. Moreover, before forming the first conductive layer, the waveguide structure is disposed within the first cladding layer, and the first cladding layer located on the waveguide structure can serve as a buffer layer for the subsequent polishing process to avoid damaging the waveguide structure.

[0007] In an alternative embodiment, polishing the second cladding layer to form the bonding layer includes: polishing the second cladding layer by chemical mechanical planarization to form the bonding layer.

[0008] In this embodiment, polishing the second cladding layer by chemical mechanical planarization can control the flatness of the bonding interface at the nanometer level, meeting the requirements for the surface flatness of the bonding layer.

[0009] In an alternative embodiment, the thickness of the bonding layer ranges from 90 nm to 110 nm.

[0010] In an alternative embodiment, forming the first conductive layer in the groove includes: electroplating a first conductive material on the surface of the groove and the first cladding layer away from the substrate layer, where the first conductive material covers the groove and the first cladding layer; polishing the first conductive material by chemical mechanical planarization until a plurality of waveguide structures are exposed to form the first conductive layer.

[0011] In this embodiment, processing the first conductive layer by the damascene process is beneficial for fine processing and can more accurately control the processing accuracy of the first conductive layer.

[0012] In an alternative embodiment, forming a plurality of spaced second conductive layers on the surface of the bonding layer away from the first cladding layer includes: forming a protective layer on the surface of the bonding layer away from the first cladding layer; etching the surface of the protective layer away from the bonding layer to form a bonding area protective layer and a through hole area protective layer; forming a third cladding layer on the surface of the bonding area protective layer and the through hole area protective layer away from the bonding layer; etching the third cladding layer, the through hole area protective layer, and the bonding layer to form through holes, where the through holes expose the first conductive layer; forming an interconnect structure in the through holes; forming a second conductive material on the surface of the third cladding layer away from the bonding layer; etching the second conductive material to form a plurality of spaced second conductive layers.

[0013] In an alternative embodiment, etching the third cladding layer, the via region protection layer, and the bonding layer to form a via includes: etching the third cladding layer by a dry etching method until the via region protection layer is exposed; etching the via region protection layer by a wet etching method to expose the bonding layer; and etching the bonding layer by a dry etching method until the first conductive layer is exposed to form a via.

[0014] In this embodiment, after the via region protection layer is formed on one side surface of the bonding layer, it is etched to form a via. The via region protection layer can indicate the etching position to avoid over-etching the first conductive layer and affecting the surface flatness of the first conductive layer.

[0015] In an alternative embodiment, before bonding the modulator chip to the side surface of the bonding layer away from the first cladding layer, the method further includes: forming a fourth cladding layer on the side surface of the second conductive layer away from the third cladding layer; and etching the side surface of the fourth cladding layer away from the third cladding layer to form a pad window, where the pad window exposes the second conductive layer.

[0016] In an alternative embodiment, after forming the fourth cladding layer on the side surface of the second conductive layer away from the third cladding layer, the method further includes: etching the fourth cladding layer and the third cladding layer by a dry etching method until the bonding region protection layer is exposed; and etching the bonding region protection layer by a wet etching method to form an opening, where the opening exposes the bonding layer.

[0017] In this embodiment, after the bonding region protection layer is formed on one side surface of the bonding layer, it is etched to form an opening. The bonding region protection layer can indicate the etching position to avoid over-etching the bonding layer and affecting the flatness of the bonding interface.

[0018] In an alternative embodiment, the thickness of the protection layer ranges from 90 nm to 200 nm.

[0019] In an alternative embodiment, bonding the modulator chip to the side surface of the bonding layer away from the first cladding layer includes: performing a pre-bonding process on the side surface of the modulator chip and the bonding layer away from the first cladding layer; and after the pre-bonding process, performing a thermocompression bonding process on the side surface of the modulator chip and the bonding layer away from the first cladding layer to obtain a composite optical waveguide modulator.

[0020] In this embodiment, first, a pre-bonding process is performed on the surface of the modulator chip and the bonding layer on the side away from the first cladding, and then a thermocompression bonding process is performed on the surface of the modulator chip and the bonding layer on the side away from the first cladding. During the pre-bonding process, the bonding position of the modulator chip can be adjusted to improve the bonding accuracy. Moreover, pre-bonding can activate the bonding energy on the surface of the modulator chip and the bonding layer on the side away from the first cladding, laying a foundation for subsequent thermocompression bonding.

[0021] In an alternative embodiment, the process parameters of the pre-bonding process include: the first bonding pressure is 0; the value range of the first bonding temperature is from 20°C to 300°C; the value range of the first bonding time is from 1 h to 12 h; the process parameters of the thermocompression bonding process include: the second bonding pressure is less than or equal to 2000 N; the value range of the second bonding temperature is from 100°C to 300°C; the value range of the second bonding time is from 1 h to 12 h.

[0022] In a second aspect, the present invention provides a composite optical waveguide modulator, which is prepared by the preparation method of the composite optical waveguide modulator according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 is a schematic flowchart of a preparation method of a composite optical waveguide modulator according to an embodiment of the present invention.

[0025] Figure 2 is a schematic diagram of a waveguide wafer structure according to an embodiment of the present invention.

[0026] Figure 3 is based on an embodiment of the present invention in Figure 2 a schematic diagram of a semiconductor structure with a groove formed thereon.

[0027] Figure 4 is based on an embodiment of the present invention in Figure 3 a schematic diagram of a semiconductor structure with a first conductive material electroplated on the surface of the groove and the first cladding.

[0028] Figure 5 is based on an embodiment of the present invention in Figure 4 a schematic diagram of a semiconductor structure with the first conductive material polished to form a first conductive layer.

[0029] Figure 6 is a schematic diagram of a semiconductor structure that forms a second cladding on a first conductive layer and a plurality of waveguide structures based on Figure 5 the following.

[0030] Figure 7 is a schematic diagram of a semiconductor structure that polishes the second cladding to form a bonding layer based on Figure 6 the following.

[0031] Figure 8 is a schematic diagram of a semiconductor structure that forms a protective layer on the surface of the bonding layer based on Figure 7 the following.

[0032] Figure 9 is a schematic diagram of a semiconductor structure that etches the protective layer to form a bonding area protective layer and a via area protective layer based on Figure 8 the following.

[0033] Figure 10 is a schematic diagram of a semiconductor structure that forms a third cladding on the surfaces of the bonding layer and the protective layer based on Figure 9 the following.

[0034] Figure 11 is a schematic diagram of a semiconductor structure that etches the third cladding to form a third cladding via based on Figure 10 the following.

[0035] Figure 12 is a schematic diagram of a semiconductor structure that etches the via area protective layer to form a via area protective layer via based on Figure 11 the following.

[0036] Figure 13 is a schematic diagram of a semiconductor structure that etches the bonding layer to form a via based on Figure 12 the following.

[0037] Figure 14 is a schematic diagram of a semiconductor structure that forms an electrical connection material on the surfaces of the first conductive layer and the third cladding based on Figure 13 the following.

[0038] Figure 15 is a schematic diagram of a semiconductor structure that polishes the electrical connection material to form an electrical connection structure based on Figure 14 the following.

[0039] Figure 16 is a schematic diagram of a semiconductor structure that based on Figure 15Schematic diagram of a semiconductor structure in which a second conductive layer is formed on the surface of a third cladding layer on the basis of

[0040] Figure 17 is based on the embodiment of the present invention Figure 16 Schematic diagram of a semiconductor structure in which a fourth cladding layer is formed on the surfaces of a third cladding layer and a second conductive layer on the basis of

[0041] Figure 18 is based on the embodiment of the present invention Figure 17 Schematic diagram of a semiconductor structure in which a fourth cladding layer and a third cladding layer are etched to expose a bonding area protection layer on the basis of

[0042] Figure 19 is based on the embodiment of the present invention Figure 18 Schematic diagram of a semiconductor structure in which a bonding area protection layer is etched to expose a bonding layer on the basis of

[0043] Figure 20 is based on the embodiment of the present invention Figure 19 Schematic diagram of a semiconductor structure in which a fourth cladding layer is etched to form a pad window on the basis of

[0044] Figure 21 is based on the embodiment of the present invention Figure 20 Schematic diagram of a semiconductor structure in which a modulator chip is bonded to the surface of a bonding layer to form a composite optical waveguide modulator on the basis of

[0045] Reference numerals: 100, waveguide wafer; 110, substrate layer; 120, first cladding layer; 130, waveguide structure; 140, thermal oxide layer; 210, groove; 220, first conductive layer; 230, first conductive material; 310, second cladding layer; 410, bonding layer; 420, protection layer; 421, bonding area protection layer; 422, via area protection layer; 510, interconnect structure; 520, second conductive layer; 530, third cladding layer; 531, first dielectric via; 532, second dielectric via; 533, via; 540, third conductive material; 610, modulator chip; 620, fourth cladding layer; 630, pad window. Detailed implementation manners

[0046] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that for the sake of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0047] In the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various schematic structural diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. Furthermore, the terms "first", "second", and "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0048] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "mount", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0049] With the rapid development of optical communication, integrated photonics, and sensing technologies, the performance requirements for optical waveguides in related fields are increasing day by day. Waveguides with a single structure have become difficult to meet the needs of complex application scenarios in related fields. Composite optical waveguides are waveguide technologies that achieve specific optical properties by combining multiple materials or structural designs. Their core advantage lies in the ability to flexibly control the transmission characteristics of the optical field, thereby meeting the needs of different application scenarios. How to firmly combine different materials or structures together and ensure the stability and efficiency of the optical performance of the composite optical waveguide is a key challenge faced in the preparation process of the composite optical waveguide.

[0050] Bonding technology is exactly the core means to solve this problem. Bonding not only needs to physically achieve the tight combination of materials but also ensure low loss and high stability of the optical interface. As mentioned in the background technology, the flatness of the bonding interface directly affects the coupling between the modulator chip and the waveguide structure. Therefore, ensuring the high flatness of the bonding interface has become a key issue in the process of preparing composite optical waveguide modulators.

[0051] Such asFigure 1 As shown, this embodiment provides a method for fabricating a compound optical waveguide modulator, and the fabrication method includes but is not limited to steps S10 to S16.

[0052] Step S10: Provide a waveguide wafer.

[0053] Among them, as Figure 2 shown, the waveguide wafer 100 includes a substrate layer 110, a first cladding layer 120, and a plurality of waveguide structures 130. The first cladding layer 120 is located on one side surface of the substrate layer 110, and the plurality of waveguide structures 130 are arranged at intervals in the first cladding layer 120. The arrangement pattern of the plurality of waveguide structures 130 can be determined by designers according to processing requirements.

[0054] Exemplarily, the first spacing between the side surface of the waveguide structure 130 facing away from the substrate layer 110 and the side surface of the first cladding layer 120 facing away from the substrate layer 110 can be 100 nm to 200 nm. For example, the first spacing can be 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0055] In this embodiment, the waveguide structure 130 is disposed within the first cladding layer 120, and the first cladding layer 120 located on the waveguide structure 130 can serve as a buffer layer for subsequent polishing processes to avoid damaging the waveguide structure.

[0056] Exemplarily, the material of the substrate layer 110 can be silicon (Si), the material of the first cladding layer 120 can be silicon dioxide (SiO2), and the material of the waveguide structure 130 can be silicon nitride (SiN).

[0057] Optionally, as Figure 2 shown, the waveguide wafer 100 further includes a thermal oxide layer 140, and the thermal oxide layer 140 is located between the substrate layer 110 and the first cladding layer 120. Among them, the material of the thermal oxide layer 140 can be silicon dioxide (SiO2).

[0058] Step S11: Etch the side surface of the first cladding layer away from the substrate layer to form grooves on both sides of the waveguide structure.

[0059] Exemplarily, patterning lithographic etching can be performed on the first cladding layer 120 and the thermal oxide layer 140 to obtain the grooves 210 as Figure 3 shown, wherein the bottom of the grooves 210 can be located in the thermal oxide layer 140.

[0060] Specifically, a photoresist solution can be dropped onto the first cladding layer 120, and a uniform photoresist film is formed by high-speed rotation; the position where the groove 210 is to be formed is marked on the photoresist film, the mask is aligned with the mark, and then projection exposure is performed through an optical system; a developer is sprayed onto the exposed waveguide film to dissolve the exposed area, and then deionized water is used to terminate the developing reaction to remove the residual developer; the first cladding layer 120 and the thermal oxide layer 140 that are not protected by the photoresist are selectively removed by dry etching to form the groove 210; acetone or a special photoresist remover is used to completely remove the residual photoresist and etching by-products.

[0061] Step S12, forming a first conductive layer in the groove.

[0062] Specifically, step S12 may include step S121 and step S122:

[0063] Step S121, electroplating a first conductive material on the surface of the groove and the side of the first cladding layer away from the substrate layer.

[0064] Among them, the first conductive material may be metallic copper (Cu).

[0065] Specifically, as Figure 4 shown, the first conductive material 230 can be electroplated to cover the groove 210 and the first cladding layer 120.

[0066] Step S122, performing a polishing treatment on the first conductive material by chemical mechanical planarization until multiple waveguide structures are exposed to form the first conductive layer.

[0067] Specifically, the damascene process can be adopted to perform CMP (Chemical Mechanical Planarization) treatment on the first conductive material 230 as Figure 4 shown, and the stop position of the polishing treatment is the waveguide structure 130 to form the first conductive layer 220 as Figure 5 shown. Among them, the thickness of the removed first cladding layer 120 is equal to the first pitch.

[0068] Step S13, forming a second cladding layer on the surface of the first conductive layer away from the first cladding layer.

[0069] Among them, the material of the second cladding layer can also be silicon dioxide (SiO2), and the thickness of the second cladding layer is greater than the target thickness required for the bonding layer. The target thickness required for the bonding layer can be determined by designers based on the coupling degree between the modulator chip and the waveguide structure 130. For example, the value range of the target thickness required for the bonding layer can be from 90 nm to 110 nm. For example, the thickness of the bonding layer can be 90 nm, 95 nm, 100 nm, 105 nm or 110 nm, etc.

[0070] Specifically, bonding not only requires a tight fit between different materials, but is also very sensitive to the distance between the modulator chip and the waveguide structure. The modulator chip and the waveguide structure can only be coupled at a specific distance to form a composite optical waveguide device.

[0071] For example, if the target thickness is 110 nm, the thickness of the second cladding layer needs to be greater than 110 nm.

[0072] Exemplarily, the thickness range of the second cladding layer can be from 120 nm to 500 nm. For example, the thickness of the second cladding layer can be 120 nm, 200 nm, 300 nm, 400 nm, or 500 nm, etc.

[0073] Specifically, after obtaining the semiconductor structure as Figure 5 shown, a second cladding layer 310 can be deposited on the surfaces of the waveguide structure 130, the first conductive layer 220, and the first cladding layer 120 away from the substrate layer 110 to form a semiconductor structure as Figure 6 shown.

[0074] Exemplarily, the second cladding layer 310 can be formed on the surface of the first conductive layer 220 away from the first cladding layer 120 by PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0075] Step S14: Polish the second cladding layer to form a bonding layer.

[0076] Specifically, the second cladding layer 310 can be polished by CMP to make the thickness of the second cladding layer 310 the target thickness required for the bonding layer 410, thereby forming the bonding layer 410 as Figure 7 shown. Among them, the surface of the bonding layer 410 facing away from the first cladding layer 120 is the bonding interface.

[0077] Step S15: Form a plurality of second conductive layers arranged at intervals on the surface of the bonding layer away from the first cladding layer.

[0078] Among them, the first conductive layer and the second conductive layer form an electrical connection.

[0079] Specifically, a second conductive material can be deposited on the surface of the bonding layer away from the first cladding layer, and then the second conductive material is patterned and etched to form the second conductive layer 520 as Figure 16 shown.

[0080] Among them, the material of the second conductive layer 520 can be metal aluminum (Al), metal copper (Cu), or aluminum-copper alloy (AlCu), etc.

[0081] Step S16: Bond the surface of the modulator chip and the bonding layer away from the first cladding to obtain a composite optical waveguide modulator.

[0082] Specifically, after forming the bonding layer, a thermocompression bonding process can be performed on the surface of the modulator chip 610 away from the first cladding (i.e., the bonding interface) of the bonding layer, thereby obtaining a composite optical waveguide modulator as shown in Figure 21 the figure.

[0083] Among them, the material of the modulator chip 610 can be lithium niobate (LiNbO3).

[0084] In the method for preparing the composite optical waveguide adjuster provided by the present invention, after forming the first conductive layer, a second cladding is formed on the surface of the first conductive layer away from the first cladding, and the second cladding is polished to form a bonding layer. The polished second cladding is used as the bonding layer, and the flatness of the bonding interface can be flexibly adjusted according to requirements, thereby improving the stability of the subsequent bonding process, as well as controlling the stability and efficiency of the optical performance of the composite optical waveguide adjuster. Moreover, before forming the first conductive layer, the waveguide structure is disposed in the first cladding, and the first cladding located on the waveguide structure can be used as a buffer layer for the subsequent polishing process to avoid damaging the waveguide structure.

[0085] Exemplarily, the process of forming a waveguide wafer as shown in Figure 2 the figure may include: forming a thermal oxide layer 140 on one surface of the substrate layer 110; forming a first sub-cladding on the surface of the thermal oxide layer 140 away from the substrate layer 110; forming a waveguide thin film on the surface of the first sub-cladding away from the thermal oxide layer 140; etching the waveguide thin film to obtain a plurality of spaced waveguide structures 130; forming a second sub-cladding on the surface of the plurality of spaced waveguide structures 130 away from the first sub-cladding; and polishing the second sub-cladding so that the first sub-cladding and the second sub-cladding form a first cladding 120.

[0086] Specifically, the waveguide thin film can be formed on the surface of the first sub-cladding away from the thermal oxide layer 140 by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD. It should be understood that the thickness of the second sub-cladding after polishing is the above-mentioned first spacing.

[0087] In some embodiments, forming a plurality of spaced second conductive layers on the surface of the bonding layer away from the first cladding (i.e., step S15) includes steps S151 to S158:

[0088] Step S151: Form a protective layer on the surface of the bonding layer away from the first cladding layer.

[0089] Specifically, as Figure 8 shown, a protective layer 420 can be formed on the surface of the bonding layer 410 away from the first cladding layer 120 by PECVD.

[0090] Among them, the material of the protective layer 420 can be titanium nitride (TiN), aluminum (Al), aluminum-copper alloy (AlCu), polysilicon (α-Si), etc. The thickness of the protective layer 420 can range from 90 nm to 200 nm. For example, the thickness of the protective layer 420 can be 90 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc.

[0091] Step S152: Etch the surface of the protective layer away from the bonding layer to form a bonding area protective layer and a via area protective layer.

[0092] Specifically, after obtaining the semiconductor structure as Figure 8 shown, the surface of the protective layer 420 away from the bonding layer 410 can be patterned etched to obtain the bonding area protective layer 421 and the via area protective layer 422 as Figure 9 shown.

[0093] In this embodiment, the bonding area protective layer 421 is used to protect the bonding interface from damage during subsequent process processing; the via area protective layer 422 is used to prevent over-etching onto the first conductive layer during via etching, causing damage to the first conductive layer and contamination of the etching machine.

[0094] Step S153: Form a third cladding layer on the surface of the bonding area protective layer and the via area protective layer away from the bonding layer.

[0095] Specifically, after obtaining the semiconductor structure as Figure 9 shown, a third cladding layer 530 as Figure 10 shown can be deposited by PECVD on the surfaces of the bonding area protective layer 421, the via area protective layer 422, and the bonding layer 410 away from the first cladding layer 120.

[0096] Among them, the thickness of the third cladding layer 530 can be 100 nm to 800 nm. For example, the thickness of the third cladding layer 530 can be 100 nm, 200 nm, 400 nm, 600 nm, 800 nm, etc. The material of the third cladding layer 530 can be silicon dioxide (SiO2).

[0097] Step S154: Etch the third cladding layer, the via area protective layer, and the bonding layer to form a via.

[0098] Among them, the through hole exposes the first conductive layer.

[0099] Specifically, the above step S154 includes steps S1541 to S1543:

[0100] Step S1541: Etch the third cladding layer by dry etching until the protective layer in the through hole area is exposed.

[0101] Specifically, etch the third cladding layer 530 by dry etching and stop at the protective layer 422 in the through hole area to form the first dielectric through hole 531 as shown in Figure 10 the figure.

[0102] Furthermore, in order to ensure that there is no residue in the etching of the third cladding layer 530 in the area where the through hole is located, a certain amount of over-etching can be performed on the protective layer 422 in the through hole area. The thickness of the third cladding layer 530 needs to be adjusted according to the size of the modulator chip. Using the protective layer 422 in the through hole area as the stop layer for dry etching, there is no need to adjust the etching parameters of dry etching according to the size of the modulator chip additionally.

[0103] Step S1542: Etch the protective layer in the through hole area by wet etching to expose the bonding layer.

[0104] Among them, the solution used for wet etching can be hydrochloric acid (HCl) solution, phosphoric acid (H3PO4) solution or other wet etching solutions for metals.

[0105] Specifically, after obtaining the semiconductor structure as shown in Figure 11 the figure, the protective layer 422 in the through hole area under the first dielectric through hole 531 can be removed by wet etching to form the second dielectric through hole 532 as shown in Figure 12 the figure.

[0106] In this embodiment, removing the protective layer 422 in the through hole area at a specific position by wet etching will not affect the material of the bonding layer 410, and the protective layer 422 in the through hole area can be removed without affecting the bonding layer 410.

[0107] Step S1543: Etch the bonding layer by dry etching until the first conductive layer is exposed to form a through hole.

[0108] Specifically, after obtaining the semiconductor structure as shown in Figure 12 the figure, the bonding layer under the second dielectric through hole 532 can be removed by dry etching until the first conductive layer is exposed, and then the through hole 533 as shown in Figure 13 the figure is obtained.

[0109] Step S155: Form an interconnection structure in the through hole.

[0110] Specifically, forming an interconnect structure within the through-hole includes: depositing a third conductive material 540 on a surface of the third cladding layer away from the first conductive layer to obtain a semiconductor structure as shown in Figure 14 ; performing a polishing process on the third conductive material 540 to obtain an interconnect structure 510 as shown in Figure 15 .

[0111] Among them, the third conductive material 540 can be metallic copper (Cu).

[0112] Exemplarily, a PECVD method can be used to deposit the third conductive material 540 on a surface of the third cladding layer away from the first conductive layer, and the third conductive material 540 covers the through-hole 533 and the third cladding layer 530. A CMP method can be used to perform a polishing process on the third conductive material 540, and the stop position of the polishing process is a surface of the third cladding layer 530 facing away from the first conductive layer.

[0113] Step S156, forming a second conductive material on a surface of the third cladding layer away from the bonding layer.

[0114] Specifically, after obtaining the semiconductor structure as shown in Figure 15 , a second conductive material can be electroplated on a surface of the third cladding layer away from the bonding layer. Among them, the second conductive material covers the third cladding layer and the interconnect structure 510.

[0115] Step S157, performing an etching process on the second conductive material to form a plurality of second conductive layers arranged at intervals.

[0116] Specifically, after forming the second conductive material, a patterning etch can be performed on the second conductive material to form a plurality of second conductive layers 520 arranged at intervals as shown in Figure 16 . Among them, the arrangement pattern formed by the plurality of second conductive layers 520 arranged at intervals can be set by a designer according to requirements.

[0117] Specifically, after setting the protective layer, before bonding the modulator chip to a surface of the bonding layer away from the first cladding layer, the method for manufacturing a compound optical waveguide modulator further includes steps S17 to S20:

[0118] Step S17, forming a fourth cladding layer on a surface of the second conductive layer away from the third cladding layer.

[0119] Specifically, a PECVD method can be used to deposit and form a fourth cladding layer 620 as shown in Figure 17 on a surface of the second conductive layer 520 away from the third cladding layer. The fourth cladding layer 620 covers the third cladding layer 530 and the second conductive layer 520, and the material of the fourth cladding layer 620 can be silicon dioxide (SiO2).

[0120] Step S18: Etch the fourth cladding layer and the third cladding layer by dry etching until the bonding area protection layer is exposed.

[0121] Step S19: Etch the bonding area protection layer by wet etching to form an opening.

[0122] Wherein, the opening exposes the bonding layer.

[0123] Specifically, the fourth cladding layer and the third cladding layer are etched by dry etching until the bonding area protection layer 421 as shown is exposed. The stop position of the etching process is the surface of the bonding area protection layer 421 away from the first cladding layer 120, and the width of the etching process is less than the width of the bonding area protection layer 421. Figure 18 After obtaining the semiconductor structure as shown, the bonding area protection layer 421 is etched by wet etching to form an opening as shown. The solution for wet etching can be hydrochloric acid (HCl) solution, phosphoric acid (H3PO4) solution or other wet etching solutions for metals.

[0124] In this embodiment, removing the bonding area protection layer 421 by wet etching will not affect the bonding layer 410, thereby ensuring the flatness of the bonding interface. Figure 18 After obtaining the semiconductor structure as shown, the bonding area protection layer 421 is etched by wet etching to form an opening as shown. The solution for wet etching can be hydrochloric acid (HCl) solution, phosphoric acid (H3PO4) solution or other wet etching solutions for metals. Figure 19 In this embodiment, removing the bonding area protection layer 421 by wet etching will not affect the bonding layer 410, thereby ensuring the flatness of the bonding interface.

[0125] In this embodiment, removing the bonding area protection layer 421 by wet etching will not affect the bonding layer 410, thereby ensuring the flatness of the bonding interface.

[0126] Step S20: Etch the surface of the fourth cladding layer away from the third cladding layer to form a pad window.

[0127] Wherein, the pad window exposes the second conductive layer.

[0128] Specifically, after obtaining the semiconductor structure as shown, the surface of the fourth cladding layer away from the third cladding layer can be etched by dry etching to form a pad window 630 as shown. The stop position of the dry etching is the surface of the second conductive layer 520 away from the first conductive layer. Figure 19 After obtaining the semiconductor structure as shown, the surface of the fourth cladding layer away from the third cladding layer can be etched by dry etching to form a pad window 630 as shown. The stop position of the dry etching is the surface of the second conductive layer 520 away from the first conductive layer. Figure 20 In some embodiments, the above step S16 may include step S161 and step S162:

[0129] In some embodiments, the above step S16 may include step S161 and step S162:

[0130] Step S161: Perform a pre-bonding process on the modulator chip and the surface of the bonding layer away from the first cladding layer.

[0131] Step S162: After the pre-bonding process, perform a thermocompression bonding process on the modulator chip and the surface of the bonding layer away from the first cladding layer to obtain a composite optical waveguide modulator.

[0132] Specifically, after obtaining the semiconductor structure as shown in Figure 20 , the modulator chip 610 can be placed at a preset position of the bonding interface for pre-bonding treatment and thermocompression bonding treatment to obtain a composite optical waveguide modulator as shown in Figure 21 .

[0133] Among them, the process parameters of the pre-bonding treatment include: the first bonding pressure is 0, the value range of the first bonding temperature is from 20°C to 300°C. For example, the first bonding temperature can be 20°C, 90°C, 160°C, 230°C or 300°C, etc.; the value range of the first bonding time is from 1 h to 12 h. For example, the first bonding time can be 1 h, 3 h, 6 h, 9 h or 12 h, etc.

[0134] The process parameters of the thermocompression bonding treatment include: the second bonding pressure is less than or equal to 2000 N. For example, the second bonding pressure can be 500 N, 1000 N, 1500 N or 2000 N, etc.; the value range of the second bonding temperature is from 100°C to 300°C. For example, the second bonding temperature can be 100°C, 150°C, 200°C, 250°C or 300°C, etc.; the value range of the second bonding time is from 1 h to 12 h. For example, the second bonding time can be 1 h, 3 h, 6 h, 9 h or 12 h, etc.

[0135] Under the action of a high bonding temperature of 100°C to 300°C, the modulator chip 610 and the bonding interface form strong chemical bonds through reactions such as dehydration condensation, and the bonding energy can reach 1 - 2 J / m².

[0136] In this embodiment, first, the pre-bonding treatment is performed on the surface of the modulator chip and the bonding layer away from the first cladding, and then the thermocompression bonding treatment is performed on the surface of the modulator chip and the bonding layer away from the first cladding. The bonding position of the modulator chip can be adjusted in the pre-bonding treatment stage to improve the bonding accuracy. Moreover, the pre-bonding can activate the bonding energy of the surface of the modulator chip and the bonding layer away from the first cladding, laying a foundation for the subsequent thermocompression bonding.

[0137] Furthermore, before the pre-bonding treatment, the modulator chip 610 is also cleaned to remove organic substances and particles on the surface.

[0138] Among them, the cleaning method can be plasma treatment, such as cleaning through O2 plasma, or it can be wet cleaning, such as RCA standard cleaning.

[0139] The present invention also provides a composite optical waveguide modulator, and this composite optical waveguide modulator can be prepared by the preparation method of the composite optical waveguide modulator provided in any of the above embodiments.

[0140] In some embodiments, the composite optical waveguide modulator can be applied to fields such as optical interconnection in data centers, long-haul fiber optic communication, silicon photonic integrated circuits, optical quantum computing, phased array radars, on-chip biosensors, optical coherence tomography, lidar, satellite optical communication, or neuromorphic photonic computing.

[0141] In the description of this specification, the descriptions with reference to terms such as "this embodiment", "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0142] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0143] In the above description, technical details such as the layout and etching of each layer are not elaborated in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, for forming the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0144] The above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the above specific embodiments, and various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention.

[0145] Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, more other equivalent embodiments can be included.

Claims

1. A preparation method of a composite optical waveguide modulator, characterized in that The method includes: Providing a waveguide wafer, wherein the waveguide wafer includes a substrate layer, a first cladding layer, and a plurality of waveguide structures. The first cladding layer is located on one side surface of the substrate layer, and the plurality of waveguide structures are arranged at intervals in the first cladding layer; Etching the side surface of the first cladding layer away from the substrate layer to form grooves on both sides of the waveguide structure; Forming a first conductive layer in the grooves; Forming a second cladding layer on the side surface of the first conductive layer away from the first cladding layer, wherein the thickness of the second cladding layer is greater than the target thickness required for the bonding layer; Polishing the second cladding layer to form the bonding layer; Forming a plurality of second conductive layers arranged at intervals on the side surface of the bonding layer away from the first cladding layer, wherein the first conductive layer and the second conductive layer are electrically connected; Bonding a modulator chip to the side surface of the bonding layer away from the first cladding layer to obtain a composite optical waveguide modulator.

2. The method according to claim 1, characterized in that, The polishing the second cladding layer to form the bonding layer includes: Polishing the second cladding layer by chemical mechanical planarization to form the bonding layer.

3. The method according to claim 1, characterized in that, The thickness of the bonding layer ranges from 90 nm to 110 nm.

4. The method according to claim 1, wherein Forming a first conductive layer in the grooves includes: Electroplating a first conductive material in the grooves and on the side surface of the first cladding layer away from the substrate layer, wherein the first conductive material covers the grooves and the first cladding layer; Polishing the first conductive material by chemical mechanical planarization until the plurality of waveguide structures are exposed to form the first conductive layer.

5. The method according to any one of claims 1 to 4, characterized in that Forming a plurality of second conductive layers arranged at intervals on the side surface of the bonding layer away from the first cladding layer includes: Forming a protective layer on the side surface of the bonding layer away from the first cladding layer; Etching the side surface of the protective layer away from the bonding layer to form a bonding area protective layer and a via area protective layer; Forming a third cladding layer on the side surfaces of the bonding area protective layer and the via area protective layer away from the bonding layer; Etching the third cladding layer, the via area protective layer, and the bonding layer to form vias, wherein the vias expose the first conductive layer; Forming an interconnect structure in the vias; Forming a second conductive material on the side surface of the third cladding layer away from the bonding layer; Etching the second conductive material to form a plurality of second conductive layers arranged at intervals.

6. The method according to claim 5, wherein The etching the third cladding layer, the via area protective layer, and the bonding layer to form vias includes: Etching the third cladding layer by dry etching until the via area protective layer is exposed; Etching the via area protective layer by wet etching to expose the bonding layer; Etching the bonding layer by dry etching until the first conductive layer is exposed to form the vias.

7. The method according to claim 5, characterized in that, Before the bonding the modulator chip to the side surface of the bonding layer away from the first cladding layer, the method further includes: A fourth cladding layer is formed on a surface of the second conductive layer away from the third cladding layer; Etching treatment is performed on a surface of the fourth cladding layer away from the third cladding layer to form a pad window, wherein the pad window exposes the second conductive layer.

8. The method according to claim 7, characterized in that, After a fourth cladding layer is formed on a surface of the second conductive layer away from the third cladding layer, the method further includes: Performing etching treatment on the fourth cladding layer and the third cladding layer by a dry etching method until the bonding area protective layer is exposed; Performing etching treatment on the bonding area protective layer by a wet etching method to form an opening, wherein the opening exposes the bonding layer.

9. The method according to claim 5, wherein The thickness of the protective layer ranges from 90 nm to 200 nm.

10. The method according to any one of claims 1 to 4, characterized in that, The bonding treatment of the modulator chip and a surface of the bonding layer away from the first cladding layer includes: Performing pre-bonding treatment on the modulator chip and a surface of the bonding layer away from the first cladding layer; After the pre-bonding treatment, performing thermocompression bonding treatment on the modulator chip and a surface of the bonding layer away from the first cladding layer to obtain a compound optical waveguide modulator.

11. The method according to claim 10, wherein The process parameters of the pre-bonding treatment include: the first bonding pressure is 0, the first bonding temperature ranges from 20 °C to 300 °C, and the first bonding time ranges from 1 h to 12 h; The process parameters of the thermocompression bonding treatment include: the second bonding pressure is less than or equal to 2000 N, the second bonding temperature ranges from 100 °C to 300 °C, and the second bonding time ranges from 1 h to 12 h.

12. A compound optical waveguide modulator, characterized in that, The compound optical waveguide modulator is prepared by the preparation method of the compound optical waveguide modulator according to any one of claims 1 to 11.

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