Row activation scheduling method in DDR (Double Data Rate) controller, DDR controller and system on chip

Abstract

The invention relates to the field of memory management, and discloses a row activation scheduling method in a DDR (Double Data Rate) controller, the DDR controller and an on-chip system.The method comprises the steps that when it is judged that a row conflict command exists in all commands stored in a command queue through an intelligent row closing module, the row conflict command is activated; determining one or more target commands containing row conflict commands in the commands, and adding automatic pre-charging identifiers for the target commands; for any target command, acquiring currently activated target row information from the bank management module through an intelligent row closing module, if the target command is matched with the target row information and other commands matched with the target row information exist in the command queue, clearing an automatic pre-charging identifier in the target command, and if the other commands matched with the target row information exist in the command queue, clearing the automatic pre-charging identifier in the target command; and sending the target command of which the automatic pre-charging identifier is cleared through a physical layer interface connected with the DDR controller. According to the technical scheme provided by one or more embodiments, the processing efficiency of the access command can be improved.

Description

Technical Field

[0001] This application relates to the technical field of memory management, and in particular to a row activation scheduling method in a DDR controller, a DDR controller, and a system on chip. Background Art

[0002] In DDR memory technology, after performing an access operation on a certain bank of a memory, if it is necessary to address and access another row of the same bank again, the bank management module needs to send a precharge command to the memory through the bus.

[0003] In practical applications, the bank management module needs to obtain the control right of the bus to send a precharge command through the bus. Moreover, due to the small bus bandwidth, after the precharge operation is completed, it is necessary to wait until the control right of the bus is released before executing the access command. Obtaining / releasing the control right of the bus each requires one cycle, resulting in a long waiting time for the access command and low memory access efficiency.

[0004] In view of this, how to improve the processing efficiency of access commands has become an urgent problem to be solved in the field of memory management. Summary of the Invention

[0005] This application provides a row activation scheduling method in a DDR controller, a DDR controller, and a system on chip, which can improve the processing efficiency of access commands.

[0006] A first aspect of this application provides a row activation scheduling method in a DDR controller. The method is applied to a DDR controller, and the DDR controller includes an intelligent row closing module, a bank management module, and a command queue. The method includes: when the intelligent row closing module determines that there are row conflict commands among the commands stored in the command queue, determining one or more target commands including the row conflict commands among the commands, and adding an automatic precharge flag to the target commands; for any one of the target commands, obtaining the current activated target row information from the bank management module through the intelligent row closing module. If the target command matches the target row information, and there are other commands in the command queue that match the target row information, clearing the automatic precharge flag in the target command, and sending the target command with the cleared automatic precharge flag through the physical layer interface connected to the DDR controller.

[0007] The technical solution provided by this embodiment of the present application dynamically adjusts the automatic precharge flag of a command through an intelligent row control module to improve the processing efficiency of the command. Among them, the intelligent row control module obtains row conflict information from the command queue, determines a target command according to the row conflict information, and adjusts the automatic precharge flag bit of the target command, so that each command matching the currently activated target row can complete the processing of these commands with only one precharge operation, avoiding multiple precharge operations and reducing the command processing time when row conflicts occur. It can be seen that through the technical solution provided by this embodiment of the present application, the command processing time can be reduced and the command processing efficiency can be improved.

[0008] In a possible implementation manner, when the intelligent row control module determines whether there are row conflict commands among the commands stored in the command queue, it includes: the intelligent row control module obtains the address information of each command in the command queue, and determines whether there are a first address and a second address in the address information that point to different rows of the same bank. If so, it is determined that there are row conflict commands in the command queue.

[0009] The technical solution provided by this embodiment of the present application clarifies the determination method of row conflict situations. The intelligent row control module determines the address information of adjacent commands, and determines whether there are row conflict commands in the command queue according to the row addresses pointed to by the address information.

[0010] In a possible implementation manner, the row conflict commands are determined as follows: the intelligent row control module identifies the execution order of each command in the command queue, and sequentially determines whether there is a row conflict between two adjacent commands according to the execution order; for any adjacent first command and second command, if there is a row conflict between the first command and the second command, and the first command is executed before the second command, the first command is determined as the row conflict command.

[0011] The technical solution provided by this embodiment of the present application clarifies the determination method of row conflict commands. When the intelligent row control module determines that there are row conflict commands among adjacent commands in the command queue, the command with the earlier execution order among the adjacent commands is determined as the row conflict command.

[0012] In a possible implementation manner, determining one or more target commands including the row conflict commands among the commands includes: determining all commands in the command queue as target commands; or only determining the row conflict commands in the command queue as target commands.

[0013] The technical solution provided by this embodiment of the present application clarifies the determination method of the target command. All commands can be used as the target command, or the row conflict command can be used as the target command to dynamically add or clear the automatic precharge flag of the target command.

[0014] In a possible implementation manner, if the currently to-be-processed target command does not match the target row information, or there is no other command in the command queue that matches the target row information, the currently to-be-processed target command carrying the automatic precharge flag is sent out through the physical layer interface.

[0015] The technical solution provided by this embodiment of the present application elaborates on the situation where the target command needs to be precharged. When the target command whose automatic precharge flag has not been cleared is about to be executed, the bank management module will send the target command carrying the automatic precharge flag to the physical layer for precharge operation to ensure the correctness of command execution.

[0016] In a possible implementation manner, the intelligent row closing module obtains the currently activated target row information from the bank management module, including: the intelligent row closing module obtains the address information of the target command and identifies the target bank pointed to by the address information; the intelligent row closing module queries the target page entry where the target bank is located in multiple page entries of the bank management module and obtains the currently activated target row information stored in the target page entry.

[0017] The technical solution provided by this embodiment of the present application details the acquisition method of the currently activated target row information. By querying multiple page entries stored in the bank management module by the intelligent row closing module according to the address information, the currently activated target row information of the target bank can be quickly located and obtained to improve the processing efficiency of access commands.

[0018] In a possible implementation manner, the matching relationship between the target command and the target row information, and the matching relationship between the other commands in the command queue and the target row information are represented as follows: the bank and row pointed to by the address information of the target command correspond exactly to the bank and row characterized by the target row information, and the bank and row pointed to by the address information of the other commands in the command queue also correspond exactly to the bank and row characterized by the target row information.

[0019] The technical solution provided by this embodiment of the present application defines the matching relationship between the commands in the command queue and the target row information. When the bank and row pointed to by the address information of the current command are the same, it is determined that the current command matches the target row information, so as to clear the automatic precharge flag of the current command and improve the processing efficiency of the commands in the command queue.

[0020] In a possible implementation manner, whenever a new command is written into the command queue, the intelligent row closing module determines whether there are row conflict commands among the commands currently stored in the command queue, and determines whether to add an automatic precharge flag to the commands in the command queue according to the determination result.

[0021] The technical solution provided by this embodiment of the present application describes the processing method of new commands in the command queue. When a new command enters the command queue, it will trigger the judgment process of row conflict, so as to realize the dynamic management of the automatic precharge flag.

[0022] The second aspect of the present application provides a DDR controller, which includes an intelligent row closing module, a bank management module, and a command queue, wherein: the bank management module is used to provide the intelligent row closing module with the target row information of the currently activated bank; the command queue is used to store each command to be executed; the intelligent row closing module is used to determine one or more target commands including the row conflict command among the commands stored in the command queue when it is determined that there are row conflict commands in the commands stored in the command queue, and add an automatic precharge flag to the target commands; for any target command to be processed currently, obtain the target row information of the currently activated bank from the bank management module. If the target command matches the target row information, and there are other commands in the command queue that also match the target row information, clear the automatic precharge flag in the target command, and send the target command with the automatic precharge flag cleared through the physical layer interface connected to the DDR controller.

[0023] The third aspect of the present application provides a system-on-chip, which includes a processor core, a network-on-chip, a DDR controller, and a physical layer interface, wherein: the processor core is used to send data read / write commands to the DDR controller through the network-on-chip; the DDR controller is used to execute the above-mentioned row activation scheduling method for the received data read / write commands; the physical layer interface is used to perform protocol conversion on the commands output by the DDR controller and send out the commands after protocol conversion. Description of the Drawings

[0024] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 It is a step diagram of a row activation scheduling method in a DDR controller provided by an embodiment of the present application;

[0026] Figure 2 It is a command schematic diagram for determining row conflict commands in a command queue provided by an embodiment of the present application;

[0027] Figure 3 It is a step schematic diagram for performing row activation scheduling in a DDR controller provided by an embodiment of the present application;

[0028] Figure 4 It is a structural schematic diagram for performing row activation scheduling in a DDR controller provided by an embodiment of the present application;

[0029] Figure 5(a) and 5(b) It is a node schematic diagram of the command execution process when a row conflict occurs provided by an embodiment of the present application;

[0030] Figure 6 It is a structural schematic diagram of a DDR controller provided by an embodiment of the present application;

[0031] Figure 7 It is a structural schematic diagram of a system-on-chip provided by an embodiment of the present application. Specific Embodiments

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0033] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the embodiments of this application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, the use of "based on" or "according to" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" or "according to" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0034] In a DDR memory system, when an access operation such as data read / write to the memory is required, the processor core sends an access command to the DDR controller. The bank management module of the DDR controller schedules the access command and transmits the access command through the bus to the physical layer interface to access the corresponding storage unit. During this process, since memory addressing is exclusive, after a data read / write operation, if it is necessary to perform a data read / write operation on different rows of the same bank again, the bank management module needs to perform a precharge operation on the current bank. The above precharge operation can be understood as closing the original active row to prepare for opening a new row.

[0035] During the above process, when the bank management module performs a precharge operation on the memory through the physical layer interface, it needs to occupy the control right of the bus connecting the physical layer interface. Obtaining and releasing the bus each requires one cycle, and the waiting time of the data read / write instruction is relatively long, resulting in a certain access delay and low memory access efficiency. In related technologies, the precharge operation can be controlled by commands or set to perform automatic precharge after each read / write operation.

[0036] This application provides a scenario example of controlling the precharge operation by sending commands. By keeping the page in the bank always open, when the configured count value is reached, the bank management module of the DDR controller regularly requests the bus control right to send a precharge command to the memory.

[0037] Exemplarily, command A and command B are executed in sequence. There is a row conflict situation between command A and command B. After the data read / write operation of command A, an additional instruction cycle needs to be waited to obtain the bus control right, and a precharge operation is performed on the target bank. After the tRP (RAS Precharge Time) timing, an activate command is sent to the row pointed to by command B, and after the tRCD (RAS to CAS Delay) timing, the data read / write operation of command B is executed. In the case of frequent row conflicts, since the bank management module needs to occupy the bus control right to send the precharge command, the waiting delay time of command B is relatively long, and the processing efficiency of memory access is relatively low.

[0038] The above are only one or more scenario examples provided in the specification, and are not intended to limit the present invention. Any modifications, equivalent replacements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0039] In view of this, one or more embodiments of the present application provide a row activation scheduling method in a DDR controller, a DDR controller, and a system on chip, which can solve the above problems and improve the processing efficiency of access commands.

[0040] Please refer to Figure 1 , one embodiment of the present application provides a row activation scheduling method in a DDR controller. The method is applied to a DDR controller, and the DDR controller includes an intelligent row closing module, a bank management module, and a command queue. The method may include the following steps:

[0041] S1: Determine whether there are row conflict commands among the commands stored in the command queue through the intelligent row closing module. If so, execute steps S11 and S3; if not, execute steps S13 and S3.

[0042] S11: In the case of determining that there are row conflict commands among the commands stored in the command queue, determine one or more target commands including the row conflict commands among the commands, and add an automatic precharge flag to the target commands.

[0043] S13: In the case of determining that there are no row conflict commands among the commands stored in the command queue, determine the commands as target commands, and add an automatic precharge flag to the target commands.

[0044] In this embodiment, the identification bit of the target command is adjusted according to the intelligent bank operation module to selectively add an auto-precharge identification to one or more commands in the command queue. Specifically, the intelligent bank operation module selectively determines one or more access commands in the command queue as target commands, and only adds an auto-precharge identification to the target commands, so as to selectively perform a precharge operation on each access command. For other commands in the command queue except the target commands, no precharge operation is performed, thereby reducing the delay time of some commands and improving the processing efficiency of the access commands.

[0045] In this embodiment, an auto-precharge identification can be added to the target command by assigning a value to the identification bit. Specifically, the identification bit of the target command is set to a first value, indicating that an auto-precharge identification is added to the target command. At this time, an auto-precharge operation needs to be performed on the target command. The identification bit of the target command is set to a second value, indicating that the identification bit of the target command is cleared. At this time, no auto-precharge operation needs to be performed on the target command. Exemplarily, the first value can be 1 and the second value can be 0. It should be noted that the above examples are only examples and should not constitute a limitation.

[0046] In one embodiment, an auto-precharge identification can also be added to the target command by expanding the identification bit. Specifically, the identification bit of the target command is expanded from 2 bits to 3 bits. For example, the 2-bit identification bit '00' of the command is expanded to the 3-bit identification bit '100'. When the identification bit of the target command is '100', it indicates that a precharge operation needs to be performed. By increasing the length of the identification bit, additional coding space is provided for the identification of the auto-precharge, while maintaining compatibility with the original command identification.

[0047] S3: For any one of the target commands, the intelligent bank operation module obtains the currently activated target row information from the bank management module. If the target command matches the target row information and there are other commands in the command queue that also match the target row information, the auto-precharge identification in the target command is cleared, and the target command with the cleared auto-precharge identification is sent through the physical layer interface connected to the DDR controller.

[0048] The above target row information can be understood as the currently activated row address information in the bank pointed to by the target command, and the above target row information is stored in the bank management module. Specifically, if the above target command satisfies the matching relationship with the target row information, and other commands in the command queue also satisfy the matching relationship with the target row information, then the auto-precharge flag of the current target command is cleared. Further, the target command after the adjustment of the auto-precharge flag is sent through the physical layer interface. The above physical layer interface will convert the above target command into a signal that conforms to the input specification of the memory, and send the above converted target command to the memory through the bus to access the corresponding storage unit.

[0049] In this embodiment, for a target command with an added auto-precharge flag, when any target command is executed, the auto-precharge flag of the target command can be dynamically cleared. By readjusting the auto-precharge flag of the target command, the correct execution of the auto-precharge operation of each target command can be ensured. Even if a new command enters the command queue, the auto-precharge flag of the current target command can be adjusted according to the real-time status of the command queue, further reducing the number of executions of the precharge operation, thereby improving the processing efficiency of the access command.

[0050] In a possible embodiment, when any target command is executed, the flag bit of the above target command is cleared. Specifically, if the above target command matches the target row information, and there are other commands in the command queue that match the target row information, then there is no need to perform a precharge operation. The auto-precharge flag of the above target command is directly cleared, and the above target command is executed and sent to the memory through the physical layer interface. At the same time, other commands that match the target row information are scheduled after the above target command to reduce the occurrence of row conflicts, reduce the number of executions of the precharge operation, and avoid the access delay of other commands that match the target row information, thereby improving the processing efficiency of the access command.

[0051] In another possible embodiment, when any target command is executed, the flag bit of the above target command is retained. Specifically, if the above target command does not match the target row information, or there are no other commands in the command queue that match the target row information, then the auto-precharge flag of the above target command is retained, and the above target command is sent through the physical layer interface. By the above method of retaining the auto-precharge flag, it is ensured that while reducing the waiting delay caused by precharging, the correct execution of each command is ensured.

[0052] In one embodiment, the above-mentioned target row information can be determined by calling the bank management module. Specifically, the intelligent bank closing module obtains the address information of the above-mentioned target command and identifies the target bank pointed to by the address information. Further, the intelligent bank closing module queries the target page entry where the target bank is located among multiple page entries of the bank management module, and obtains the currently activated target row information stored in the target page entry.

[0053] In this embodiment, the bank management module stores the row activation information of different banks according to different entries. Exemplarily, taking DDR4 as an example, there are multiple bank groups in a DDR4 chip, and each bank group contains multiple banks. For each bank in DDR4, the bank management module has a corresponding page entry. After identifying the bank pointed to by the address information of the target command, the stored information in the corresponding page entry can be located through the bank management module. The above-mentioned stored information represents the address information of the currently activated row in the corresponding bank, that is, the target row information.

[0054] In one embodiment, by respectively judging the matching relationship between the target command, other commands in the command queue and the target row information, it is determined whether to clear the automatic precharge flag of the above-mentioned target command. The above-mentioned matching relationship can be represented in the following way:

[0055] If the bank and row pointed to by the address information of the target command are both correspondingly consistent with the bank and row represented by the target row information, it is determined that the above-mentioned target command matches the target row information. And if the bank and row pointed to by the address information of other commands in the command queue are also correspondingly consistent with the bank and row represented by the target row information, it is determined that the above-mentioned other commands match the target row information.

[0056] Further, when both the current target command and other commands in the command queue match the target row information, there is no need to perform a precharge operation at this time. The automatic precharge flag of the current target command can be cleared to reduce the waiting time for unnecessary precharging during command execution, thereby improving the processing efficiency of access commands.

[0057] Conversely, if the bank pointed to by the address information of the current target command is the same as the bank represented by the target row information, but the row pointed to by the address information of the current target command is different from the row represented by the target row information, it is determined that the above target command does not match the target row information. At this time, a precharge operation is required, and the automatic precharge flag of the above target command should be retained. If the bank pointed to by the address information of other commands in the command queue is the same as the bank represented by the target row information, but the rows pointed to by the address information of the above other commands are all different from the row represented by the target row information, it is determined that the other commands in the command queue do not match the target row information. At this time, a precharge operation is required, and the automatic precharge flag of the above target command should be retained.

[0058] It should be noted that if the banks pointed to by the address information of other commands in the command queue are all different from the current target command to be processed, the automatic precharge flag of the current target command to be processed can also be cleared at this time.

[0059] In one embodiment, the intelligent bank closing module can determine whether there are row conflict commands among the commands stored in the command queue in the following manner. Specifically, the intelligent bank closing module obtains the address information of each command in the command queue and determines whether there are a first address and a second address in the address information that point to the same bank but different rows. If so, it is determined that there are row conflict commands in the command queue.

[0060] In this embodiment, the above address information can be understood as the location information of the memory that the command is about to access, usually pointing to a row address in a certain bank of the DDR. If there are two or more address information among the address information of each command that point to different rows in the same bank, it is determined that there are row conflict commands in the command queue. It should be noted that if the address information of each command in the command queue points to the same row in the same bank, or the address information of each command in the command queue points to different banks, it is determined that there are no row conflict commands in the command queue.

[0061] In one embodiment, the intelligent bank closing module can determine the row conflict commands stored in the command queue in the following manner. Specifically, the intelligent bank closing module identifies the execution order of each command in the command queue and sequentially determines whether there are row conflicts between two adjacent commands according to the above execution order. Further, for any adjacent first command and second command, if the first command and the second command have a row conflict and the first command is executed before the second command, the first command is determined as the row conflict command.

[0062] In this embodiment, the above execution order is the order of commands after reordering each command in the command queue according to the address information. Specifically, when it is determined that there is a row conflict command in the command queue, the address information of each command is obtained, and the commands with the address information of the same row in the same bank are arranged in sequence. Exemplarily, if the address information of a certain command in the command queue is the same as that of another command arranged later, then the above another command is used as the next command of the current command. It should be noted that when a new command enters the command queue, the address information of the current new command is also obtained and matched with the address information of other commands in the command queue. If there is the same address information, the new command is used as the next command of the last command with the same address information. By adjusting the arrangement order of each command through the intelligent row closing module, it is ensured that the commands with the same address information in the command queue can be preferentially processed, so as to reduce the number of row conflict commands, thereby reducing the number of precharges, avoiding unnecessary access delays, and further improving the processing efficiency of access commands.

[0063] In this embodiment, if there is a row conflict situation among adjacent commands in the above execution order, the command with the earlier execution order is used as the row conflict command. The reason for this processing is that in some embodiments, it is necessary to add an automatic precharge flag for the row conflict command. Only by using the command with the earlier execution order as the row conflict command can the normal automatic precharge logic be completed. Specifically, assume that the adjacent commands are the first command and the second command, and there is a row conflict situation between these two commands. When the first command with the earlier execution order is used as the row conflict command, since the first command carries the automatic precharge flag, after the first command is executed, the page can be precharged, and the subsequent row closing and row activation processes can be realized, ensuring that the second command can be normally processed. If the second command with the later execution order is used as the row conflict command, then after the first command is executed, since the first command does not carry the automatic precharge flag, the automatic precharge process cannot be normally triggered, which will cause the second command to not be normally executed. Moreover, even if the second command is executed, since the second command carries the automatic precharge flag, at this time, additional row closing and row activation behaviors will occur. However, in fact, the commands after the second command do not necessarily have a row conflict relationship with the second command. The additional row closing and row activation behaviors are not necessary steps, which will cause waste of resources.

[0064] Specifically, according to the above execution order, the address information of adjacent commands in the command queue is compared in sequence. If there are adjacent first and second commands that point to different rows of the same bank, the first command with a higher arrangement position is taken as the row conflict command, and an automatic precharge flag is added to the first command. When subsequent commands are executed, since the first command carries the automatic precharge flag, after the first command completes access operations such as data read / write, the page can be directly precharged to ensure the normal execution of the second command.

[0065] Exemplarily, please refer to Figure 2 , taking six commands such as command a in the command queue as an example. Among them, command a, command b, and command c all point to the first target row of the same bank, and command D, command E, and command F all point to the second target row of the same bank. First, the execution order of each command in the command queue is re-sorted according to the address information, and the commands with the same target row are arranged in sequence to reduce the number of row conflicts in the command queue. In the shown execution order, for adjacent commands c and D, the target rows pointed to by commands c and D are different, and it is determined that there is a row conflict between commands c and D. At this time, command c is determined as the row conflict command.

[0066] In an optional implementation manner, the row conflict command in the command queue is determined as the target command, and only the automatic precharge flag is added to the row conflict command. Further, when the command queue is executed according to the execution order, if the address information of the current target command to be processed points to different rows of the same bank as the target row information, or there is no other command in the command queue that matches the target row information, the automatic precharge flag of the current target command is retained, and the target command is sent to the physical layer to access the memory. When subsequent commands after the current target command are executed, since the previous command carried the automatic precharge flag, after the previous command completes access operations such as data read / write, the page can be directly precharged to ensure the normal execution of subsequent commands.

[0067] In this implementation manner, if a new command enters the command queue, it is necessary to re-judge whether the automatic precharge flags of each command need to be adjusted. Specifically, if there is a row conflict command in the command queue and the above row conflict command is taken as the target command, before the current target command is executed, it is necessary to judge whether the new command matches the current target row information through the intelligent row closing module. If it matches, the automatic precharge flag of the current target command is cleared, and the above new command is placed after the current target command to be processed, and an automatic precharge flag is added to the above new command. When the current target command is executed subsequently, since the automatic precharge flag is cleared, the above new command can directly perform data read / write operations on the page, thereby reducing the number of precharge operations and further improving the processing efficiency of access commands.

[0068] In an alternative embodiment, all commands in the command queue are determined as target commands, and an automatic precharge flag is added to all commands. Further, when executing the command queue in the execution order, if the address information of the currently pending target command and the target row information point to the same row in the same bank or to different banks, and there are other commands in the command queue with the same address information as the currently pending target command, then the automatic precharge flag of the currently pending target command is cleared. Subsequently, when executing other commands with the same address information, since the previous target command cleared the automatic precharge flag, the above-mentioned other commands can directly perform data read / write operations, thereby reducing the number of precharge operations and improving the processing efficiency of access commands.

[0069] In this embodiment, if the address information of the currently pending target command does not match the target row information, or there are no other commands in the command queue that match the target row information, then the automatic precharge flag of the current target command is retained, and the target command is sent to the physical layer to access the memory. Subsequently, when executing other commands after the current target command, since the previous command carried the automatic precharge flag, after the previous command completes access operations such as data read / write, the page can be directly precharged to ensure the normal execution of subsequent commands.

[0070] In this embodiment, if a new command enters the command queue, it is necessary to re-judge whether it is necessary to adjust the automatic precharge flags of each command. Specifically, if there are row conflict commands in the command queue and all commands in the command queue are used as target commands, then before executing the current target command, it is necessary to determine whether the address information of the new command matches the current target row information. If they match, the new command is inserted after the target command with the same address information and the automatic precharge flag retained, and the automatic precharge flag of the target command with the same address information and the automatic precharge flag is cleared, and an automatic precharge flag is added to the new command with the same address information. If they do not match, the target commands are sequentially popped from the command queue in the execution order and sent through the physical layer interface, and an automatic precharge flag is also added to the new command.

[0071] Based on the above idea, the intelligent bank closing module dynamically adjusts the precharge flag of the command to improve the command processing efficiency. Among them, the intelligent bank closing module obtains the row conflict information from the command queue, determines the target command according to the row conflict information, and adjusts the automatic precharge flag bit of the target command, so that each command matching the currently activated target row can complete the processing of these commands with only one precharge operation, avoiding multiple precharge operations, and reducing the command processing time when row conflicts occur. It can be seen that through the technical solution provided by this embodiment of the present application, the command processing time can be reduced and the command processing efficiency can be improved.

[0072] Please refer to Figure 3 and Figure 4 , the present application provides an embodiment of applying the row activation scheduling method in a DDR controller as described above. This embodiment is carried out according to the following steps:

[0073] Step 1: When the command queue receives a data read / write command, the intelligent bank closing module obtains the address information of each data read / write command, and determines whether there are row conflict commands in the command queue according to the above address information.

[0074] Step 2: Determine whether the first preset condition is satisfied. If the intelligent bank closing module detects that there are row conflict commands in the command queue, it is determined that the first preset condition is satisfied, and the AP bit of the corresponding row conflict command is set to the first value, indicating adding an automatic precharge flag to the row conflict command, and the AP bits of other data read / write instructions without row conflicts are set to the second value. If the intelligent bank closing module detects that there are no row conflict commands in the command queue, it is determined that the first preset condition is not satisfied, and the AP bits of all data read / write instructions are set to the first value. Among them, the above AP bit is the identification bit of the automatic precharge of the data read / write instruction. Exemplarily, the first value can be 1 and the second value can be 0. It should be noted that the above example is only an example and should not constitute a limitation.

[0075] Step 3: When the command queue executes each data read / write instruction, the intelligent bank closing module retrieves the page entry of the corresponding bank in the bank management module according to the bank address pointed to by the current data read / write instruction to obtain the information of the activated target row in the corresponding bank. Determine whether the current data read / write command satisfies the second preset condition. If the row address pointed to by the current data read / write instruction is the same as the target row information and there are no commands with different address information in the command queue, it is determined that the second preset condition is satisfied, and the identification bit of the current data read / write instruction is set to '0', indicating clearing the automatic precharge flag of the current data read / write command, and the data read / write instruction is sent to the physical layer interface. Further, it can be written to the memory through the bus.

[0076] In this embodiment, a data read / write command carrying an auto-precharge flag is connected to the physical layer interface through a bus and sent to the memory through the physical layer. After the data read / write operation of the current data read / write command carrying the auto-precharge flag is completed, a precharge operation is performed on the current bank. At the same time, the bank management module will send an activate command carrying the address information of the next data read / write command through the bus to activate the corresponding target row.

[0077] Please refer to FIGS. 5(a) and 5(b). FIG. 5(a) shows the command execution flow when a row conflict occurs in the related art, and FIG. 5(b) shows the command execution flow when a row conflict occurs in this embodiment. In this embodiment, the data read / write command is operated according to steps 1 to 3, and commands A and B are executed in sequence. There is a row conflict between commands A and B. By adding an auto-precharge flag to command A, a precharge operation is directly performed on the bank after the data read / write operation of command A is completed. After the tRP timing, the row address pointed to by command B is activated, and after the tRCD timing, command B is directly executed, without the need to release and acquire the DFI bus time. Compared with the traditional method, the delay time of command B is reduced.

[0078] In view of this, in one or more embodiments of the present application, by dynamically clearing or adding an auto-precharge flag to the target command in the command queue, the number of precharge operations performed by the command queue when executing commands can be reduced, and the delay time of each command waiting for the bus control right can be reduced, thereby greatly improving the processing efficiency of memory access.

[0079] Please refer to Figure 6 , the present application also provides a DDR controller, which includes an intelligent row closing module 301, a bank management module 302, and a command queue 303, where:

[0080] The bank management module 301 is used to provide the information of the currently activated target row to the intelligent row closing module;

[0081] The command queue 302 is used to store each command to be executed;

[0082] The intelligent bank closing module 303 is configured to, when it is determined that there are row conflict commands among the commands stored in the command queue memory, determine one or more target commands including the row conflict commands among the commands, and add an automatic precharge flag to the target commands; for any target command to be processed currently, obtain the target row information of the currently activated bank from the bank management module, if the target command matches the target row information, and there are other commands in the command queue that match the target row information, clear the automatic precharge flag in the target command, and send the target command with the cleared automatic precharge flag through the physical layer interface connected to the DDR controller.

[0083] Wherein,

[0084] The bank management module 301 is specifically configured to timely obtain the target row information of each currently activated bank in the memory, and provide the above target row information to the intelligent bank closing module. If there is a situation where all rows in any bank are not activated, obtain the row address information of the current data read / write command to the current bank to be processed in the command queue, and send an activation command to the current bank according to the row pointed to by the above row address information.

[0085] The command queue 302 is specifically configured to store one or more data read / write commands to be processed, adjust the execution order of each data read / write command, and pop the data read / write commands in the execution order.

[0086] The intelligent bank closing module 303 is specifically configured to dynamically add an automatic precharge flag to each data read / write command according to the row conflict situation in the command queue, obtain the target row information of each bank in the bank management module and the address information of each data read / write command in the command queue, and dynamically clear or add an automatic precharge flag to each data read / write instruction according to the above target row information and address information.

[0087] The further function descriptions of the above various modules and units are the same as those in the corresponding above embodiments, and will not be repeated here.

[0088] Please refer to Figure 7 , this application also provides a system-on-chip, the system-on-chip includes a processor core 10, a network-on-chip 20, a DDR controller 30, and a physical layer interface 40, wherein:

[0089] The processor core 10 is configured to send data read / write commands to the DDR controller through the network-on-chip;

[0090] The DDR controller 30 is configured to execute the above row activation scheduling method for the received data read / write commands;

[0091] The physical layer interface 40 is used to convert the protocol of the commands output by the DDR controller and issue the instructions after protocol conversion.

[0092] In one embodiment, the above physical layer interface may be selected as DFI (DDR PHY Interface, an industry standard interface). The physical layer interface is specifically used to receive the commands and data sent by the DDR controller, and directly send the commands and data to the memory device through the physical layer, and then read or write data.

[0093] In one embodiment, the above DDR controller is specifically used for, in response to the received data read / write command, when there is a row conflict command in the received data read / write command, dynamically adding or clearing the auto-precharge flag for the target command, and only automatically performing the precharge operation after the data read / write operation of the row conflict command is completed, reducing the number of precharge operations for the data read / write command, thereby reducing the waiting latency time of the data read / write command.

[0094] In one embodiment, the above processor core can be selected as: CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), TPU (Tensor Processing Unit), DPU (Deep learning Processing Unit), microprocessor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions executable by at least one processor, and the types of the at least one processor can be different, for example, including CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0095] The above external memory can be implemented by DDR memory chips, and the DDR memory chips are DDR SDRAM (Double Data Rate SDRAM, double data rate synchronous dynamic random access memory). The storage unit storage order is organized into a multi-level structure, which are channel, DIMM, rank, chip, Bank, row, and column in sequence. One channel corresponds to one DDR controller. Among them, each group of Ranks can be regarded as an independent external memory, with an independent address space and control logic, and can perform read and write operations independently. In the external memory, different external memory modules can be accessed by selecting different Ranks.

[0096] A DDR controller / on-chip device in an embodiment of the present application is presented in the form of a functional unit. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, or other devices that can provide the above functions.

[0097] The on-chip system illustrated in the above embodiment can be specifically implemented by a computer chip or an entity, or by a product with a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0098] Those skilled in the art should understand that the embodiments of the present application can be provided as methods and systems. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The present application is described with reference to the flowcharts and / or block diagrams of methods and systems according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementation in the process Figure 1one process or multiple processes and / or boxes Figure 1 means for the functions specified in one box or multiple boxes.

[0100] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, and the instruction device implements the processes Figure 1 one process or multiple processes and / or boxes Figure 1 the functions specified in one box or multiple boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or boxes Figure 1 one box or multiple boxes.

[0102] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity or device including the said element.

[0103] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the description of the method embodiment.

[0104] The above description is only for the embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0105] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A row activation scheduling method in a DDR controller, characterized in that The method is applied to a DDR controller, which includes an intelligent row closing module, a bank management module, and a command queue. The method includes: When the intelligent row closing module determines that there are row conflict commands among the commands stored in the command queue, one or more target commands including the row conflict commands are determined from the commands, and an automatic precharge flag is added to the target commands; For any one of the target commands, the intelligent row closing module obtains the currently activated target row information from the bank management module. If the target command matches the target row information and there are other commands in the command queue that also match the target row information, the automatic precharge flag in the target command is cleared, and the target command with the cleared automatic precharge flag is sent through the physical layer interface connected to the DDR controller.

2. The method according to claim 1, wherein, The intelligent row closing module determines whether there are row conflict commands among the commands stored in the command queue, including: The intelligent row closing module obtains the address information of each command in the command queue and determines whether there are a first address and a second address in the address information that point to different rows in the same bank. If so, it is determined that there are row conflict commands in the command queue.

3. The method according to claim 1 or 2, characterized in that, The row conflict commands are determined in the following manner: The intelligent row closing module identifies the execution order of each command in the command queue and sequentially determines whether there are row conflicts between adjacent two commands according to the execution order; For any adjacent first command and second command, if there is a row conflict between the first command and the second command and the first command is executed before the second command, the first command is determined as the row conflict command.

4. The method according to claim 1, wherein Determining one or more target commands including the row conflict commands from the commands includes: Determining all the commands in the command queue as target commands; Or Only determining the row conflict commands in the command queue as target commands.

5. The method according to claim 1, wherein The method further includes: If the target command does not match the target row information, or there are no other commands in the command queue that match the target row information, the target command carrying the automatic precharge flag is sent through the physical layer interface.

6. The method according to claim 1, characterized in that, The intelligent row closing module obtains the currently activated target row information from the bank management module, including: The intelligent row closing module obtains the address information of the target command and identifies the target bank pointed to by the address information; The intelligent row closing module queries the target page entry where the target bank is located in multiple page entries of the bank management module and obtains the currently activated target row information stored in the target page entry.

7. The method according to claim 1 or 6, characterized in that, The matching relationship between the target command and the target row information, and the matching relationship between the other commands in the command queue and the target row information are represented in the following manner: The bank and row pointed to by the address information of the target command are both correspondingly consistent with the bank and row represented by the target row information, and the bank and row pointed to by the address information of the other commands in the command queue are also correspondingly consistent with the bank and row represented by the target row information.

8. The method according to claim 1, wherein The method further includes: Whenever a new command is written into the command queue, the intelligent row closing module determines whether there are row conflict commands among the commands currently stored in the command queue, and determines whether to add an automatic precharge flag to the commands in the command queue according to the judgment result.

9. A DDR controller, characterized in that, The DDR controller includes an intelligent row closing module, a bank management module, and a command queue, where: The bank management module is used to provide the intelligent row closing module with the target row information of the currently activated row; The command queue is used to store each command to be executed; The intelligent row closing module is used to determine one or more target commands including the row conflict command among the commands when it is determined that there are row conflict commands among the commands stored in the command queue, and add an automatic precharge flag to the target commands; for any target command to be processed currently, obtain the target row information of the currently activated row from the bank management module. If the target command matches the target row information and there are other commands in the command queue that also match the target row information, clear the automatic precharge flag in the target command, and send the target command with the cleared automatic precharge flag through the physical layer interface connected to the DDR controller.

10. A system on a chip, characterized in that, The system-on-chip includes a processor core, an on-chip network, a DDR controller, and a physical layer interface, where: The processor core is used to send data read / write commands to the DDR controller through the on-chip network; The DDR controller is used to execute the row activation scheduling method according to any one of claims 1 to 8 for the received data read / write commands; The physical layer interface is used to perform protocol conversion on the commands output by the DDR controller and send out the commands after protocol conversion.

Images