Control method, system and device for realizing double BIOS redundancy through FPGA and medium

Abstract

The invention relates to the technical field of server double BIOS redundancy, in particular to a control method, system and device for achieving double BIOS redundancy through an FPGA and a medium. The method comprises the following steps of: arranging two chips for storing the same BIOS (Basic Input / Output System) programs on a server mainboard; a chip selection signal of a main chip is subjected to default gating through the FPGA when the server is started, so that the system is guided to be started; the FPGA detects the starting state of the main chip in real time; when it is detected that the main chip is started abnormally, switching a chip selection signal to the standby chip; sending a reset signal to the mainboard to trigger system restart; booting the system to start through a BIOS program of the standby chip; and after successful guiding, controlling the BIOS program of the standby chip to be updated into the main chip. The method has the remarkable beneficial effects that the starting reliability of the server is improved, the circuit structure is simplified, the switching accuracy and efficiency are improved, and online BIOS program updating is supported.

Description

Technical Field

[0001] This application relates to the technical field of server dual - BIOS redundancy, and relates to a control method, system, device and medium for implementing dual - BIOS redundancy through FPGA. Background Art

[0002] Currently, with the rapid development of information technology, servers, as the core devices for data processing and storage, their stability and reliability have become the focus of attention in all industries. During the operation of a server, it needs to rely on the BIOS (Basic Input / Output System) to perform key tasks such as hardware initialization, device configuration, and loading the operating system. As the bridge between hardware and the operating system, the normal operation of the BIOS is of crucial significance for the startup and subsequent operations of the server.

[0003] However, the traditional single - BIOS design has obvious defects. Once the BIOS chip is damaged or fails due to various reasons (such as unstable voltage, hardware aging, virus attack, etc.), the server will be unable to complete the startup process, resulting in serious consequences such as data loss and service interruption. This risk not only affects the reliability and availability of the server but may also cause huge losses to the user's business operations.

[0004] To solve this problem, the industry has begun to explore dual - BIOS redundancy technology. The dual - BIOS redundancy design configures two BIOS chips (usually referred to as the primary BIOS and the backup BIOS) on the server motherboard and stores the same BIOS program in these two chips to achieve redundant backup of the BIOS. When the primary BIOS fails, the backup BIOS can quickly take over its work and boot the server normally. This design greatly enhances the fault - tolerance ability of the server and improves the reliability and stability of the system.

[0005] However, during the implementation of dual - BIOS redundancy, technical problems also arise. How to effectively switch between the primary and backup BIOS chips to ensure that the backup BIOS can be quickly started when the primary BIOS fails has become an urgent problem to be solved. Traditional switching methods often rely on complex circuit designs and cumbersome manual operations, which not only increase the complexity of the system but may also introduce new fault points and reduce the reliability and flexibility of the system.

[0006] In addition, how to automatically update the BIOS program in the backup BIOS chip when the primary BIOS fails is also a technical challenge. Since the update of the BIOS program involves the interaction between hardware and software, it is necessary to ensure that the update process is both accurate and efficient. Traditional update methods often rely on external devices (such as USB flash drives, optical discs, etc.) for manual update, which is not only cumbersome to operate but may also cause the system to crash due to errors during the update process.

[0007] Therefore, there is an urgent need in the industry for a technical solution that can efficiently and reliably implement dual - BIOS redundant switching and automatic update. Such a solution needs to simplify the circuit structure, reduce system complexity, and improve the accuracy and efficiency of switching and updating. At the same time, this solution also needs to have a high degree of flexibility and maintainability to adapt to changes in different application scenarios and user requirements.

[0008] It should be noted that the information disclosed in the above - mentioned background technology section is only used to enhance the understanding of the background of this application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0009] To have a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary is not a general review, nor is it intended to identify key / important constituent elements or delineate the protection scope of these embodiments. Instead, it serves as a preface to the subsequent detailed description.

[0010] Embodiments of the present disclosure provide a control method, system, device, and medium for implementing dual - BIOS redundancy through FPGA, which solve the reliability and stability problems existing in the traditional single - BIOS design and the technical problems in the process of implementing dual - BIOS redundancy.

[0011] In some embodiments, the method includes:

[0012] Set two flash chips storing the same BIOS program on the server motherboard, where one is the main flash chip and the other is the backup flash chip;

[0013] When the server starts up, the FPGA defaults to select the chip - select signal of the main flash chip to boot the system;

[0014] The FPGA detects the startup status of the main flash chip in real - time;

[0015] When it is detected that the main flash chip has an abnormal startup, perform the following operations: switch the chip - select signal to the backup flash chip; send a reset signal to the motherboard to trigger a system restart; boot the system through the BIOS program of the backup flash chip;

[0016] After the backup flash chip successfully boots, control the BIOS program of the backup flash chip to be updated into the main flash chip.

[0017] Preferably, the step of detecting the startup status of the main flash chip includes:

[0018] Control the CPU's GPIO pin to output a level signal through the BIOS program;

[0019] The FPGA monitors the level change of the GPIO pin;

[0020] If the level of the GPIO pin does not reach the expected state within the preset time, it is determined that the main flash chip fails to start.

[0021] Preferably, the step of switching the chip select signal is specifically:

[0022] The FPGA dynamically binds the SPI chip select signal of the CPU to the chip select channel of the primary and backup flash chips through an internal logic circuit;

[0023] During the switching process, the chip select signal connection of the main flash chip is disconnected, and the chip select signal of the backup flash chip is enabled.

[0024] Preferably, the step of updating the main flash chip includes:

[0025] After the backup flash chip is successfully booted, the FPGA sends a backup instruction to the CPU;

[0026] The CPU responds to the instruction and reads the backup BIOS program from the hard disk;

[0027] The backup BIOS program is written into the main flash chip through an in-circuit programming operation, and the updated program takes effect after the next power-off and restart.

[0028] Preferably, the method further includes:

[0029] After each power-off and restart of the server, the FPGA automatically resets the chip select signal and preferentially selects the chip select channel of the main flash chip.

[0030] Preferably, the change state of the level signal is as follows: When the BIOS program starts, the BIOS program controls the GPIO pin of the CPU to be pulled high, and after the boot is completed, it controls the GPIO pin of the CPU to be pulled low; When the BIOS program is abnormal, the GPIO pin remains high, and the FPGA triggers a switching action when the high level duration is detected to exceed the preset threshold.

[0031] In some embodiments, the system includes:

[0032] Two on-board flash chips that respectively store the same BIOS program;

[0033] An FPGA connected to the flash chip, which is used to detect the startup state of the main flash chip;

[0034] The FPGA is configured as:

[0035] When the server starts up, the chip select signal of the main flash chip is defaultly selected to boot the system;

[0036] When it is detected that the main flash chip fails to start up normally, switch the chip select signal to the standby flash chip and trigger a system reset to boot through the standby flash chip;

[0037] After the standby flash chip successfully boots, control the BIOS program of the standby flash chip to be updated into the main flash chip.

[0038] Preferably, the way for the FPGA to trigger a system reset includes sending a reset signal to the motherboard and controlling the chip select signal of the standby flash chip to take effect after the reset is completed.

[0039] In some embodiments, the device includes a processor and a memory storing program instructions, and the processor is configured to execute the control method for implementing dual BIOS redundancy through the FPGA when running the program instructions.

[0040] In some embodiments, the storage medium stores a computer program, and when the program is executed by a processor, it implements the control method for implementing dual BIOS redundancy through the FPGA.

[0041] A control method, system, device and medium for implementing dual BIOS redundancy through an FPGA provided by an embodiment of the present disclosure can achieve the following technical effects:

[0042] First, this solution greatly improves the reliability of the server's normal startup by having two on-board flash chips and implementing dual BIOS redundancy. In the traditional single-BIOS design, once the BIOS fails, the server will not be able to start, bringing great inconvenience to users and the risk of data loss. In this solution, when the main BIOS is abnormal, the backup BIOS can quickly take over to boot the server and ensure the continuous operation of the server.

[0043] Secondly, this solution uses the FPGA to judge the startup state and realizes the flexible switching of flash chips. As a field-programmable gate array, the FPGA has high flexibility and programmability, and can accurately control the CS chip select signal of the flash chip to achieve fast switching between the main and backup BIOS chips. This design not only simplifies the circuit structure, reduces the complexity of the system, but also improves the accuracy and efficiency of switching.

[0044] In addition, this solution also supports the function of online updating the BIOS program from the standby flash chip to the main flash chip. In traditional dual-BIOS designs, updating the BIOS program often requires manual operation, which is not only cumbersome but also error-prone. However, with the control of the FPGA in this solution, automatic updating of the BIOS program is achieved, greatly improving the flexibility and maintainability of the system. At the same time, this online updating method also ensures that the BIOS program in the main BIOS chip is always in the latest version, further enhancing the stability and security of the system.

[0045] In summary, a design solution for achieving dual-BIOS redundancy through FPGA proposed in this invention patent has significant beneficial effects such as improving the startup reliability of the server, simplifying the circuit structure, enhancing the switching accuracy and efficiency, and supporting online updating of the BIOS program. This solution provides a new implementation method for the dual-BIOS redundancy design of servers, contributing to the further development and application of server technology.

[0046] The above general description and the following description are only exemplary and explanatory, and are not used to limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations and the drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation, and among them:

[0048] Figure 1 is a schematic diagram of the method flow of the present invention;

[0049] Figure 2 is a schematic diagram of the principle of achieving dual-BIOS redundancy through FPGA;

[0050] Figure 3 is a schematic diagram of the overall control flow of the present invention;

[0051] Figure 4 is a schematic diagram of the device structure of the disclosed embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] In order to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the drawings. The attached drawings are for reference and illustration purposes only, and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, numerous details are provided to give a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be shown in a simplified manner to simplify the drawings.

[0053] In the description and claims of the embodiments of the present disclosure and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0054] Unless otherwise specified, the term "plurality" means two or more.

[0055] In the embodiments of the present disclosure, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0056] The term "and / or" is an associative relationship describing an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, the three relationships of A and B.

[0057] The term "corresponding" may refer to an associative relationship or a binding relationship. A corresponding to B means that there is an associative relationship or a binding relationship between A and B.

[0058] Embodiment 1

[0059] As Figure 1 and Figure 3 shown, a control method for implementing dual BIOS redundancy through FPGA utilizes the flexibility and programmability of FPGA to achieve flexible switching between the primary and backup BIOS chips by controlling the CS (chip select) signal of the flash chip. At the same time, this solution also supports the function of the backup BIOS chip to update the BIOS program online to the primary BIOS chip, further improving the reliability and flexibility of the system.

[0060] Specifically, the method includes:

[0061] S1: Set two flash chips storing the same BIOS program on the server motherboard, one of which is the primary flash chip and the other is the backup flash chip.

[0062] As a refinement of the above embodiment, the server motherboard integrates two primary and backup flash chips to store the BIOS program. By default, the CPU uses the CS1 path to select the primary flash to read the BIOS and boot. The FPGA program defaults to selecting the chip select of the primary flash to ensure that the device boots from the primary flash chip every time after power-off and power-on, avoiding abnormal startup in extreme cases (such as abnormal power-off and restart of the device when the switching action or backup action is not completed).

[0063] S2: When the server starts up, the FPGA default-selects the chip select signal of the main flash chip to boot the system.

[0064] S3: The FPGA detects the startup status of the main flash chip in real time.

[0065] As a refinement of the above embodiment, the judgment function is realized by the FPGA judging the high and low levels of the GPIO status signal on the CPU. Hardware-wise, a GPIO of the CPU is connected to the FPGA. During the operation of the BIOS, the BIOS program controls the GPIO pin of the CPU to be pulled high, and after the boot is completed, the GPIO pin of the CPU is controlled to be pulled low. The FPGA judges whether the BIOS program is executed normally by detecting the change of the high and low levels of the GPIO pin.

[0066] Specifically, the steps of detecting the startup status of the main flash chip include:

[0067] The BIOS program controls the GPIO pin of the CPU to output a level signal;

[0068] The FPGA monitors the level change of the GPIO pin;

[0069] If the level of the GPIO pin does not reach the expected state within the preset time, it is determined that the startup of the main flash chip is abnormal. The preset time in this embodiment is 20 seconds, and this time needs to be verified through debugging according to the actual debugging situation of the specific board.

[0070] S4: When it is detected that the startup of the main flash chip is abnormal, perform the following operations: switch the chip select signal to the standby flash chip; send a reset signal to the motherboard to trigger a system restart; boot the system through the BIOS program of the standby flash chip.

[0071] As a refinement of the above embodiment, when the BIOS program in the main flash starts up abnormally, the status signal sent by the GPIO pin of the CPU controlled by the BIOS program to the FPGA is abnormal.

[0072] After the FPGA detects that the status signal is abnormal, it switches the chip select signal to the standby flash chip, and at the same time sends a reset signal to the motherboard to reset the system, and boots through the standby flash;

[0073] Specifically, the steps of switching the chip select signal are as follows:

[0074] The FPGA dynamically binds the SPI chip select signal of the CPU with the chip select channels of the main and standby flash chips through the internal logic circuit; during the switching process, the connection of the chip select signal of the main flash chip is disconnected, and the chip select signal of the standby flash chip is enabled.

[0075] During the system restart process, the BIOS program in the backup flash chip is read and the system is successfully booted. A signal indicating normal startup is sent to the FPGA through the GPIO status signal. At this time, the backup flash program has been copied from the flash chip to the memory for operation.

[0076] S5: After the backup flash chip is successfully booted, control the BIOS program of the backup flash chip to be updated to the main flash chip.

[0077] As a refinement of the above embodiment, the backup function is mainly controlled by the backup pin output by the FPGA. The block diagram for implementing the backup function is as Figure 1 shown. When the main flash is normally booted, the backup signal sent by the FPGA is detected to determine whether a switch is needed; during normal boot, the FPGA sends a signal indicating no backup to the CPU, and the main flash boots the system normally.

[0078] When the main flash is abnormal, the FPGA controls the chip select signal to switch to the backup flash for booting. During the normal boot process of the BIOS, the BIOS program will be copied to the memory; at this time, the FPGA determines that the backup flash boot is successful and a program backup is required, and sends a switching instruction to the switching chip. The CS chip select channel is switched from the main flash chip select to the backup flash chip select channel; the FPGA outputs a signal indicating that backup is needed to the CPU. After detecting it, the CPU burns the BIOS program in the hard disk to the main flash chip to complete the backup, which takes effect when the power is off and restarted next time.

[0079] As a refinement of the above embodiment, the method further includes:

[0080] After each power-off restart of the server, the FPGA automatically resets the chip select signal and preferentially selects the chip select channel of the main flash chip.

[0081] As a refinement of the above embodiment, the change state of the level signal is as follows: When the BIOS program starts, the GPIO pin of the CPU controlled by the BIOS program is pulled high, and after the boot is completed, the GPIO pin of the CPU is pulled low again; when the BIOS program is abnormal, the GPIO pin remains high, and the FPGA triggers a switching action when detecting that the high level duration exceeds a preset threshold.

[0082] It should be noted that: This solution uses two on-board flash chips to implement dual BIOS redundancy, greatly improving the reliability of the server's normal startup. In the traditional single BIOS design, once the BIOS fails, the server will not be able to start, bringing great inconvenience to users and the risk of data loss. In this solution, when the main BIOS is abnormal, the backup BIOS can quickly take over to boot the server and ensure the continuous operation of the server.

[0083] This solution uses an FPGA to judge the startup state and realizes the flexible switching of flash chips. As a field-programmable gate array, the FPGA has high flexibility and programmability, and can accurately control the CS chip selection signal of the flash chip to achieve fast switching between the primary and backup BIOS chips. This design not only simplifies the circuit structure, reduces the complexity of the system, but also improves the accuracy and efficiency of switching.

[0084] This solution also supports the function of online updating the BIOS program from the backup flash chip to the primary flash chip. In traditional dual-BIOS designs, the update of the BIOS program often requires manual operation, which is both cumbersome and error-prone. However, through the control of the FPGA in this solution, the automatic update of the BIOS program is realized, greatly improving the flexibility and maintainability of the system. At the same time, this online update method also ensures that the BIOS program in the primary BIOS chip is always in the latest version, further improving the stability and security of the system.

[0085] In summary, a design solution for realizing dual-BIOS redundancy through an FPGA proposed in this invention patent has significant beneficial effects such as improving the startup reliability of the server, simplifying the circuit structure, improving the accuracy and efficiency of switching, and supporting the online update of the BIOS program. This solution provides a new implementation method for the dual-BIOS redundancy design of servers, which helps to promote the further development and application of server technology.

[0086] Embodiment 2

[0087] As Figure 2 shown, a control system for realizing dual-BIOS redundancy through an FPGA is a design system for realizing dual-BIOS redundancy through an FPGA (field-programmable gate array). This system utilizes the flexibility and programmability of the FPGA to achieve flexible switching and automatic update of the primary and backup BIOS chips by controlling the CS (chip selection) signal of the flash chip. This design not only solves the technical problems in traditional dual-BIOS redundancy technologies, but also provides new guarantees for the stability and reliability of servers. It includes:

[0088] Two on-board flash chips that store the same BIOS program respectively.

[0089] An FPGA connected to the flash chip, which is used to detect the startup state of the primary flash chip.

[0090] The FPGA is configured as:

[0091] When the server starts up, the chip selection signal of the primary flash chip is defaultly selected to boot the system;

[0092] When it is detected that the main flash chip fails to start properly, switch the chip select signal to the backup flash chip and trigger a system reset to boot through the backup flash chip;

[0093] After the backup flash chip successfully boots, control the BIOS program of the backup flash chip to be updated into the main flash chip.

[0094] As a refinement of the above embodiment, the FPGA receives a status signal through the GPIO pins of the CPU to determine the running status of the BIOS program, specifically including:

[0095] When the BIOS program runs normally, control the GPIO pins to output a first level signal;

[0096] When the BIOS program is abnormal, the GPIO pins maintain or output a second level signal;

[0097] The FPGA performs a switching action of the chip select signal according to the change of the level signal.

[0098] Combined Figure 4 As shown, an embodiment of the present disclosure provides a control device 300 for implementing dual BIOS redundancy through an FPGA, including a processor 304 and a memory 301. Optionally, the device may further include a communication interface 302 and a bus 303. Among them, the processor 304, the communication interface 302, and the memory 301 can complete mutual communication through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can call the logical instructions in the memory 301 to execute the control method for implementing dual BIOS redundancy through the FPGA in the above embodiment.

[0099] In addition, when the logical instructions in the above-mentioned memory 301 are implemented in the form of software function units and sold or used as an independent product, they can be stored in a computer-readable storage medium.

[0100] The memory 301, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes functional applications and data processing by running the program instructions / modules stored in the memory 301, that is, implements the control method for implementing dual BIOS redundancy through the FPGA in the above embodiment.

[0101] The memory 301 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of the terminal device and the like. In addition, the memory 301 may include a high-speed random access memory and may also include a non-volatile memory.

[0102] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are configured to execute the above-mentioned control method for implementing dual BIOS redundancy through an FPGA.

[0103] The above-mentioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transient computer-readable storage medium.

[0104] The technical solution of the embodiment of the present disclosure may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The foregoing storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc, and other media that can store program codes, or may also be a transient storage medium.

[0105] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure, enabling those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process, and other changes. The embodiments only represent possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only for describing the embodiments and do not limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to also include the plural forms. Similarly, as used in this application, the term "and / or" refers to any and all possible combinations of one or more of the associated listed items. Additionally, when used in this application, the term "comprise" and its variants "comprises" and / or "comprising" etc. mean the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups of these. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, or device comprising the element. Herein, each embodiment may focus on the differences from other embodiments, and the same or similar parts among the embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method parts disclosed in the embodiments, the relevant parts may refer to the description of the method parts.

[0106] Those skilled in the art will realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software may depend on the specific application and design constraints of the technical solution. The technician may use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the embodiments of the present disclosure. The technician can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0107] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units can be merely a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Additionally, the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms. The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to implement this embodiment. Additionally, in the embodiments of the present disclosure, the various functional units can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit.

[0108] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions marked in the blocks can occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, which can depend on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks can also occur in a different order than that disclosed in the description. Sometimes, there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, which can depend on the functions involved. Each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A control method for implementing dual BIOS redundancy through FPGA, characterized in that It includes the following steps: Set two flash chips storing the same BIOS program on the server motherboard, where one is the main flash chip and the other is the backup flash chip; When the server starts up, the FPGA default selects the chip select signal of the main flash chip through the FPGA to boot the system; The FPGA detects the startup status of the main flash chip in real time; When it is detected that the main flash chip has an abnormal startup, perform the following operations: switch the chip select signal to the backup flash chip; send a reset signal to the motherboard to trigger a system restart; Boot the system through the BIOS program of the backup flash chip; After the backup flash chip successfully boots, control the BIOS program of the backup flash chip to be updated into the main flash chip.

2. The control method for implementing dual BIOS redundancy through FPGA according to claim 1, characterized in that The step of detecting the startup status of the main flash chip includes: Control the CPU's GPIO pin to output a level signal through the BIOS program; The FPGA monitors the level change of the GPIO pin; If the level of the GPIO pin does not reach the expected state within the preset time, it is determined that the main flash chip has an abnormal startup.

3. The control method for implementing dual BIOS redundancy through FPGA according to claim 1, characterized in that, The step of switching the chip select signal is specifically: The FPGA dynamically binds the CPU's SPI chip select signal and the chip select channels of the main and backup flash chips through the internal logic circuit; During the switching process, disconnect the connection of the chip select signal of the main flash chip and enable the chip select signal of the backup flash chip.

4. The control method for implementing dual BIOS redundancy through FPGA according to claim 1, wherein The step of updating to the main flash chip includes: After the backup flash chip successfully boots, the FPGA sends a backup instruction to the CPU; The CPU responds to the instruction and reads the backed-up BIOS program from the hard disk; Write the backed-up BIOS program into the main flash chip through an in-line programming operation, and the updated program takes effect after the next power-off and restart.

5. The control method for implementing dual BIOS redundancy through FPGA according to claim 1, wherein The method further includes: After each power-off and restart of the server, the FPGA automatically resets the chip select signal and preferentially selects the chip select channel of the main flash chip.

6. The control method for implementing dual BIOS redundancy through FPGA according to claim 2, characterized in that The change status of the level signal is as follows: when the BIOS program starts, the BIOS program controls the CPU's GPIO pin to pull high, and after the boot is completed, it controls the CPU's GPIO pin to pull low; when the BIOS program is abnormal, the GPIO pin remains high, and the FPGA triggers a switching action when it detects that the high level duration exceeds the preset threshold.

7. A control system for implementing dual BIOS redundancy through FPGA using the method according to any one of claims 1-6, characterized in that, It includes: Two on-board flash chips, which respectively store the same BIOS program; The FPGA connected to the flash chip, which is used to detect the startup status of the main flash chip; The FPGA is configured as: When the server starts up, default select the chip select signal of the main flash chip to boot the system; When it is detected that the main flash chip has an abnormal startup, switch the chip select signal to the backup flash chip and trigger a system reset to boot through the backup flash chip; After the backup flash chip successfully boots, control the BIOS program of the backup flash chip to be updated into the main flash chip.

8. The control system for implementing dual BIOS redundancy through FPGA according to claim 7, characterized in that, The way to reset the FPGA trigger system includes sending a reset signal to the main board and controlling the chip select signal of the spare flash chip to become effective after the reset is completed.

9. A control device for implementing dual BIOS redundancy through an FPGA, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute the server method for implementing dual BIOS redundancy through FPGA as described in any one of claims 1-6 when running the program instructions.

10. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and when the program is executed by the processor, it implements the control method for implementing dual BIOS redundancy through FPGA as described in any one of the above claims 1-6.

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