Multi-core device and multi-core operation method

Abstract

The invention provides a multi-core device and a multi-core operation method. The multi-core device may include a first core, a second core, and a memory circuit. The second core can obtain a compiler and a source code corresponding to the first core, and compile the source code by using the compiler. The second core has a higher operational capability than the first core. The memory circuit may couple the first core and the second core. The first core and the second core may share a memory circuit.

Description

Technical Field

[0001] Embodiments of the present invention are mainly related to a multi-core technology, and particularly to a multi-core technology in a multi-core device for compiling a core with weak computing power by a core with strong computing power. Background Art

[0002] Currently, many processors or integrated circuits (ICs) are configured with a heterogeneous core architecture. In this dual-core architecture, a core with high power consumption but strong computing power and a core with low power consumption but relatively low computing power can be configured. These two cores can share a memory section and cooperate in different operations to reduce power consumption and load.

[0003] However, during the development stage of currently configured dual-core devices, the dual-core device needs to be additionally connected to an external tool (e.g., a Serial Wire Debug (SWD) tool) to compile and debug the core with weak computing power. In addition, during the mass production stage of currently configured dual-core devices, the training model of the core with weak computing power needs to be trained via an external electronic device.

[0004] Therefore, how to more efficiently and quickly compile and debug the core with weak computing power, and train and update its training model will be a research topic worthy of study. Summary of the Invention

[0005] In view of the problems in the above background art, embodiments of the present invention provide a multi-core device and a multi-core operation method.

[0006] According to an embodiment of the present invention, a multi-core device is provided. The multi-core device may include a first core, a second core, and a memory circuit. The second core can obtain a compiler and a source code corresponding to the first core, and use the compiler to compile the source code. The computing power of the second core is stronger than that of the first core. The memory circuit can be coupled to the first core and the second core. The first core and the second core can share the memory circuit.

[0007] According to some embodiments of the present invention, after the second core compiles the source code, the second core can load the compiled source code into a section of the memory circuit corresponding to the first core. Then, the first core can execute the compiled source code to generate an execution result, and store the execution result in a register and the memory circuit. The second core can read the execution result from the register and the memory circuit to debug the execution result.

[0008] According to some embodiments of the present invention, a second core may collect data corresponding to a first core in a field environment and analyze the data to train a training model corresponding to the first core. The second core may load the trained training model into a section corresponding to the first core in a memory circuit to update the training model. In addition, the first core may execute the updated training model to generate an execution result, and the second core may determine whether to continue training the training model based on the execution result.

[0009] According to some embodiments of the present invention, a multi-core device may obtain a compiler and source code corresponding to a first core from a debug controller via a wireless communication method.

[0010] According to an embodiment of the present invention, a multi-core operation method is provided. The multi-core operation method may be applicable to a multi-core device. The multi-core operation method may include the following steps: obtaining, by a second core of the multi-core device, a compiler and a source code corresponding to a first core of the multi-core device, wherein the computing power of the second core is stronger than that of the first core; and compiling, by the second core, the source code using the compiler.

[0011] Regarding other additional features and advantages of the present invention, those skilled in the art can make some modifications and refinements according to the multi-core device and multi-core operation method disclosed in the implementation method of this case without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0013] Figure 1 is a block diagram showing a multi-core device 100 according to an embodiment of the present invention.

[0014] Figure 2 is a flowchart of a multi-core operation method in a development stage according to an embodiment of the present invention.

[0015] Figure 3 is a flowchart of a multi-core operation method in a mass production stage according to an embodiment of the present invention.

[0016] Figure 4 is a flowchart of a multi-core operation method according to an embodiment of the present invention.

[0017]

Symbolic Explanation

[0018] 100: Multi-core device

[0019] 110: First core

[0020] 120: Second core

[0021] 121: Compiler

[0022] 130: Communication circuit

[0023] 140: Memory circuit

[0024] 150: Register

[0025] 200: Debug controller

[0026] S210~S270, S310~S360, S410~S420: Steps Detailed implementation manners

[0027] What is described in this section is the preferred manner of implementing the present invention, aiming to illustrate the spirit of the present invention rather than limiting the protection scope of the present invention. The protection scope of the present invention shall be subject to what is defined in the claims.

[0028] Figure 1 is a block diagram of a multi-core device 100 according to an embodiment of the present invention. As Figure 1 shown, the multi-core device 100 may include a first core 110, a second core 120, a communication circuit 130, a memory circuit 140, and a register 150. It should be noted that in the Figure 1 block diagram shown, it is only for conveniently illustrating the embodiments of the present invention, but the present invention is not limited to Figure 1 . Other elements may also be included in the multi-core device 100.

[0029] According to an embodiment of the present invention, the first core 110 may be a low-power core, which can be used to process immediate and low-computation operations.

[0030] According to an embodiment of the present invention, the second core 120 may be a high-performance core, which can be used to process more complex operations. That is to say, in the embodiments of the present invention, the second core 120 has better computing power than the first core 110.

[0031] In addition, according to an embodiment of the present invention, the second core 120 may have a compiler 121 corresponding to the first core 110. The second core 120 may obtain the compiler 121 corresponding to the first core 110 from a debug console 200 or a development board, or the compiler 121 corresponding to the first core 110 may also be directly built into the second core 120. The compiler 121 can be used to compile the source code of the first core 110. That is, in an embodiment of the present invention, when the multi-core device 100 is in a development stage, the second core 120 can be used to directly compile and debug the source code of the first core 110. In addition, in an embodiment of the present invention, when the multi-core device 100 is in a mass production stage, the second core 120 can be directly used to train and update the training model corresponding to the first core 110. There will be a more detailed description below.

[0032] According to an embodiment of the present invention, the communication circuit 130 can obtain the compiler 121 and the source code corresponding to the first core 110 from the debug console 200 via a wireless communication method (for example: 4G, 5G, Wi-Fi, but the present invention is not limited thereto). The compiler 121 and the source code corresponding to the first core 110 possessed by the debug console 200 can come from a remote electronic device.

[0033] According to an embodiment of the present invention, the memory circuit 140 can be a volatile memory (for example: Random Access Memory, RAM), or a non-volatile memory (for example: flash memory, Read Only Memory, ROM), a hard disk, or a combination of the above devices. The memory circuit 140 can be used to store information and code related to multi-core operations. The first core 110 and the second core 120 can share the memory circuit 140.

[0034] According to an embodiment of the present invention, the register 150 can be used to store the source code compiled by the compiler 121 executed by the first core 110 to generate an execution result.

[0035] According to another embodiment of the present invention, the debug controller 200 can also be integrated into the multi-core device 100. That is to say, the debug controller 200 can first obtain the compiler 121 and the source code corresponding to the first core 110 from a remote device via the communication circuit 130, and store the obtained data in the shared memory circuit 140. The second core 120 then obtains the compiler 121 and the source code corresponding to the first core 110 from the shared memory circuit 140. In addition, according to another embodiment of the present invention, the debug controller 200 can also be implemented by software. That is to say, after executing the software corresponding to the debug controller 200, the communication circuit 130 can first obtain the compiler 121 and the source code corresponding to the first core 110 from a remote device, and store the obtained data in the shared memory circuit 140. The second core 120 then obtains the compiler 121 and the source code corresponding to the first core 110 from the shared memory circuit 140.

[0036] Figure 2 is a flowchart of a multi-core operation method in a development stage according to an embodiment of the present invention. As Figure 2 shown, in step S210, during the development stage of the multi-core device 100, the multi-core device 100 can be connected to the debug controller 200 via a wireless communication method.

[0037] In step S220, the multi-core device 100 can obtain the compiler 121 and the source code corresponding to the first core 110 of the multi-core device 100 from the debug controller 200.

[0038] In step S230, the second core 120 of the multi-core device 100 can use the compiler 121 to compile the source code corresponding to the first core 110.

[0039] In step S240, the second core 120 can load (or burn) the compiled source code into the section corresponding to the first core 110 in the memory circuit 140 of the multi-core device 100.

[0040] In step S250, the first core 110 can read the compiled source code from the section corresponding to the first core 110 in the memory circuit 140, and execute the compiled source code to generate an execution result.

[0041] In step S260, the first core 110 can store the execution result in the memory circuit 140 and the register 150.

[0042] In step S270, the second core 120 can read the execution result of the first core 110 from the memory circuit 140 and the register 150, and debug the execution result of the first core 110. If the second core 120 detects an error, after debugging, the process can return to step S230. The second core 120 can then use the compiler 121 to compile the debugged source code.

[0043] Compared with the multi-core operation in the traditional development stage, in an embodiment of the present invention, during the development stage of the multi-core device 100, the core with stronger computing power in the multi-core device 100 (e.g., the second core 120) can directly compile and debug the core with weaker computing power (e.g., the first core 110). That is to say, the multi-core device 100 will not need to additionally connect an external tool (e.g., a Serial Wire Debug (SWD) tool) to compile and debug the core with weaker computing power (e.g., the first core 110). Therefore, the multi-core device 100 can save pin points and more immediately compile and debug the core with weaker computing power (e.g., the first core 110).

[0044] Figure 3 is a flowchart of a multi-core operation method in a mass production stage according to an embodiment of the present invention. As Figure 3 shown, in step S310, during the mass production stage of the multi-core device 100, the multi-core device 100 can be connected to the debug controller 200 via a wireless communication method in a field environment (e.g., a factory).

[0045] In step S320, the second core 120 can directly collect a piece of data (e.g., sound, vibration, temperature, etc.) corresponding to the first core 110 in the field environment, and analyze the data corresponding to the first core 110.

[0046] In step S330, the second core 120 can train a training model (e.g., a machine learning model) or source code corresponding to the first core 110 according to the data corresponding to the first core 110 in the field environment after collection and analysis, to obtain a training result (i.e., the trained training model or source code).

[0047] In step S340, the second core 120 can compile the training result and load it into the section corresponding to the first core 110 in the memory circuit 140, to update the training model or source code corresponding to the first core 110.

[0048] In step S350, the first core 110 may read the updated training model or source code from the section of the memory circuit 140 corresponding to the first core 110, and execute the updated training model or source code to generate an execution result.

[0049] In step S360, the second core 120 may determine whether to continue training the training model or source code corresponding to the first core 110 according to the execution result of the first core 110.

[0050] Compared with the multi-core operation in the traditional development stage, in an embodiment of the present invention, at the mass production stage of the multi-core device 100, the core with stronger computing power in the multi-core device 100 (e.g., the second core 120) can directly collect and analyze the data of the core with weaker computing power (e.g., the first core 110), and instantaneously train and update the training model or source code corresponding to the core with weaker computing power. That is to say, the multi-core device 100 will not need to train the core with weaker computing power via an external electronic device.

[0051] Figure 4 is a flowchart of a multi-core operation method 400 according to an embodiment of the present invention. The multi-core operation method is applicable to the multi-core device 100. As Figure 2 shown, in step S410, a second core of the multi-core device 100 may obtain a compiler and a source code corresponding to a first core of the multi-core device 100 from a debug controller. The computing power of the second core is stronger than that of the first core. In addition, the first core and the second core may share a memory circuit of the multi-core device 100.

[0052] In step S420, the second core of the multi-core device 100 may use the compiler to compile the above source code.

[0053] According to an embodiment of the present invention, in the multi-core operation method, the second core of the multi-core device 100 may load the compiled above source code into a section of the memory circuit of the multi-core device corresponding to the first core.

[0054] According to an embodiment of the present invention, in the multi-core operation method, the first core of the multi-core device 100 may execute the compiled above source code to generate an execution result, and store the execution result in a register and the memory circuit.

[0055] According to an embodiment of the present invention, in the multi-core operation method, the second core of the multi-core device 100 may read the execution result from the register and the memory circuit to debug the execution result.

[0056] According to an embodiment of the present invention, in a multi-core operation method, a second core of the multi-core device 100 may collect data corresponding to the first core in a field environment and analyze the data to train a training model corresponding to the first core.

[0057] According to an embodiment of the present invention, in a multi-core operation method, the second core of the multi-core device 100 may load the trained training model into a section corresponding to the first core in the memory circuit to update the training model.

[0058] According to an embodiment of the present invention, in a multi-core operation method, the first core of the multi-core device 100 may execute the updated training model to generate an execution result, and the second core of the multi-core device 100 may determine whether to continue training the training model based on the execution result.

[0059] According to an embodiment of the present invention, in a multi-core operation method, the multi-core device 100 obtains the compiler and the source code corresponding to the first core from the debug controller via a wireless communication method.

[0060] According to the multi-core operation method of the present invention, in the development stage, the multi-core device will not need to be additionally connected to an external tool to compile and debug a core with relatively weak computing power. In addition, according to the multi-core operation method of the present invention, in the mass production stage, the multi-core device will not need to train a core with relatively weak computing power via an external electronic device.

[0061] The serial numbers in this specification and the claims, such as "first", "second", etc., are only for convenience of description, and there is no sequential precedence relationship between them.

[0062] The steps of the methods and algorithms disclosed in the specification of the present invention can be directly applied to hardware and software modules or a combination of both by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data memory, such as a random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable diskette, compact disc read-only memory (CD-ROM), DVD, or any other computer-readable storage media format in the art. A storage media can be coupled to a machine device, for example, a computer / processor (for the convenience of illustration, represented as a processor in this specification), and the above processor can read information (such as code) and write information to the storage media. A storage media can integrate a processor. An application specific integrated circuit (ASIC) includes a processor and a storage media. A user device includes an application specific integrated circuit. In other words, the processor and the storage media are included in the user device in a way that does not directly connect to the user device. In addition, in some embodiments, any suitable computer program product includes a readable storage media, where the readable storage media includes code related to one or more disclosed embodiments. In some embodiments, the computer program product can include packaging materials.

[0063] The above paragraphs are described at multiple levels. Obviously, the teachings herein can be implemented in various ways, and any specific architecture or function disclosed in the examples is only a representative situation. According to the teachings herein, any person skilled in the art should understand that each level disclosed herein can be implemented independently or two or more levels can be combined and implemented.

[0064] Although this application has been disclosed as above by way of examples, it is not intended to limit this application. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of this application. Therefore, the protection scope of the invention shall be subject to what is defined by the claims.

Claims

1. A multi-core device, characterized in that, Comprising: A first core; A second core, obtaining a compiler and a source code corresponding to the first core, and using the compiler to compile the source code, wherein the computing power of the second core is stronger than that of the first core; And A memory circuit, coupled to the first core and the second core, wherein the first core and the second core can share the memory circuit.

2. The multi-core device according to claim 1, characterized in that After the second core compiles the source code, the second core loads the compiled source code into a section corresponding to the first core in the memory circuit.

3. The multi-core device according to claim 2, wherein The first core executes the compiled source code to generate an execution result, and stores the execution result in a register and the memory circuit.

4. The multi-core device according to claim 3, characterized in that, The second core reads the execution result from the register and the memory circuit to debug the execution result.

5. The multi-core device according to claim 1, characterized in that, The second core collects a piece of data corresponding to the first core in a field environment, and analyzes the data to train a training model corresponding to the first core.

6. A multi-core operation method, characterized in that, Applicable to a multi-core device, comprising: Obtaining, by a second core of the multi-core device, a compiler and a source code corresponding to a first core of the multi-core device, wherein the computing power of the second core is stronger than that of the first core; and Compiling, by the second core, the source code using the compiler.

7. The multi-core operation method according to claim 6, wherein Further comprising: Collecting, by the second core, a piece of data corresponding to the first core in a field environment; And Analyzing, by the second core, the data to train a training model corresponding to the first core.

8. The multi-core operation method according to claim 7, wherein Further comprising: Loading, by the second core, the trained training model into a section corresponding to the first core in the memory circuit to update the training model.

9. The multi-core operation method according to claim 8, wherein, Further comprising: Executing, by the first core, the updated training model to generate an execution result; And Judging, by the second core, whether to continue training the training model according to the execution result.

10. The multi-core operation method according to claim 6, wherein Further comprising: Obtaining, via a wireless communication method, the compiler and the source code corresponding to the first core from a debugging controller.

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