Universal asynchronous transceiver and system on chip
By introducing a routing controller in UART, the problem of UART interface occupying a large amount of IO Pad is solved, and the effect of reducing the SOC system area and cost is achieved.
Patent Information
- Application Number
- CN202510428432.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-07-18
AI Technical Summary
In the existing UART interface design, each UART interface corresponds one by one to the IO Pad, resulting in an increase in the area and cost of the SOC system.
By introducing a receiving-side routing controller and a sending-side routing controller in the UART, the routing of data between the input and output pins and the controller is realized, reducing the corresponding number of IO Pads.
It reduces the number of pin pads corresponding to UART in the system on chip, reduces the chip area and packaging size, reduces the chip cost, and improves the efficiency of software and hardware use.
Smart Images
Figure CN120336252A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of universal asynchronous receivers and transmitters, and particularly to a universal asynchronous receiver and transmitter and a system on a chip. Background Art
[0002] A universal asynchronous receiver transmitter (UART) is a serial, asynchronous, full-duplex communication protocol. Its working principle is to transmit each binary bit of the transmitted data one by one, making the communication line simple, and only a pair of transmission lines is required to achieve two-way full-duplex communication. UART is suitable for long-distance connections and is widely used in fields such as computer systems and industrial automation instrumentation.
[0003] UART can be used as a peripheral interface of a system on a chip (SoC) for input and output of logic information of the SoC system, SoC system debugging, etc. With the development of SoC systems, the number of UART interfaces is increasing. However, in the current UART interface design, the controller in each UART interface corresponds one-to-one with the input / output (I / O) pin pads, that is, each UART has a set of independent I / O pads. When the UART designed as above is applied to the SOC system, multiple UART interfaces occupy a large number of pin pads, resulting in an increase in the area and cost of the SOC system. Summary of the Invention
[0004] This application provides a universal asynchronous receiver and transmitter and a system on a chip to at least improve the problem that when UART is applied to the SOC system in the related art, multiple UART interfaces occupy a large number of pin pads, resulting in an increase in the area and cost of the SOC system.
[0005] This application provides a universal asynchronous receiver and transmitter, which includes a receiving end routing controller, a receiving end controller, a transmitting end routing controller, and a transmitting end controller;
[0006] The input end of the receiving end routing controller is connected to the input pin of the system on a chip, and the output end of the receiving end routing controller is connected to the receiving end controller;
[0007] The input end of the transmitting end routing controller is connected to the transmitting end controller, and the output end of the transmitting end routing controller is connected to the output pin of the system on a chip;
[0008] Both the input pins and the output pins are connected to at least one universal asynchronous receiver / transmitter (UART). The receiving-end routing controller is used to route the data received from the input pins to the receiving-end controller of the target UART, and the transmitting-end routing controller is used to route the data received from the transmitting-end controller to the output pins connected to the target UART. The target UART is any one of the at least one UARTs.
[0009] This application also provides a system-on-chip (SoC), which includes at least one input pin, at least one output pin, and multiple UARTs of any one of the above types.
[0010] The input end of the receiving-end routing controller in the UART is connected to the first input pin, and the output end of the transmitting-end routing controller in the UART is connected to the first output pin. The first input pin is any one of the at least one input pins, and the first output pin is any one of the at least one output pins.
[0011] The UART provided by this application can forward data by adding a receiving-end routing controller and a transmitting-end routing controller, so that the receiving-end controller does not have to correspond to the input pins one by one and the transmitting-end controller does not have to correspond to the output pins one by one. As a result, the number of pin pads corresponding to the UART in the SoC can be reduced, the chip area and packaging size can be decreased, the chip cost can be lowered, the use of the UART in software and hardware can be improved, and at the same time, the design layout of the SoC can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0013] Figure 1 FIG. 18 is a schematic structural diagram of a UART provided by an embodiment of this application;
[0014] Figure 2 FIG. 22 is a schematic structural diagram of another UART provided by an embodiment of this application;
[0015] Figure 3 FIG. 26 is a schematic connection diagram of the UART provided by an embodiment of this application during external loopback;
[0016] Figure 4 FIG. 30 is a schematic connection diagram of the UART provided by an embodiment of this application during internal loopback;
[0017] Figure 5A schematic structural diagram of a system - on - a - chip provided by an embodiment of the present application;
[0018] Figure 6 Another schematic structural diagram of a system - on - a - chip provided by an embodiment of the present application.
[0019] Reference numerals: 110, receiving - end routing controller; 120, receiving - end controller; 130, transmitting - end routing controller; 140, transmitting - end controller; 150, system - interface routing controller. Detailed implementation manners
[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.
[0021] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.
[0022] An SoC system can be an integrated circuit that integrates most functions of a complete system on a single chip. Most functions can refer to a processor, a storage unit, dedicated function modules (such as analog - to - digital converters and wireless communication modules), and peripheral interfaces, etc.
[0023] Multiple universal asynchronous receiver - transmitters (UARTs) can be provided on the SoC system, enabling the SoC system to communicate with different types of devices and achieve data transmission and interaction. For example, in a smart home control chip, multiple UARTs can be provided. One UART can be connected to a temperature sensor to collect ambient temperature data in real - time, and another UART interface can be connected to a Bluetooth module to achieve wireless communication with external devices such as mobile phones, so that users can remotely control home appliances through the mobile phone.
[0024] With the development of the SoC system, the number of UART interfaces is increasing. For example, an SOC system can include UART interfaces for local input and output, UART interfaces for server host system input and output, etc.
[0025] Specifically, the UART can transmit data bit by bit, converting the data to be transmitted between serial communication and parallel communication. As an interface for converting parallel input signals into serial output signals, the UART is commonly used to connect various low-speed peripherals, such as sensors, modems, Bluetooth modules, etc.
[0026] Currently, commonly used UARTs generally include a transmitter controller and a receiver controller. The transmitter controller is used to convert parallel data into serial data and send the data to an electronic device connected to the system-on-chip through an output pin according to a set communication format. The receiver controller can receive the serial data input by an external electronic device through an input pin and convert the received serial data into parallel data for subsequent processing.
[0027] In the above UART structure design, the controller corresponds to the IO Pad one by one. When multiple UARTs are set in the SOC system, this requires multiple IO Pads, resulting in an increase in chip area and cost.
[0028] In view of this, the present application provides a universal asynchronous receiver-transmitter (UART). By additionally setting up a routing controller, the controller in the UART does not have to correspond to the IO Pad one by one, thereby reducing the number of Pads prepared by the system-on-chip for the UART, reducing the chip area and package size, and lowering the chip cost.
[0029] To enable those skilled in the art of this technology to better understand the solution of the present application, the following further detailed description of the present application is provided in conjunction with the accompanying drawings.
[0030] As Figure 1 shown, the universal asynchronous receiver-transmitter (UART) provided by the present application includes a receiver (RX) routing controller 110, a receiver controller 120, a transmitter (TX) routing controller 130, and a transmitter controller 140.
[0031] Among them, the input end of the receiver routing controller 110 is connected to the input pin (RX Pad) of the system-on-chip, and the output end of the receiver routing controller 110 is connected to the receiver controller 120. The input end of the transmitter routing controller 130 is connected to the transmitter controller 140, and the output end of the transmitter routing controller 130 is connected to the output pin (TX Pad) of the system-on-chip.
[0032] Specifically, both the input pin and the output pin are connected to at least one universal asynchronous receiver / transmitter (UART) in the system-on-chip. The receiving-end routing controller 110 is configured to route the data received from the input pin to the receiving-end controller 120 of the target UART. The transmitting-end routing controller 130 is configured to route the data received from the transmitting-end controller 140 to the output pin connected to the target UART. The target UART is any one of the at least one UARTs.
[0033] That is, a receiving-end routing controller 110 is provided between the input pin and the receiving-end controller 120. Through the receiving-end routing controller 110, the data received by the input pin can be routed to different receiving-end controllers 120, so that one input pin can be connected to the receiving-end controllers 120 of at least one UART, without the need for one input pin to correspond to one receiving-end controller 120. A transmitting-end routing controller 130 is provided between the output pin and the transmitting-end controller 140. Through the transmitting-end routing controller 130, the data of the transmitting-end controller 140 can be routed to different output pins, so that the output pins can also be multiplexed, without the need for one output pin to correspond to one transmitting-end controller 140.
[0034] For example, the system-on-chip may include three UARTs, respectively referred to as the first UART, the second UART, and the third UART. The system-on-chip may include two input pins and two output pins, respectively referred to as the first input pin, the second input pin, the first output pin, and the second output pin. If the UART is the UART provided by this application, the receiving-end controllers of the first UART and the second UART can share the first input pin, and the transmitting-end controllers of the first UART and the third UART can share the first output pin.
[0035] Among them, the receiving-end controller of the third UART can also share the first input pin and can also use the second input pin alone. The transmitting-end controller of the second UART can also share the first output pin and can also use the second output pin alone. Moreover, the above is only an example and is not limited thereto.
[0036] The universal asynchronous transceiver provided by this application can forward data by adding a receiving-end routing controller and a transmitting-end routing controller, so that the receiving-end controller does not have to correspond one by one with the input pins and the transmitting-end controller does not have to correspond one by one with the output pins. As a result, the number of pin pads corresponding to the universal asynchronous transceiver in the system-on-chip can be reduced, the chip area and packaging size can be reduced, the chip cost can be lowered, the use of the universal asynchronous transceiver by software and hardware can be improved, and at the same time, the design layout of the system-on-chip can be reduced.
[0037] Further, in some embodiments, as Figure 2 shown, the universal asynchronous transceiver further includes a system interface routing controller 150, and the system interface routing controller 150 is used to perform a loopback self-test to determine whether the universal asynchronous transceiver is normal.
[0038] The loopback self-test can verify whether the most basic sending and receiving functions of the UART are normal. When there are problems in UART communication, through the loopback self-test, internal faults can be located, interference can be quickly eliminated, and test costs and time can be saved.
[0039] Specifically, the loopback self-test can include an external loopback test and an internal loopback test. The external loopback test is mainly used to test whether the functions of the UART itself during interaction with the external environment are normal, and verify whether the UART can correctly send and receive data during actual physical connection and signal transmission processes; the internal loopback test is mainly used to test the integrity and correctness of the internal path of the UART itself, and can check the internal data processing flow of the UART, including whether functions such as data encoding, decoding, and synchronization work properly.
[0040] During the external loopback test and the internal loopback test, the connection relationships among the receiving-end routing controller 110, the receiving-end controller 120, the transmitting-end routing controller 130, the transmitting-end controller 140, and the system interface routing controller 150 in the universal asynchronous transceiver will change. The external loopback test process and the internal loopback test process will be described in detail below with reference to the accompanying drawings.
[0041] As Figure 3 shown, when the system interface routing controller 150 receives an external loopback indication sent by the main controller in the system-on-chip, it connects the bus interface of the system-on-chip and controls the input end of the receiving-end routing controller 110 to be connected to the transmitting-end controller 140. Among them, the external loopback indication is used to indicate that the loopback self-test is an external loopback test, and the external loopback indication can be a special string or number set by the designer, etc.
[0042] Specifically, the transmitting - end controller 140 is configured to, after receiving data from the system interface routing controller, route the data to the receiving - end controller 120 through the receiving - end routing controller 110, and route the data to the output pins through the transmitting - end routing controller 130.
[0043] In this embodiment, the data sent by the UART will pass through an external physical line (connected to the outside through the output pins), leave the system - on - chip, and then return after being transmitted in the external environment.
[0044] As Figure 4 shown, when the system interface routing controller 150 receives an internal loop - back indication sent by the main controller in the system - on - chip, it connects to the receiving - end controller 120. Among them, the internal loop - back indication is used to indicate that the loop - back self - test is an internal loop - back test. The internal loop - back indication can also be a special string or number set by the designer, etc.
[0045] Specifically, the receiving - end controller 120 receives data from the input pins through the receiving - end routing controller 110. The transmitting - end controller 140 receives data from the receiving - end controller 120 through the system interface routing controller 150. The transmitting - end controller 140 also routes the data to the output pins through the transmitting - end routing controller 130.
[0046] In this embodiment, the system interface routing controller 150 can route the data of the receiving - end controller 120 to the transmitting - end controller 140, and the data circulates inside the UART without passing through the external physical line.
[0047] This application also provides a system - on - chip. As Figure 5 shown, the system - on - chip includes at least one input pin, at least one output pin, and multiple universal asynchronous receivers / transmitters provided in any of the above embodiments.
[0048] Among them, the input end of the receiving - end routing controller in the universal asynchronous receiver / transmitter is connected to the first input pin, and the output end of the transmitting - end routing controller in the universal asynchronous receiver / transmitter is connected to the first output pin. The first input pin is any one of the at least one input pins, and the first output pin is any one of the at least one output pins. Figure 5 Taking the system - on - chip including two input pins, two output pins, and two universal asynchronous receivers / transmitters as an example, but not limited thereto.
[0049] Specifically, when performing data transmission, the receiving - end routing controller can route the data received by any one of the input pins to the corresponding receiving - end controller, and the transmitting - end routing controller can also route the data in the transmitting - end controller to any one of the output pins.
[0050] In some embodiments, asFigure 6 As shown, the input ends of the receive - end routing controllers in multiple universal asynchronous receiver - transmitters are connected to the same input pin, and the output ends of the transmit - end routing controllers in multiple universal asynchronous receiver - transmitters are connected to the same output pin.
[0051] That is to say, multiple universal asynchronous receiver - transmitters in the system - on - a - chip of this embodiment can share a set of IO pins (one input pin and one output pin), reducing the number of pads.
[0052] Optionally, the receive - end routing controller 110 of the first universal asynchronous receiver - transmitter can be connected to the input pin corresponding to the first universal asynchronous receiver - transmitter, the input pin corresponding to the second universal asynchronous receiver - transmitter, and / or the transmit - end routing controller corresponding to the second universal asynchronous receiver - transmitter to indirectly connect to the output pin corresponding to the second universal asynchronous receiver - transmitter. Here, the first universal asynchronous receiver - transmitter is any one of the multiple universal asynchronous receiver - transmitters, and the second universal asynchronous receiver - transmitter is any one of the multiple universal asynchronous receiver - transmitters except the first universal asynchronous receiver - transmitter.
[0053] That is, the input of the receive - end routing controller 110 can include the input pin of its own universal asynchronous receiver - transmitter, the input pins of other universal asynchronous receiver - transmitters, and / or the output pins of other universal asynchronous receiver - transmitters. Among them, the output of the receive - end routing controller 110 is connected to the receive - end controller 120.
[0054] Optionally, the transmit - end routing controller 130 of the first universal asynchronous receiver - transmitter can be connected to the output pin corresponding to the first universal asynchronous receiver - transmitter, the output pins corresponding to the second universal asynchronous receiver - transmitter, and / or the receive - end routing controller corresponding to the second universal asynchronous receiver - transmitter to indirectly connect to the input pin corresponding to the second universal asynchronous receiver - transmitter.
[0055] That is, the output of the transmit - end routing controller 130 can be the output pin of its own universal asynchronous receiver - transmitter, the output pins of other universal asynchronous receiver - transmitters, and / or the input pins of other universal asynchronous receiver - transmitters. Among them, the input of the transmit - end routing controller 130 is connected to the transmit - end controller 140.
[0056] Optionally, the input of the system - interface routing controller 150 of the first universal asynchronous receiver - transmitter can be connected to the bus interface corresponding to the main controller of the system - on - a - chip and / or the receive - end controller 120, and the output of the system - interface routing controller 150 of the first universal asynchronous receiver - transmitter can be connected to the transmit - end controller 140.
[0057] Exemplarily, the system-on-chip further includes a main controller (not shown in the figure), and the main controller can determine the first input pin and the first output pin according to the configuration information. Wherein, the configuration information includes the indication information of the input of the receive-end routing controller 110 and the indication information of the output of the transmit-end routing controller 130. The configuration information can be determined by the designer and stored in the main controller in advance.
[0058] When the system-on-chip is initialized, the first input pin and the first output pin of the universal asynchronous receiver / transmitter can be determined according to the configuration information, and then the receive-end routing controller 110 and the transmit-end routing controller 130 can be configured.
[0059] Specifically, if the configuration information indicates that the first input pin is the input pin of the first universal asynchronous receiver / transmitter (its own universal asynchronous receiver / transmitter), then select to connect the input pin of its own universal asynchronous receiver / transmitter and the receive-end routing controller 110 of its own universal asynchronous receiver / transmitter; if the configuration information indicates that the first input pin is the input pin corresponding to the second universal asynchronous receiver / transmitter (other universal asynchronous receiver / transmitter), then select to connect the input pin of the other universal asynchronous receiver / transmitter and the receive-end routing controller 110 of its own universal asynchronous receiver / transmitter. In this case, the input pin of its own universal asynchronous receiver / transmitter can be used as the input of the receive-end routing controller of the other universal asynchronous receiver / transmitter; if the configuration information indicates that the first input pin is the output pin of the other universal asynchronous receiver / transmitter, then select to connect the receive-end routing controller 110 of its own universal asynchronous receiver / transmitter and the output pin of the other universal asynchronous receiver / transmitter, and use the output of the other universal asynchronous receiver / transmitter as the input of its own universal asynchronous receiver / transmitter. This case is used for loopback self-testing.
[0060] If the configuration information indicates that the first output pin is the output pin of the first universal asynchronous receiver / transmitter (its own universal asynchronous receiver / transmitter), then select to connect the output pin of its own universal asynchronous receiver / transmitter and the transmit-end routing controller 130 of its own universal asynchronous receiver / transmitter; if the configuration information indicates that the first output pin is the output pin corresponding to the second universal asynchronous receiver / transmitter (other universal asynchronous receiver / transmitter), then select to connect the output pin of the other universal asynchronous receiver / transmitter and the transmit-end routing controller 130 of its own universal asynchronous receiver / transmitter. In this case, the output pin of its own universal asynchronous receiver / transmitter can be used as the output of the transmit-end routing controller of the other universal asynchronous receiver / transmitter; if the configuration information indicates that the first output pin is the input pin of the other universal asynchronous receiver / transmitter, then select to connect the transmit-end routing controller 130 of its own universal asynchronous receiver / transmitter and the input pin of the other universal asynchronous receiver / transmitter, and use the input of the other universal asynchronous receiver / transmitter as the output of its own universal asynchronous receiver / transmitter. This case is used for loopback self-testing.
[0061] Exemplarily, the configuration information further includes indication information of the input of the system interface routing controller 150. If the configuration information indicates that the input of the system interface routing controller 150 is a bus interface, then the system interface routing controller 150 and the bus interface are selected to be connected. If the configuration information indicates that the input of the system interface routing controller 150 is the receiving end controller 120, then the system interface routing controller 150 of its own universal asynchronous receiver / transmitter and the receiving end controller 120 of its own universal asynchronous receiver / transmitter are selected to be connected.
[0062] In some embodiments, both the receiving end controller and the transmitting end controller of the universal asynchronous receiver / transmitter are configured with address information.
[0063] Among them, after receiving a data frame containing the first address information, the receiving end routing controller 110 is used to route the data frame to the target receiving end controller according to the first address information, and the target receiving end controller transmits the received data frame to the main controller. After receiving a data frame containing the second address information, the transmitting end controller 140 is used to send the data frame containing the second address information to the transmitting end routing controller 130, and the transmitting end routing controller is used to route the data frame to the target output pin according to the second address information.
[0064] Specifically, before the system-on-chip receives data from a first electronic device (such as a mobile phone, a tablet computer, or a server host, etc.), the main controller of the system-on-chip sets the communication parameters of the UART (such as serial port baud rate, data bit width, parity bit, stop bit, etc.) to ensure consistency with the communication parameters of the first electronic device. Then, the main controller enables the UART receiving function, and the receiving end routing controller 110 of the UART detects the level change of the input pin and receives a data frame containing the first address information sent by the first electronic device to the system-on-chip. Among them, the first address information includes the address information of the first electronic device.
[0065] After the receiving end routing controller 110 of the UART receives a data frame containing the first address information, it searches for and determines the receiving end controller (i.e., the target receiving end controller) that matches the first address information, and then routes the data frame containing the first address information to the target receiving end controller. After the target receiving end controller receives the data frame, it converts the received serial data into parallel data and stores it in the received data buffer register, and the main controller obtains the received data frame by reading the received data buffer register.
[0066] Exemplarily, if the address information of the first electronic device included in the first address information is the same as the address information of the receiving end controller, it is considered that the receiving end controller matches the first address information.
[0067] Before the system - on - chip (SoC) sends data to a second electronic device (such as a mobile phone, a tablet computer, or a server host, etc.), the main controller of the SoC sets the communication parameters of the UART (such as serial port baud rate, data bit width, parity bit, stop bit, etc.) to ensure consistency with the communication parameters of the second electronic device. Then, the main controller enables the UART transmission function. The main controller is also used to determine the address information of the second electronic device and the data to be sent, form a data frame containing the second address information, and write the data frame containing the second address information into the transmit data buffer register. The transmit - side controller obtains the data frame containing the second address information from the transmit data buffer register and processes the data frame containing the second address information to convert the data frame from parallel data to serial data.
[0068] After that, the transmit - side controller sends the processed data frame containing the second address information to the transmit - side routing controller. The transmit - side routing controller searches and determines the output pin (i.e., the target output pin) controlled by the transmit - side that matches the second address information. Then, the data frame is routed to the target output pin, and the data frame is sent to the second electronic device.
[0069] In this embodiment, both the receive - side controller and the transmit - side controller of the universal asynchronous receiver - transmitter (UART) are configured with address information, which can facilitate the receive - side routing controller to quickly determine the target receive - side controller and the transmit - side routing controller to quickly determine the target output pin, thus improving the data transmission efficiency.
[0070] Exemplarily, the first electronic device and the second electronic device can be the same or different.
[0071] It should be understood that the UART is usually integrated on other communication interfaces. When UART communication is used between an electronic device and an SoC system, since there is no reference clock signal, both communication parties must agree on communication parameters such as serial port baud rate, data bit width, parity bit, stop bit, etc., so as to communicate at the same rate.
[0072] The serial port baud rate is used to measure the data transmission rate, indicating the number of binary bits transmitted per second, and the unit is Baud. For example, a serial port baud rate of 9600 bps means that 9600 binary bits can be transmitted per second. Both communication parties must set the same baud rate to ensure that data can be correctly transmitted and received. If the baud rates of the sender and the receiver are inconsistent, it will cause data reception errors because the receiver cannot parse the received signal at the correct time interval.
[0073] The data bit width refers to the number of bits of valid data actually transmitted in each frame of data. Common data bit widths are 5 bits, 6 bits, 7 bits, and 8 bits. The data bit width determines the amount of information that can be carried in a single transmission. For example, when the data bit width is 8 bits, one byte of data can be transmitted, which can represent more characters and data types.
[0074] The parity bit is a mechanism used to detect whether errors occur during data transmission. The parity bit is an additional binary bit added after the data bits and is divided into two methods: odd parity and even parity. When sending data with odd parity, the sender calculates the number of "1"s in the data bits. If the number of "1"s is even, the parity bit is set to "1" so that the total number of "1"s in the entire data frame including the parity bit is odd; if the number of "1"s is odd, the parity bit is set to "0". Even parity is the opposite of odd parity. The sender ensures that the total number of "1"s in the entire data frame including the parity bit is even.
[0075] After receiving the data, the receiver calculates the number of "1"s in the received data bits in the same parity check method and compares it with the received parity bit. If they do not match, it indicates that an error may have occurred during data transmission. It should be noted that parity checking can only detect errors in an odd number of bits and cannot detect errors in an even number of bits.
[0076] The stop bit is one or more binary bits added at the end of each frame of data to indicate the end of a frame of data. Common numbers of stop bits are 1 bit, 1.5 bits, and 2 bits. The main function of the stop bit is to provide a time interval for the receiver so that it can correctly identify the end of a frame of data and be ready to receive the next frame of data. A longer stop bit can provide more ample time for data processing and synchronization.
[0077] The above has introduced in detail a universal asynchronous transceiver and a system-on-chip provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be pointed out that for those of ordinary skill in the art of this technology, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A universal asynchronous receiver / transmitter, characterized in that, The general asynchronous transceiver includes a receive - end routing controller, a receive - end controller, a transmit - end routing controller, and a transmit - end controller; The input end of the receive - end routing controller is connected to the input pin of the system - on - chip, and the output end of the receive - end routing controller is connected to the receive - end controller; The input end of the transmit - end routing controller is connected to the transmit - end controller, and the output end of the transmit - end routing controller is connected to the output pin of the system - on - chip; Both the input pin and the output pin are connected to at least one general asynchronous transceiver. The receive - end routing controller is used to route the data received from the input pin to the receive - end controller of the target general asynchronous transceiver, and the transmit - end routing controller is used to route the data received from the transmit - end controller to the output pin connected to the target general asynchronous transceiver. The target general asynchronous transceiver is any one of the at least one general asynchronous transceiver.
2. The universal asynchronous receiver / transmitter according to claim 1, wherein The general asynchronous transceiver further includes a system interface routing controller, and the system interface routing controller is used to perform a loop - back self - test to determine whether the general asynchronous transceiver is normal.
3. The universal asynchronous receiver / transmitter according to claim 2, wherein When the system interface routing controller receives an external loop - back indication sent by the main controller in the system - on - chip, it connects to the bus interface of the system - on - chip and controls the input end of the receive - end routing controller to be connected to the transmit - end controller; The transmit - end controller, after receiving the data from the system interface routing controller, routes the data to the receive - end controller through the receive - end routing controller and routes the data to the output pin through the transmit - end routing controller.
4. The universal asynchronous receiver / transmitter according to claim 2, wherein When the system interface routing controller receives an internal loop - back indication sent by the main controller in the system - on - chip, it connects to the receive - end controller; The receive - end controller receives data from the input pin through the receive - end routing controller. The transmit - end controller receives data from the receive - end controller through the system interface routing controller, and the transmit - end controller also routes the data to the output pin through the transmit - end routing controller.
5. A system on chip, characterized in that, The system - on - chip includes at least one input pin, at least one output pin, and multiple general asynchronous transceivers as described in any one of claims 1 to 4; The input end of the receive - end routing controller in the general asynchronous transceiver is connected to the first input pin, and the output end of the transmit - end routing controller in the general asynchronous transceiver is connected to the first output pin. The first input pin is any one of the at least one input pin, and the first output pin is any one of the at least one output pin.
6. The system on chip according to claim 5, characterized in that The input ends of the receive - end routing controllers in multiple general asynchronous transceivers are connected to the same input pin, and the output ends of the transmit - end routing controllers in multiple general asynchronous transceivers are connected to the same output pin.
7. The system on chip according to claim 5, wherein The system - on - chip further includes a main controller, and the main controller determines the first input pin and the first output pin according to the configuration information.
8. The system on chip according to claim 7, wherein Both the receive - end controller and the transmit - end controller of the general asynchronous transceiver are configured with address information; After receiving a data frame containing the first address information, the receiving - end routing controller is configured to route the data frame to the target receiving - end controller according to the first address information, and the target receiving - end controller transmits the received data frame to the main controller; After receiving a data frame containing the second address information, the sending - end controller is configured to send the data frame containing the second address information to the sending - end routing controller, and the sending - end routing controller is configured to route the data frame to the target output pin according to the second address information.
9. The system on chip according to any one of claims 5 to 8, characterized in that, The receiving - end routing controller of the first universal asynchronous transceiver is connected to the input pin corresponding to the first universal asynchronous transceiver, the input pin corresponding to the second universal asynchronous transceiver, and / or the sending - end routing controller corresponding to the second universal asynchronous transceiver to indirectly connect to the output pin corresponding to the second universal asynchronous transceiver, where the first universal asynchronous transceiver is any one of multiple universal asynchronous transceivers, and the second universal asynchronous transceiver is any one of the multiple universal asynchronous transceivers except the first universal asynchronous transceiver.
10. The system on chip according to claim 9, wherein The sending - end routing controller of the first universal asynchronous transceiver is connected to the output pin corresponding to the first universal asynchronous transceiver, the output pin corresponding to the second universal asynchronous transceiver, and / or the receiving - end routing controller corresponding to the second universal asynchronous transceiver to indirectly connect to the input pin corresponding to the second universal asynchronous transceiver.