Storage and calculation integrated chip and storage device

Abstract

The invention discloses a storage and calculation integrated chip and a storage device. The chip comprises a Flash storage and calculation integrated unit, the Flash storage and calculation integrated unit comprises a floating gate transistor array module, a word line reading driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module and a negative voltage charge pump module; the main control module is connected with the Flash storage and calculation integrated unit; and the floating gate transistor array module is connected with the word line reading driving module, the word line programming and erasing driving module, the bit line and source line driving module and the substrate potential control module. According to the invention, the Flash storage and calculation integrated unit is used for storing data and performing calculation, so that the data transmission distance is effectively shortened, the calculation delay can be reduced, the calculation efficiency of the chip is greatly improved, and the data can be stored during power failure.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly relates to a memory - in - computing chip and a storage device. Background Art

[0002] In today's information age, data processing has become the core requirement in all walks of life. From real - time image processing on smart phones, large - scale data analysis in data centers to complex decision - making systems for autonomous driving, there is an urgent need for high - performance and low - power chips.

[0003] Currently, the mainstream chip architectures in the market are still mainly based on the traditional von Neumann architecture, that is, the storage module and the computing module are separated. This chip architecture is convenient for designing the storage module and the computing module, and is also convenient for large - scale production on the production line.

[0004] However, with mainstream chips, data needs to be frequently transmitted between the storage module and the computing module, resulting in a high computing latency. With the emergence of computing - intensive application scenarios such as artificial intelligence and big data analysis, under the traditional von Neumann architecture, the bottleneck of computing efficiency caused by the separation of the chip computing module and the storage module is becoming increasingly apparent. Although the chip manufacturing process has been continuously improved, such as the application of 7 - nanometer and 5 - nanometer technologies, which have improved the chip performance to a certain extent, it has not fundamentally solved the computing efficiency problem caused by the separation of the storage module and the computing module. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the present application provides a memory - in - computing chip and a storage device. The Flash memory - in - computing unit includes a floating - gate transistor array module composed of a plurality of floating - gate transistors connected, a word - line reading and driving module, a word - line programming and erasing driving module, a word - line control module, a bit - line and source - line driving module, a bit - line and source - line control module, a substrate potential control module, and a negative - voltage charge pump module, enabling the Flash memory - in - computing unit to store data and perform calculations, effectively shortening the data transmission distance, reducing the computing latency, thus greatly improving the computing efficiency of the chip, and being able to save data when power is off.

[0006] To solve the above problems, the present invention provides the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a memory - in - computing chip, including: a Flash memory - in - computing unit, where the Flash memory - in - computing unit is used to store data and perform calculations;

[0008] The Flash memory and computing integrated unit includes a floating gate transistor array module composed of multiple floating gate transistors connected together, a word line reading and driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module, and a negative voltage charge pump module;

[0009] A main control module, which is used to control the operation of the Flash memory and computing integrated unit to execute storage operations and computing operations, and the main control module is connected to the Flash memory and computing integrated unit;

[0010] The floating gate transistor array module is connected to the word line reading and driving module, the word line programming and erasing driving module, the bit line and source line driving module, and the substrate potential control module;

[0011] The word line control module is connected to the word line reading and driving module and the word line programming and erasing driving module; the bit line and source line control module is connected to the bit line and source line driving module, and the negative voltage charge pump module is connected to the word line programming and erasing driving module;

[0012] The floating gate transistor array module is used to implement the functions of storing data and computing;

[0013] The word line control module is used to control the word line reading and driving module and the word line programming and erasing driving module to output the operating voltages required for the current working mode to the floating gate transistor array module according to the control signals of the main control module, and the working modes include a reading mode, a programming mode, and an erasing mode;

[0014] The word line reading and driving module is used to output the operating voltage in the reading mode to the word lines of the floating gate transistor array module according to the control signals of the word line control module;

[0015] The word line programming and erasing driving module is used to output the operating voltage in the programming mode or the erasing mode to the word lines of the floating gate transistor array module according to the control signals of the word line control module;

[0016] The bit line and source line control module is used to control the bit line and source line driving module to output corresponding operating voltages to the bit lines and source lines of the floating gate transistor array module according to the control signals of the main control module, so that the floating gate transistor array module is in the target working mode;

[0017] The substrate potential control module is used to control the substrate potential of the floating gate transistors in the floating gate transistor array module;

[0018] The negative voltage charge pump module is used to provide the negative voltage required in the erasing mode for the word line programming and erasing driving module.

[0019] In some embodiments, the floating-gate transistor array module is a NAND Flash array module. The NAND Flash array module includes floating-gate transistors arranged in A rows and B columns. Every B floating-gate transistors are connected in series to form a row. The source of the first floating-gate transistor in each row of floating-gate transistors is connected to a source line to form a column of ground selection transistors. The drain of the last floating-gate transistor in each row of floating-gate transistors is connected to the bit line corresponding to the row. The gates of all the floating-gate transistors in each column of floating-gate transistors are connected to a word line. Here, both A and B are positive integers.

[0020] In some embodiments, the floating-gate transistor array module is a NOR Flash array module. The sources of all the floating-gate transistors in the NOR Flash array module are connected to a source line, the drains are connected to a bit line, and the gates of each column of floating-gate transistors are connected to a word line.

[0021] In some embodiments, the word line programming and erasing driving module includes a first level conversion circuit module, a voltage clamping module, and a high-voltage transmission module. The first level conversion circuit module is connected to the voltage clamping module, and the voltage clamping module is connected to the high-voltage transmission module.

[0022] In some embodiments, the word line reading driving module includes a second level conversion circuit module, a signal driving module, and a transmission gate module. The second level conversion circuit module is connected to the signal driving module, and the signal driving module is connected to the transmission gate module;

[0023] The signal driving module includes a first field-effect transistor and a second field-effect transistor. The source of the first field-effect transistor is connected to an analog reading voltage, the gate is connected to the second level conversion circuit module, and the drain is connected to the drain of the second field-effect transistor. The source of the second field-effect transistor is connected to the reference ground voltage of the analog reading voltage, and the gate is connected to the second level conversion circuit module;

[0024] The drains of the first field-effect transistor and the second field-effect transistor are both connected to the transmission gate module.

[0025] In some embodiments, the bit line and source line driving module includes a first-stage cross-coupled structure module, a second-stage cross-coupled structure module, a state transmission stage module, and a blocking control module. The first-stage cross-coupled structure module is connected to the second-stage cross-coupled structure module, the second-stage cross-coupled structure module is connected to the state transmission stage module, and the state transmission stage module is connected to the blocking control module.

[0026] In some embodiments, the bit line and source line control module includes a positive high-voltage level conversion circuit, a reference ground voltage conversion circuit, a negative high-voltage level conversion circuit, and a strobe circuit. The positive high-voltage level conversion circuit, the reference ground voltage conversion circuit, and the negative high-voltage level conversion circuit are all connected to the strobe circuit.

[0027] In some embodiments, the negative voltage charge pump module includes a four-phase clock generation circuit, a charge pump circuit, an operational amplifier, an oscillator, a logic operation module, a buffer, and a feedback voltage stabilization circuit. The four-phase clock generation circuit is connected to the charge pump circuit. The operational amplifier is connected to the buffer through a resistor and is also connected to the reference ground voltage. The outputs of the operational amplifier and the oscillator are inputs to the logic operation module. The four-phase clock generation circuit receives the output signal of the logic operation module and outputs a clock signal to the charge pump circuit. The charge pump circuit is connected to the feedback voltage stabilization circuit.

[0028] In some embodiments, the word line control module includes a plurality of cascaded flip-flops and a plurality of cascaded latches. Each flip-flop is connected to one latch.

[0029] In a second aspect, an embodiment of the present application provides a storage device, which includes the memory-computation integrated chip as described in the first aspect.

[0030] The present application provides a memory-computation integrated chip and a storage device. The Flash memory-computation integrated unit of the present application includes a floating gate transistor array module composed of a plurality of floating gate transistors connected, a word line read driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module, and a negative voltage charge pump module, enabling the Flash memory-computation integrated unit to store data and perform calculations, effectively shortening the data transmission distance, reducing the calculation delay, thus greatly improving the calculation efficiency of the chip, and being able to save data even when power is off. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of the memory-computation integrated chip provided by an embodiment of the present application.

[0032] Figure 2 is a schematic structural diagram of the first embodiment of the floating gate transistor array module provided by an embodiment of the present application.

[0033] Figure 3 is a schematic structural diagram of the second embodiment of the floating gate transistor array module provided by an embodiment of the present application.

[0034] Figure 4It is a schematic structural diagram of a word line programming and erasing driving module provided by an embodiment of the present application.

[0035] Figure 5 It is a schematic structural diagram of a word line reading driving module provided by an embodiment of the present application.

[0036] Figure 6 It is a schematic structural diagram of a word line control module provided by an embodiment of the present application.

[0037] Figure 7 It is a schematic structural diagram of a bit line and source line driving module provided by an embodiment of the present application.

[0038] Figure 8 It is a schematic structural diagram of a bit line and source line control module provided by an embodiment of the present application.

[0039] Figure 9 It is a schematic structural diagram of a negative voltage charge pump module provided by an embodiment of the present application.

[0040] Figure 10 It is a schematic structural diagram of a storage device provided by an embodiment of the present application. Specific Embodiments

[0041] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0042] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0043] The present application provides a memory-computation integrated chip and a storage device. The Flash memory-computation integrated unit includes a floating gate transistor array module, a word line reading driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module, and a negative voltage charge pump module composed of a plurality of floating gate transistors connected. The Flash memory-computation integrated unit can store data and perform calculations, effectively shortening the data transmission distance, reducing the calculation delay, thus greatly improving the calculation efficiency of the chip, and being able to save data even when power is off.

[0044] The computing-in-memory chip provided by the present application will be specifically described below in conjunction with the accompanying drawings.

[0045] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the computing-in-memory chip provided by an embodiment of the present application. As Figure 1 shown, in some embodiments, the computing-in-memory chip 1 includes a Flash computing-in-memory unit 10 and a main control module 20. The Flash computing-in-memory unit 10 is used to store data and perform calculations. The main control module 20 is used to control the operation of the Flash computing-in-memory unit 10 to execute storage operations and calculation operations. The main control module 20 is connected to the Flash computing-in-memory unit 10.

[0046] In some embodiments, the Flash computing-in-memory unit 10 includes a floating-gate transistor array module 11 composed of a plurality of floating-gate transistors connected, a word-line reading and driving module 12, a word-line programming and erasing driving module 13, a word-line control module 14, a bit-line and source-line driving module 15, a bit-line and source-line control module 16, a substrate potential control module 17, and a negative voltage charge pump module 18. The floating-gate transistor array module 11 is connected to the word-line reading and driving module 12, the word-line programming and erasing driving module 13, the bit-line and source-line driving module 15, and the substrate potential control module 17. The word-line control module 14 is connected to the word-line reading and driving module 12 and the word-line programming and erasing driving module 13. The bit-line and source-line control module 15 is connected to the bit-line and source-line driving module 16. The negative voltage charge pump module 18 is connected to the word-line programming and erasing driving module 13. Among them, the floating-gate transistor array module 11 is used to implement the functions of storing data and performing calculations. The word-line control module 14 is used to control the word-line reading and driving module 12 and the word-line programming and erasing driving module 13 to output the operating voltages required for the current working mode to the floating-gate transistor array module 11 according to the control signals of the main control module 20. The working modes include a reading mode, a programming mode, and an erasing mode.

[0047] In some embodiments, the main control module 20 is connected to the word-line control module 14, the bit-line and source-line control module 16, and the substrate potential control module 17 in the Flash computing-in-memory unit 10 to control the Flash computing-in-memory unit 10 to store data and perform calculations.

[0048] In some embodiments, the floating-gate transistor array module 11 is used to store the weight parameter matrix of the artificial intelligence model and perform calculations on the weight parameter matrix.

[0049] In some embodiments, the word line read driving module 12 is configured to output an operating voltage in a read mode to the word lines of the floating gate transistor array module 11 according to the control signal of the word line control module 14. The word line programming and erasing driving module 13 is configured to output an operating voltage in a programming mode or an erasing mode to the word lines of the floating gate transistor array module 11 according to the control signal of the word line control module 14. The bit line and source line control module 16 is configured to control the bit line and source line driving module 15 to output corresponding operating voltages to the bit lines and source lines of the floating gate transistor array module 11 according to the control signal of the main control module 20, so that the floating gate transistor array module 11 is in a target operating mode. The substrate potential control module 17 is configured to control the substrate potential of the floating gate transistors in the floating gate transistor array module 11. The negative voltage charge pump module 18 is configured to provide a negative voltage required in the erasing mode for the word line programming and erasing driving module 13.

[0050] In some embodiments, the floating gate transistor array module 11 is a NAND Flash array module. The NAND Flash array module includes A rows and B columns of floating gate transistors, and every B floating gate transistors are connected in series as a row. The source electrodes of the first floating gate transistors in each row of floating gate transistors are all connected to the source line to form a column of ground selection transistors. The drain electrodes of the last floating gate transistors in each row of floating gate transistors are connected to the corresponding bit lines of the row to form a column of bit line selection transistors. The gate electrodes of all the floating gate transistors in each column of floating gate transistors are all connected to a word line. Wherein, both A and B are positive integers.

[0051] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the first embodiment of the floating gate transistor array module provided by the embodiments of the present application. As Figure 2 shown, exemplarily, at this time A is 4 and B is 5. The source electrodes of the first floating gate transistors J in each row of floating gate transistors J are all connected to the source line SL to form a column of ground selection transistors GSL. The drain electrodes of the last floating gate transistors J in each row of floating gate transistors J are connected to the corresponding bit lines of the row to form a column of bit line selection transistors BSL. The ground selection transistors GSL and the bit line selection transistors BSL are used to select the bit lines in the floating gate transistor array module 11. The gate electrodes of all the floating gate transistors J in the second column of floating gate transistors J are all connected to the word line WL3, the gate electrodes of all the floating gate transistors J in the third column of floating gate transistors J are all connected to the word line WL2, and the gate electrodes of all the floating gate transistors J in the fourth column of floating gate transistors J are all connected to the word line WL1. All the floating gate transistors J in the first row of floating gate transistors J are connected in series and connected to the bit line BL1, all the floating gate transistors J in the second row of floating gate transistors J are connected in series and connected to the bit line BL2, all the floating gate transistors J in the third row of floating gate transistors J are connected in series and connected to the bit line BL3, and all the floating gate transistors J in the fourth row of floating gate transistors J are connected in series and connected to the bit line BL4.

[0052] In some embodiments, the floating gate transistor array module 11 is a NOR Flash array module. The sources of all the floating gate transistors in the NOR Flash array module are connected to the source line, the drains are connected to the bit line, and the gates of each column of floating gate transistors are connected to a word line.

[0053] Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the second embodiment of the floating gate transistor array module provided by the embodiments of the present application. As Figure 3 shown, exemplarily, the sources of all the floating gate transistors J in the floating gate transistor array module 11 are connected to the source line. The gates of all the floating gate transistors J in the first column of floating gate transistors J are connected to the word line WL4, the gates of all the floating gate transistors J in the second column of floating gate transistors J are connected to the word line WL3, the gates of all the floating gate transistors J in the third column of floating gate transistors J are connected to the word line WL2, and the gates of all the floating gate transistors J in the fourth column of floating gate transistors J are connected to the word line WL1. The drains of all the floating gate transistors J in the first row of floating gate transistors J are connected to the bit line BL1, the drains of all the floating gate transistors J in the second row of floating gate transistors J are connected to the bit line BL2, the drains of all the floating gate transistors J in the third row of floating gate transistors J are connected to the bit line BL3, and the drains of all the floating gate transistors J in the fourth row of floating gate transistors J are connected to the bit line BL4.

[0054] In some embodiments, the word line programming and erasing driving module 13 is further configured to convert the digital control signal of the word line control module 14 into a word line operating voltage.

[0055] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the word line programming and erasing driving module provided by the embodiments of the present application. As Figure 4 shown, in some embodiments, the word line programming and erasing driving module 13 includes a first level conversion circuit module 131, a voltage clamping module 132, and a high voltage transmission module 133. The first level conversion circuit module 131 is connected to the voltage clamping module 132, and the voltage clamping module 132 is connected to the high voltage transmission module 133. Among them, the first level conversion circuit module 131 is configured to convert the digital control signal into a word line operating voltage, the voltage clamping module 132 is configured to limit the amplitude of the word line operating voltage, and the high voltage transmission module 133 is configured to transmit the processed word line operating voltage WL_OUT to the word line.

[0056] In some embodiments, in the first level conversion circuit module 131, the gate of the field effect transistor NM1 is connected to the gate of the field effect transistor PM4 and is simultaneously used for inputting the first path of digital control signal IN_N. The source of the field effect transistor NM1 is connected to the source of the field effect transistor PM4 and is used for inputting the voltage V LV. The drain of the field effect transistor PM3 is connected to the drain of the field effect transistor NM1 to form a node Q3, the source is connected to the drain of the field effect transistor PM1, and the gate is connected to the source of the field effect transistor PM6 in the voltage clamping module 132 through the node Q2. The source of the field effect transistor PM1 is connected to the source of the field effect transistor PM2 and is connected to the voltage V PHV , the gate is connected to the gate of the field effect transistor PM2 and is connected to the source of the field effect transistor PM3 to form a node Q1. The drain of the field effect transistor PM2 is connected to the gate of the field effect transistor PM3 and is connected to the drain of the field effect transistor NM2 to form a node Q2. The gate of the field effect transistor NM2 is connected to the gate of the field effect transistor PM5 and is simultaneously used to input the second digital control signal IN, and the source is connected to the source of the field effect transistor PM5 and is connected to the voltage V LV . The drain of the field effect transistor NM2 is connected to the drain of the field effect transistor PM2. The drain of the field effect transistor NM3 is connected to the drain of the field effect transistor PM4, the source is connected to the drain of the field effect transistor NM4, and the gate is connected to the drains of the field effect transistor PM5 and the field effect transistor NM5 to form a node Q6. The source of the field effect transistor NM4 is connected to the source of the field effect transistor NM5 and is connected to the voltage V NHV , the gate is connected to the gate of the field effect transistor NM5 and is connected to the source of the field effect transistor NM3 to form a node Q5.

[0057] In some embodiments, the voltage clamping module 132 includes a field effect transistor PM6 and a field effect transistor NM6. The source of the field effect transistor PM6 is connected to the node Q2 in the first level conversion circuit module 131. The source of the field effect transistor NM6 is connected to the gates of the field effect transistor PM4 and the field effect transistor NM3 in the first level conversion circuit module 131 to form a node Q4. The drain of the field effect transistor PM6 is connected to the drain of the field effect transistor NM6. The gate of the field effect transistor PM6 is used to input the voltage -VDD, and the voltage -VDD is the negative power supply voltage. The gate of the field effect transistor NM6 is used to input the voltage 2VDD, and the voltage 2VDD is twice the power supply voltage.

[0058] In some embodiments, the high-voltage transmission module 133 includes a field effect transistor PM7 and a field effect transistor NM7. The gates of the field effect transistor PM7 and the field effect transistor NM7 are connected and are simultaneously connected to the drains of the field effect transistor PM6 and the field effect transistor NM6 to form a node Q7. The source of the field effect transistor PM7 is used to input the voltage V HVPWL , the source of the field effect transistor NM7 is used to input the voltage V HVRSTWL . The drain of the field effect transistor PM7 is connected to the drain of the field effect transistor NM7 and is simultaneously used to output the processed word line operation voltage WL_OUT.

[0059] In some embodiments, field effect transistors NM1, NM2, NM3, NM4, NM5, NM6, and NM7 are all N-type field effect transistors. Field effect transistors PM1, PM2, PM3, PM4, PM5, PM6, and PM7 are all P-type field effect transistors.

[0060] In some embodiments, voltage V PHV , voltage V LV , voltage V NHV , voltage V HVPWL , and voltage V HVRSTWL The combination of voltage values is used to determine whether the working mode of the word line programming and erasing driving module is the programming mode or the erasing mode. The first digital control signal IN_N and the second digital control signal IN are used to determine whether the working state of the word line programming and erasing driving module is the gated state or the off state.

[0061] In some embodiments, the word line control module 14 is used to output voltage V PHV , voltage VLV , voltage V NHV , voltage V HVPWL , voltage V HVRSTWL , the first digital control signal IN_N, and the second digital control signal IN to the word line programming and erasing driving module 13.

[0062] In some embodiments, the first digital control signal IN_N is the inverted signal of the second digital control signal IN. When the voltage value of the second digital control signal IN is the reference ground voltage, the working state of the word line programming and erasing driving module is the off state. When the voltage value of the second digital control signal IN is the power supply voltage, the working state of the word line programming and erasing driving module is the gated state.

[0063] In some embodiments, when the working state of the word line programming and erasing driving module 13 is the gated state, and the voltage values of voltage V PHV and voltage V HVPWL are the first voltage value, and the voltage values of voltage V LV , voltage V NHV , and voltage V HVRSTWL are the reference ground voltage, the word line programming and erasing driving module 13 outputs the operating voltage in the programming mode. When the working state of the word line programming and erasing driving module 13 is the gated state, and the voltage values of voltage V PHV and voltage V LV are the power supply voltage, the voltage values of voltage V NHV and voltage V HVRSTWL are the second voltage, and the voltage value of voltage V HVPWLWhen the voltage value is the reference ground voltage, the word line programming and erasing driving module 13 outputs the operating voltage in the erasing mode. At this time, the voltage domain of the word line programming and erasing driving module 13 includes the reference ground voltage and the negative high voltage domain.

[0064] In some embodiments, when the word line programming and erasing driving module 13 outputs the operating voltage in the programming mode, the NMOS transistor NM1, the PMOS transistor PM3, the PMOS transistor PM1, the PMOS transistor PM2, the NMOS transistor NM2, the PMOS transistor PM6, the PMOS transistor PM7, and the NMOS transistor NM7 are all turned on, and the other MOS transistors are all turned off.

[0065] As described above, the first digital control signal IN_N is the inverted signal of the second digital control signal IN. When the word line programming and erasing driving module 13 outputs the operating voltage in the programming mode, at the initial moment when the second digital control signal IN is at a low level, the voltages of the node Q1 and the node Q2 are at a high level, and the node Q3 is at a low level. At this time, the NMOS transistor NM1 and the PMOS transistor PM2 are turned on, but the NMOS transistor NM2, the PMOS transistor PM1, and the PMOS transistor PM3 are in an off state. Then, the rising edge of the second digital control signal IN turns on the NMOS transistor NM2 and turns off the NMOS transistor NM1 at the same time, causing the parasitic capacitance of the node Q2 to start discharging simultaneously. While the voltage of the node Q2 is decreasing, the PMOS transistor PM3 is gradually turned on. Therefore, the transient current flows through the left branch of the first level conversion circuit module 131 and pulls up the current of the node Q3, and this current is mirrored to the right branch of the first level conversion circuit module 131, resulting in a competition effect between the pull-up current and the pull-down current in the node Q2. However, by increasing the voltage of the node Q3, the PMOS transistor PM1 is gradually turned off and prevents the static current from flowing through the left branch. At this time, the node Q2 will discharge to the ground without the mirror current of the left branch. Since the gate of the PMOS transistor PM6 is connected to the voltage _VDD, the low voltage of the node Q2 is transmitted to the node Q7 through the PMOS transistor PM6. When the voltage of the node Q7 is the reference ground voltage, the PMOS transistor PM7 is turned on, and the voltage V HVPWL is transmitted to the word line.

[0066] In some embodiments, when the word line programming and erasing driving module 13 outputs the operating voltage in the erasing mode, the PMOS transistor PM4, the NMOS transistor NM3, the NMOS transistor NM4, the NMOS transistor NM5, the PMOS transistor PM5, the NMOS transistor NM6, the PMOS transistor PM7, and the NMOS transistor NM7 are all turned on, and the other MOS transistors are all turned off.

[0067] In some embodiments, at the initial moment when the second digital control signal IN is at a low level, the voltages of node Q4 and node Q5 are at a high level, while the voltage of node Q6 is at a low level. At this time, the field effect transistors PM5 and NM3 are turned on, while the field effect transistors PM4, NM4 and NM5 are turned off. Then, the rising edge of the second digital control signal IN turns on the field effect transistor PM4 and turns off the field effect transistor PM5, causing the parasitic capacitances of node Q4 and node Q5 to start discharging simultaneously. During the discharging process, the field effect transistor NM4 will be turned on. In this case, a transient current will flow through the left branch of the first level conversion circuit module 131. This current is mirrored to the right branch of the first level conversion circuit module 131 and raises the voltage of node Q6, thereby gradually turning off the field effect transistor NM3 and preventing a static current from flowing through the left branch of the first level conversion circuit module 131. However, when the gate of the field effect transistor NM6 is connected to the voltage 2VDD, the voltage of node Q4 will be transmitted to node Q7 through the field effect transistor NM6. When the voltage of node Q7 is the power supply voltage, the field effect transistor NM7 is turned on, and V HVRSTWL is transmitted to the word line.

[0068] In the above manner, when the word line programming and erasing driving module outputs the operating voltages in different operating modes, the turned-on field effect transistors are different, and the influence of the previous operating mode on the circuit state of the next operating mode can be avoided when switching the operating modes.

[0069] In some embodiments, the word line reading driving module includes a second level conversion circuit module, a signal driving module and a transmission gate module. The second level conversion circuit module is connected to the signal driving module, and the signal driving module is connected to the transmission gate module. Among them, the second level conversion circuit module is used to convert the digital control signal of the word line control module into an analog reading voltage, and the signal driving module is used to drive the analog reading voltage to be transmitted to the word line through the transmission gate module.

[0070] In some embodiments, the signal driving module includes a first field effect transistor and a second field effect transistor. The source of the first field effect transistor is connected to the analog reading voltage, the gate is connected to the second level conversion circuit module, and the drain is connected to the drain of the second field effect transistor. The source of the second field effect transistor is connected to the reference ground voltage of the analog reading voltage, and the gate is connected to the second level conversion circuit module. The drains of the first field effect transistor and the second field effect transistor are both connected to the transmission gate module.

[0071] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the word line reading driving module provided by the embodiment of the present application. As Figure 5 shown, in some embodiments, the word line reading driving module 12 includes a second level conversion circuit module 121, a signal driving module 122 and a transmission gate module 123.

[0072] In some embodiments, the second level conversion circuit module 121 includes an NMOS transistor NM8, a PMOS transistor PM8, a PMOS transistor PM9, a PMOS transistor PM10, and an NMOS transistor NM9. Among them, the gate of the NMOS transistor NM8 is connected to the voltage VDD, the drain is connected to the drain of the PMOS transistor PM8, and the source is connected to the gate of the NMOS transistor NM9 and is connected to the digital control signal INR. The source of the PMOS transistor PM8 is connected to the source of the PMOS transistor PM9 and is connected to the voltage V HVRDWL , the gate is connected to the gate of the PMOS transistor PM9 and is connected to the source of the PMOS transistor PM10, forming a node Q9. The gate of the PMOS transistor PM10 is connected to the gate of the PMOS transistor PM8 and the gate of the NMOS transistor NM8 and forms a node Q8, and the drain is connected to the drain of the NMOS transistor NM9. The drain of the NMOS transistor NM9 is grounded.

[0073] In some embodiments, the signal driving module 122 includes a PMOS transistor PM11 and an NMOS transistor NM10. The gate of the PMOS transistor PM11 is connected to the gate of the NMOS transistor NM10, and is simultaneously connected to the drain of the PMOS transistor PM10 and the drain of the NMOS transistor NM9, forming a node Q10. The drain of the PMOS transistor PM11 is connected to the drain of the NMOS transistor NM10, and is simultaneously connected to the source of the PMOS transistor PM12 and the source of the NMOS transistor NM11, the source of the PMOS transistor PM12 and the source of the NMOS transistor NM11, and forms a node Q11. The source of the PMOS transistor PM11 is connected to the voltage V HVRDWL , the source of the NMOS transistor NM10 is connected to the voltage HVGND. Among them, the first transistor is the PMOS transistor PM11, and the second transistor is the NMOS transistor NM10. The analog read voltage is the voltage V HVRDWL , and the reference ground voltage of the analog read voltage is the voltage HVGND.

[0074] In some embodiments, the transmission gate module 123 includes a PMOS transistor PM12 and an NMOS transistor NM11. The source of the PMOS transistor PM12 is connected to the source of the NMOS transistor NM11, and the drain is connected to the drain of the NMOS transistor NM11 and is used to output the voltage WL_OUT2 simultaneously. The gate of the PMOS transistor PM12 is connected to the signal ctr1, and the gate of the NMOS transistor NM11 is connected to the signal ctr2. The signal ctr1 and the signal ctr2 are a pair of complementary signals.

[0075] In some embodiments, the NMOS transistors NM8, NM9, NM10, and NM11 are all N-type MOS transistors. The PMOS transistors PM8, PM9, PM10, PM11, and PM12 are all P-type MOS transistors.

[0076] In some embodiments, in the word line read driving module 12, for the rising edge of the digital control signal INR, at the initial moment, the digital control signal INR is at a low level, the node Q8 is at a low voltage, while the nodes Q8 and Q10 are at a high voltage. At this time, the field effect transistors NM8 and PM10 are in the conducting state, and the field effect transistors NM9, PM8, and PM9 are in the cut-off state. The rising edge of the digital control signal INR will turn on the field effect transistor NM9 and turn off the field effect transistor NM8 at the same time. The parasitic capacitances of the nodes Q9 and Q10 start to discharge. During the discharging process, the field effect transistor PM9 will conduct, and at this time, a static current will flow through the field effect transistor PM9 and be copied to the left branch of the second level conversion circuit module 121, and the voltage of the node Q8 will be raised. However, the voltage of the node Q8 will gradually turn off the field effect transistor PM10, and finally the node Q10 will stabilize at the reference ground voltage. At this time, since the source of the field effect transistor PM11 is connected to the voltage V HVRDWL , the field effect transistor PM11 conducts, and the voltage V HVRDWL will be transmitted to the node Q11. When the signal ctr2 is at a high level, at least one of the field effect transistors PM12 and NM11 will conduct, so the voltage V HVRDWL will be transmitted to the word line through the transmission gate module 123. At this time, the voltage V HVRDWL , that is, the voltage WL_OUT2, is the analog read voltage.

[0077] In some embodiments, for the falling edge of the digital control signal INR, the field effect transistor NM9 gradually turns off, and the field effect transistor NM8 will conduct to pull down the voltage of the node Q8. When the voltage of the node Q8 drops, the field effect transistor PM10 will gradually conduct, and at this time, a current will flow through the field effect transistor PM9 to pull up the voltage of the node Q10. This current will be copied to the left branch of the second level conversion circuit module 121 and cause a competitive effect between the pull-up current and the pull-down current at the node Q8. Because of the pull-up of the voltages of the nodes Q9 and Q10, the field effect transistor PM9 will turn off, resulting in the pull-up current through the field effect transistor PM8 being negligible. At this time, the voltage of the node Q8 will also discharge to the reference ground voltage, and the voltage of the node Q10 will stabilize at the power supply voltage. When the voltage of the node Q10 is at the power supply voltage, since the source of the field effect transistor PM11 is connected to the voltage V HVRDWL , and the drain of the field effect transistor NM10 is connected to the voltage HVGND, at this time the field effect transistor NM10 conducts, and the voltage HVGND will be transmitted to the node Q11. When the signal ctr2 is at a high level, at least one of the field effect transistors PM12 and NM11 will conduct, so the voltage HVGND will be transmitted to the word line through the transmission gate module 123.

[0078] In some embodiments, the word line control module 14 is configured to input a digital control signal INR, a voltage V HVRDWL and a voltage HVGND to the word line read driving module 12.

[0079] In some embodiments, the word line control module includes a plurality of cascaded flip - flops and a plurality of cascaded latches, and each flip - flop is connected to a latch.

[0080] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of the word line control module provided by an embodiment of the present application. As Figure 6 shown, in some embodiments, the word line control module 14 includes a plurality of cascaded flip - flops 141 and a plurality of cascaded latches 142, and each flip - flop 141 is connected to a latch 142. Among them, the first cascaded flip - flop 141 is configured to access a data signal IN_DATA and a clock signal CLK, and the last cascaded latch 142 is configured to access a signal L_EN. At this time, the word line control module 14 is a digital shift module, which can greatly reduce the number of control signals required.

[0081] It can be understood that the flip - flop 141 and the latch 142 can also access or output signal types and quantities not limited to Figure 6 those shown.

[0082] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of the bit line and source line driving module provided by an embodiment of the present application. As Figure 7 shown, in some embodiments, the bit line and source line driving module 15 includes a first - stage cross - coupled structure module 151, a second - stage cross - coupled structure module 152, a state transfer - level module 153, and a blocking control module 154. The first - stage cross - coupled structure module 151 is connected to the second - stage cross - coupled structure module 152, the second - stage cross - coupled structure module 152 is connected to the state transfer - level module 153, and the state transfer - level module 153 is connected to the blocking control module 154. Among them, the first - stage cross - coupled structure module 151 is configured to convert the control signal of the bit line and source line control module 16 into a first intermediate voltage and a reference ground voltage. The second - stage cross - coupled structure module 152 is configured to convert the voltage domain of the first intermediate voltage and the reference ground voltage into the voltage domain of the first intermediate voltage and the second intermediate voltage. The state transfer - level module 153 is configured to access the output voltage of the second - stage cross - coupled structure module 152, a first driving voltage, and a second driving voltage, and transfer the first driving voltage or the second driving voltage to the bit line terminal BL_OUT. The blocking control module 154 is configured to block the connection between the bit line terminal BL_OUT and the bit line path in the read mode, and ground the source line terminal SL_OUT.

[0083] In some embodiments, the first-stage cross-coupled structure module 151 includes field effect transistors PM13, PM14, NM12, and NM13. The gate of field effect transistor NM12 is connected to the control signal INB and is connected to the source of field effect transistor NM13. The source of field effect transistor NM12 is connected to the reference ground voltage GND, and the drain is connected to the drain of field effect transistor PM13. The source of field effect transistor PM13 is connected to the source of field effect transistor PM14 and is simultaneously connected to voltage V PUSB , and the gate of field effect transistor PM13 is connected to the drain of field effect transistor PM14. The gate of field effect transistor PM14 is connected to the drain of field effect transistor PM13, and the drain is connected to the drain of field effect transistor NM13. The gate of field effect transistor NM13 is connected to voltage VDD.

[0084] In some embodiments, the second-stage cross-coupled structure module 152 includes field effect transistors PM15, PM16, NM14, and NM15. The source of field effect transistor NM14 and the source of field effect transistor NM15 are connected and are simultaneously connected to voltage V NUSB . The drain of field effect transistor NM14 is connected to the drain of field effect transistor PM15, and the gate is connected to the drain of field effect transistor NM15 and the drain of field effect transistor PM16. The gate of field effect transistor NM15 is connected to the drain of field effect transistor PM15 and the drain of field effect transistor NM14, and the drain is connected to the drain of field effect transistor PM16. The gate of field effect transistor PM15 is connected to the drain of field effect transistor PM13 and the drain of field effect transistor NM12, and the source is connected to the source of field effect transistor PM16 and the source of field effect transistor PM14 and is simultaneously connected to voltage V PUSB . The gate of field effect transistor PM16 is connected to the drain of field effect transistor PM14 and the drain of field effect transistor NM13.

[0085] In some embodiments, the state transmission stage module 153 includes field effect transistors PM17 and NM16. The gate of field effect transistor PM17 is connected to the gate of field effect transistor NM16 and is simultaneously connected to the drain of field effect transistor PM16 and the drain of field effect transistor NM15. The drain of field effect transistor PM17 is connected to the drain of field effect transistor NM16 and simultaneously outputs voltage to the bit line terminal BL_OUT, and the source is connected to voltage V PHV . The source of field effect transistor NM16 is connected to voltage V NHV . Among them, V PHV is the first driving voltage, and V NHV is the second driving voltage.

[0086] The conduction and cutoff of the field effect transistor PM17 and the field effect transistor NM16 can be controlled by the first-stage cross-coupling structure module 151 and the second-stage cross-coupling structure module 152, so that the state transmission stage module 153 outputs the voltage V to the bit line terminal BL_OUT PHV or the voltage V NHV .

[0087] In some embodiments, the blocking control module 154 includes a field effect transistor NM17 and a field effect transistor NM18. The source of the field effect transistor NM17 is connected to the drain of the field effect transistor PM17 and the drain of the field effect transistor NM16. The gate of the field effect transistor NM17 is connected to the voltage V S1 , and the drain is connected to the source line terminal SL_OUT. The drain of the field effect transistor NM18 is connected to the source line terminal SL_OUT, the gate is connected to the voltage V S2 , and the source is grounded.

[0088] In some embodiments, in the read mode, the bit line needs to be floating and the source line needs to be grounded. Through the blocking control module 154, the bit line terminal BL_OUT can be made floating and the source line terminal SL_OUT can be grounded in the read mode.

[0089] In some embodiments, the bit line and source line control module 16 is used to output the control signals INB, the voltage V PUSB , the voltage V NUSB , the voltage V PHV , the voltage V NHV , the voltage V S1 and the voltage V S2 to the bit line and source line driving module 15.

[0090] In some embodiments, the field effect transistors NM12, NM13, NM14, NM15, NM16, NM17 and NM18 are all N-type field effect transistors. The field effect transistors PM13, PM14, PM15, PM16 and PM17 are all P-type field effect transistors.

[0091] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of the bit line and source line control module provided by the embodiment of the present application. As shown in Figure 8As shown, in some embodiments, the bit line and source line control module 16 includes a positive high voltage level conversion circuit 161, a reference ground voltage conversion circuit 162, a negative high voltage level conversion circuit 163, and a gating circuit 164. The positive high voltage level conversion circuit 161, the reference ground voltage conversion circuit 162, and the negative high voltage level conversion circuit 163 are all connected to the gating circuit 164. Among them, the positive high voltage level conversion circuit 161 is used to convert the control signal of the main control module 20 into a positive high voltage control signal. The reference ground voltage conversion circuit is used to convert the control signal of the main control module 20 into a reference ground voltage control signal. The negative high voltage level conversion circuit is used to convert the control signal of the main control module 20 into a negative high voltage control signal. The gating circuit 164 is used to transmit the positive high voltage control signal, the reference ground voltage control signal, or the negative high voltage control signal to the bit line and source line driving module 15.

[0092] In some embodiments, the positive high voltage level conversion circuit 161 is used to access the low voltage digital signal a, and convert the low voltage digital signal a into a positive high voltage control signal and the inverted signal of the positive high voltage control signal, and output them to the gating circuit 164. The reference ground voltage conversion circuit 162 is used to access the low voltage digital signal b, and convert the low voltage digital signal b into a reference ground voltage control signal and the inverted signal of the reference ground voltage control signal, and output them to the gating circuit 164. The negative high voltage level conversion circuit 163 is used to access the low voltage digital signal c, and convert the low voltage digital signal c into a negative high voltage control signal and output it to the gating circuit 164.

[0093] Optionally, the gating circuit 164 can also transmit multiple voltages or signals to the bit line and source line driving module 15 according to the received control signal.

[0094] Please refer to Figure 9 , Figure 9 which is a schematic structural diagram of the negative voltage charge pump module provided by the embodiment of the present application. As Figure 9 shown, in some embodiments, the negative voltage charge pump module 18 includes a four-phase clock generation circuit 181, a charge pump circuit 182, an operational amplifier 183, an oscillator 184, a logic operation module 185, a buffer 186, and a feedback voltage stabilization circuit 187. The four-phase clock generation circuit 181 is connected to the charge pump circuit 182. The operational amplifier 183 is connected to the buffer 186 through a resistor R2 and is also connected to the reference ground voltage. The output of the operational amplifier 183 and the output of the oscillator 184 are the inputs of the logic operation module 185. The four-phase clock generation circuit 181 accesses the output signal of the logic operation module 185 and outputs a clock signal to the charge pump circuit 182. The charge pump circuit 182 is connected to the feedback voltage stabilization circuit 187.

[0095] In some embodiments, the logic operation module 185 includes a NOT gate and a NAND gate. The NOT gate is connected to the NAND gate. The NAND gate is connected to the oscillator 184 and the operational amplifier 183. The NOT gate is connected to the four-phase clock generation circuit 181.

[0096] In some embodiments, the feedback voltage regulation circuit 187 includes a resistor R1, a resistor R2, a resistor R3, and a capacitor C1. The first end of the resistor R1 is connected to the charge pump circuit 182, the second end is connected to the first end of the resistor R2, and is simultaneously connected to the operational amplifier 183. The second end of the resistor R2 is connected to the buffer 186. After the resistor R3 and the capacitor C1 are connected in parallel, one end is connected to the resistor R1, and the other end is grounded.

[0097] In some embodiments, the buffer 186 is connected to the voltage Vref.

[0098] In some embodiments, the voltage Vref is a bandgap reference voltage.

[0099] In some embodiments, the word line programming and erasing driving module 13 further includes a bandgap reference circuit for outputting the voltage Vref.

[0100] In some embodiments, the negative voltage charge pump module 18 further includes a bandgap reference circuit for electrically outputting the voltage Vref.

[0101] In some embodiments, the main control module stores the weight parameter matrix of the artificial intelligence model in the floating gate transistor array module. Then, the main control module converts the input signal into a voltage signal according to the current calculation task and inputs it into the floating gate transistor array module, and the collected output current value is the calculation result.

[0102] Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of the storage device provided by the embodiment of the present application. As Figure 10 shown, the present application also provides a storage device 2, and the storage device 2 includes the above-mentioned memory and computing integrated chip 1.

[0103] In summary, the memory and computing integrated chip provided by the embodiment of the present application has the following advantages:

[0104] 1. The Flash memory and computing integrated unit includes a floating gate transistor array module, a word line reading driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module, and a negative voltage charge pump module composed of multiple floating gate transistors connected. The Flash memory and computing integrated unit can store data and perform calculations, effectively shortening the data transmission distance, reducing the calculation delay, thus greatly improving the calculation efficiency of the chip, and can also save data when power is off.

[0105] 2. Through the circuit structure of the word line programming and erasing driving module, when the word line programming and erasing driving module outputs the operating voltages in different working modes, the turned-on field effect transistors are different, and the influence of the previous working mode on the circuit state of the next working mode can be avoided when switching the working modes.

[0106] 3. By using the word line control module as the digital shift module, the number of control signals required can be greatly reduced.

[0107] The present application also provides a control method for a memory-computation integrated chip, which is applied to the main control module of the memory-computation integrated chip. The control method for the memory-computation integrated chip includes steps S100 to S200.

[0108] Step S100: When powering on, perform threshold voltage calibration on the Flash memory-computation integrated unit.

[0109] In some embodiments, the type of the floating gate transistor is a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC), or a quad-level cell (QLC) type. The floating gate transistor of the SLC type can store 1 bit of data, the floating gate transistor of the MLC type can store 2 bits of data, the floating gate transistor of the TLC type can store 3 bits of data, and the floating gate transistor of the TLC type can store 4 bits of data.

[0110] The charge of the floating gate transistor is distributed on the floating gate layer. By inputting a substrate voltage and a gate voltage to the floating gate transistor, electrons can enter the floating gate layer, so that the floating gate transistor stores data. When the type of the floating gate transistor is the MLC type, the TLC type, or the QLC type, by inputting different combinations of substrate voltages and gate voltages to the floating gate transistor, charges can enter different levels of the floating gate layer, so that the floating gate transistor stores multiple data.

[0111] During the operation of the floating gate transistor, the floating gate layer of the floating gate transistor is wrapped by an insulating layer for isolating electrons. In the write operation and the erase operation, electrons need to pass through the insulating layer, which will cause the insulating layer to be gradually damaged. During the process of the gradual damage of the insulating layer, the threshold voltages for different target levels for enabling electrons to enter the floating gate layer will change. Therefore, when powering on, the threshold voltage calibration can be performed on the Flash memory-computation integrated unit to improve the success rate of data storage. The threshold voltage refers to the minimum gate voltage required to change the floating gate transistor from the cut-off state to the on state under a fixed substrate voltage. The threshold voltage is also the operating voltage in the programming mode.

[0112] In some embodiments, step S100 includes steps S110 to S150.

[0113] Step S110: When powering on, apply an operating voltage in the erase mode to the floating gate transistor array module in the Flash memory and computing integrated unit.

[0114] In some embodiments, the main control module controls the word line programming and erase driving module through the word line control module to output an operating voltage in the erase mode to the word lines of the floating gate transistor array module, so as to initialize the floating gate transistor array module.

[0115] Step S120: Apply a preset substrate potential to the floating gate transistor array module.

[0116] In some embodiments, the main control module applies a preset substrate potential to the floating gate transistors in the floating gate transistor array module through the substrate potential control module.

[0117] Step S130: Apply different threshold voltages to the floating gate transistor array module in sequence according to a plurality of preset threshold voltages.

[0118] In some embodiments, the threshold voltages are applied to the floating gate transistor array in the floating gate transistor array module row by row or column by column.

[0119] Exemplarily, when the type of the floating gate transistor is the MLC type, the floating gate transistor corresponds to 4 theoretical threshold voltages. The plurality of preset threshold voltages include each theoretical threshold voltage and a plurality of threshold voltages close to each theoretical threshold voltage. At this time, one of the plurality of preset threshold voltages is applied to the floating gate transistor array module in sequence.

[0120] Step S140: Detect the drain current of each row or each column of floating gate transistors in the floating gate transistor array module, and record the threshold voltage at this time when the drain current is greater than the conduction current.

[0121] Step S150: Perform threshold voltage calibration based on the recorded plurality of threshold voltages and the corresponding theoretical threshold voltages.

[0122] In some embodiments, step S150 includes steps S151 to S153.

[0123] Step S151: Divide the plurality of threshold voltages whose difference from one theoretical threshold voltage is less than a preset difference into a group, and obtain multiple groups of threshold voltages.

[0124] Step S152: Calculate the mean and standard deviation of each group of threshold voltages, and calculate the aging coefficient corresponding to each resulting threshold voltage based on the mean and standard deviation of each group of threshold voltages, the maximum number of erase / program cycles of the current type of floating-gate transistor, and the number of erase / program cycles of the current floating-gate transistor.

[0125] In some embodiments, the aging coefficient is used to represent the average drift amount per unit of the threshold voltage with respect to temperature change after each erase / program cycle of the floating-gate transistor.

[0126] In some embodiments, determine the aging degree of the floating-gate transistor corresponding to each group of threshold voltages based on the standard deviation of each group of threshold voltages, and select a corresponding calculation method to calculate the aging coefficient corresponding to each group of threshold voltages.

[0127] Optionally, when the standard deviation of a group of threshold voltages is less than a first preset standard deviation, determine that the floating-gate transistor corresponding to this group of threshold voltages is mildly aged, and use the calculation formula corresponding to mild aging to calculate the aging coefficient.

[0128] Optionally, the calculation formula for the aging coefficient corresponding to mild aging is: where a k represents the aging coefficient corresponding to the k-th resulting threshold voltage, μ k represents the mean of the k-th group of threshold voltages, W max represents the maximum number of erase / program cycles of the current type of floating-gate transistor, W represents the number of erase / program cycles of the current floating-gate transistor, T C represents the temperature correction coefficient, V refk represents the k-th theoretical threshold voltage.

[0129] Optionally, T C is -0.02.

[0130] Optionally, when the standard deviation of a group of threshold voltages is not less than a second preset standard deviation, determine that the floating-gate transistor corresponding to this group of threshold voltages is severely aged, and use the calculation formula corresponding to severe aging to calculate the aging coefficient.

[0131] Optionally, the calculation formula for the aging coefficient corresponding to severe aging is: where β represents the aging acceleration coefficient. Optionally, β is 1, 1.1, 1.3, or 1.5, etc.

[0132] Step S153: Calculate the resulting threshold voltage based on the standard deviation of each group of threshold voltages and the corresponding aging coefficient.

[0133] In some embodiments, the calculation formula for the resulting threshold voltage is: V k = V refk + α k (W max-W)(T - T0), where V k represents the k-th result threshold voltage, and T0 represents the current temperature.

[0134] In some embodiments, after calibrating the threshold voltage, when writing data subsequently, the corresponding result threshold voltage is used to control the floating-gate transistor to store data according to the value of the data.

[0135] Step S200: Store data in the floating-gate transistor array module based on the current calculation task type and the type of the floating-gate transistor array module in the Flash computing-in-memory unit and perform calculations.

[0136] In some embodiments, the Flash computing-in-memory unit includes multiple floating-gate transistor array modules. The types of the floating-gate transistors in each floating-gate transistor array module are the same, and at least two of the multiple floating-gate transistor array modules have different types of floating-gate transistors.

[0137] In some embodiments, step S200 includes step S210 to step S220.

[0138] Step S210: Determine the target floating-gate transistor array module for storing data based on the current calculation task type.

[0139] In some embodiments, when the current calculation task type is matrix calculation, the target floating-gate transistor array module for storing data is determined to be all the floating-gate transistor array modules that can store multi-bit data. For example, the target floating-gate transistor array module is the floating-gate transistor array module of MLC type, TLC type, or QLC type floating-gate transistors.

[0140] Exemplarily, when the artificial intelligence model is a neural network model, large-scale matrix calculations are required. At this time, it is necessary to improve the storage efficiency and calculation efficiency. Therefore, the target floating-gate transistor array module for storing data is determined to be all the floating-gate transistor array modules that can store multi-bit data.

[0141] In some embodiments, when the current calculation task type is logic calculation, the target floating-gate transistor array module for storing data is determined to be all the floating-gate transistor array modules including SLC type floating-gate transistors.

[0142] Exemplarily, in an application scenario of performing Boolean logic operations or state machine control, logical calculations are required. In logical calculations, the values to be calculated are Boolean values, and high storage reliability is required. Therefore, the target floating-gate transistor array module is a floating-gate transistor array module including floating-gate transistors of the SLC type. Although the floating-gate transistors of the SLC type can only store 1 bit of data, their storage reliability is the highest and is suitable for storing Boolean values.

[0143] In some embodiments, when the current calculation task type is mixed-precision calculation, the type of calculation data is further identified, and the target floating-gate transistor array module corresponding to the data is determined according to the type of calculation data.

[0144] Exemplarily, when performing double-precision floating-point operations, the current calculation task type is mixed-precision calculation.

[0145] Optionally, the types of calculation data include critical weight data, non-critical weight data, and error-sensitive data.

[0146] In some embodiments, when the type of calculation data is critical weight data, a target floating-gate transistor array module including floating-gate transistors of the SLC type is selected to store and calculate the critical weight data.

[0147] In some embodiments, when the type of calculation data is non-critical weight data, the target floating-gate transistor array module is determined to be a floating-gate transistor array module including floating-gate transistors of the MLC type, TLC type, QLC type, or SLC type.

[0148] Optionally, the target floating-gate transistor array module is also selected according to the data volume of the non-critical weight data. For example, when the data volume of the non-critical weight data is greater than a first data volume, the target floating-gate transistor array module is determined to be a floating-gate transistor array module including floating-gate transistors of the QLC type. When the data volume of the non-critical weight data is not greater than the first data volume and greater than a second data volume, the target floating-gate transistor array module is determined to be a target floating-gate transistor array module including floating-gate transistors of the TLC type. When the data volume of the non-critical weight data is not greater than the second data volume and greater than a third data volume, the target floating-gate transistor array module is determined to be a target floating-gate transistor array module including floating-gate transistors of the MLC type. When the data volume of the non-critical weight data is not greater than the third data volume, the target floating-gate transistor array module is determined to be a target floating-gate transistor array module including floating-gate transistors of the SLC type. Wherein, the first data volume is greater than the second data volume, and the second data volume is greater than the third data volume.

[0149] In some embodiments, the first data volume, the second data volume, and the third data volume are preset.

[0150] In some embodiments, determining the first data volume, the second data volume, and the third data volume based on the type of the artificial intelligence model deployed on the in-memory computing model includes steps (210.1) to (210.5).

[0151] (210.1) Obtain the type information of the artificial intelligence model deployed on the in-memory computing model.

[0152] In some embodiments, the types of artificial intelligence models deployed on the in-memory computing model may include large language models, vision models, lightweight neural network models, and edge AI models. An edge AI model refers to a model that runs on an edge device close to the data source and does not need to transmit data to a remote cloud server or data center.

[0153] (210.2) When it is determined according to the type information that the artificial intelligence model is a large language model, determine the first data volume to be 100 gigabytes (GB), the second data volume to be 10 GB, and the third data volume to be 1 GB.

[0154] The number of parameters of a large language model is usually greater than 100 billion (B), where non-critical weight data generally accounts for 70%-90% and is a sparse matrix. In this way of setting the data volume, a floating gate transistor array module including floating gate transistors of the QLC type is generally used to store non-critical weight data, which can meet the huge storage requirements of the artificial intelligence model.

[0155] (210.3) When it is determined according to the type information that the artificial intelligence model is a vision model, determine the first data volume to be 50 GB, the second data volume to be 5 GB, and the third data volume to be 1 GB.

[0156] Exemplarily, the vision model can be a Transformer model.

[0157] The number of parameters of a vision model is usually between 10B and 100B, where non-critical weight data generally accounts for 60%-80%. In this way of setting the data volume, a floating gate transistor array module including floating gate transistors of the TLC type is generally used to store non-critical weight data, and the TLC type of floating gate transistor can balance the requirements of storage density and erasure life. When the vision model integrates multi-task branches and the data volume of non-critical weight data is greater than 50 GB, a floating gate transistor array module including floating gate transistors of the QLC type is used to store non-critical weight data, which can meet the storage requirements of the artificial intelligence model.

[0158] (210.4) When it is determined according to the type information that the artificial intelligence model is a lightweight neural network model, the first data volume is determined to be 10 GB, the second data volume is determined to be 1 GB, and the third data volume is determined to be 0.1 GB.

[0159] The number of parameters of the lightweight neural network model is usually between 1B and 10B. Among them, the non-critical weight data generally accounts for 50%-70%. In this way of setting the data volume, a floating-gate transistor array module including floating-gate transistors of MLC type or TLC type is generally used to store the non-critical weight data, which can balance the requirements of storage density and erase / write life.

[0160] (210.5) When it is determined according to the type information that the artificial intelligence model is an edge AI model, the first data volume is determined to be 1 GB, the second data volume is determined to be 0.5 GB, and the third data volume is determined to be 0.05 GB.

[0161] The number of parameters of the edge AI model is usually less than 1B. Among them, the non-critical weight data generally accounts for 40%-60%. In this way of setting the data volume, a floating-gate transistor array module including floating-gate transistors of SLC type or MLC type is generally used to store the non-critical weight data.

[0162] In some embodiments, when the type of the calculated data is error-sensitive data, error correction coding is performed on the error-sensitive data, and the target floating-gate transistor array module is determined to be a floating-gate transistor array module including floating-gate transistors of SLC type.

[0163] Step S220: Store the data in the target floating-gate transistor array module and perform calculations.

[0164] In summary, the present application provides a memory - in - computing chip and a storage device. The memory - in - computing chip includes: a Flash memory - in - computing unit for storing data and performing calculations. The Flash memory - in - computing unit includes a floating - gate transistor array module composed of a plurality of connected floating - gate transistors, a word - line reading and driving module, a word - line programming and erasing driving module, a word - line control module, a bit - line and source - line driving module, a bit - line and source - line control module, a substrate potential control module, and a negative - voltage charge - pump module. A main control module is used to control the operation of the Flash memory - in - computing unit to execute storage operations and calculation operations, and the main control module is connected to the Flash memory - in - computing unit. The floating - gate transistor array module is connected to the word - line reading and driving module, the word - line programming and erasing driving module, the bit - line and source - line driving module, and the substrate potential control module. The word - line control module is connected to the word - line reading and driving module and the word - line programming and erasing driving module. The bit - line and source - line control module is connected to the bit - line and source - line driving module, and the negative - voltage charge - pump module is connected to the word - line programming and erasing driving module. Through the Flash memory - in - computing unit including a floating - gate transistor array module composed of a plurality of connected floating - gate transistors, a word - line reading and driving module, a word - line programming and erasing driving module, a word - line control module, a bit - line and source - line driving module, a bit - line and source - line control module, a substrate potential control module, and a negative - voltage charge - pump module, the Flash memory - in - computing unit can store data and perform calculations, effectively shortening the data - transmission distance, reducing the calculation latency, thus greatly improving the calculation efficiency of the chip, and being able to save data even when power is off.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A processing-in-memory chip, characterized in that Including: A Flash memory and computing integrated unit, which is used to store data and perform calculations; The Flash memory and computing integrated unit includes a floating gate transistor array module composed of multiple floating gate transistors connected, a word line reading and driving module, a word line programming and erasing driving module, a word line control module, a bit line and source line driving module, a bit line and source line control module, a substrate potential control module, and a negative voltage charge pump module; A main control module, which is used to control the operation of the Flash memory and computing integrated unit to execute storage operations and calculation operations, and the main control module is connected to the Flash memory and computing integrated unit; The floating gate transistor array module is connected to the word line reading and driving module, the word line programming and erasing driving module, the bit line and source line driving module, and the substrate potential control module; The word line control module is connected to the word line reading and driving module and the word line programming and erasing driving module; The bit line and source line control module is connected to the bit line and source line driving module, and the negative voltage charge pump module is connected to the word line programming and erasing driving module; The floating gate transistor array module is used to realize the functions of storing data and calculating; The word line control module is used to control the word line reading and driving module and the word line programming and erasing driving module to output the operating voltages required for the current working mode to the floating gate transistor array module according to the control signal of the main control module, and the working modes include a reading mode, a programming mode, and an erasing mode; The word line reading and driving module is used to output the operating voltage in the reading mode to the word lines of the floating gate transistor array module according to the control signal of the word line control module; The word line programming and erasing driving module is used to output the operating voltage in the programming mode or the erasing mode to the word lines of the floating gate transistor array module according to the control signal of the word line control module; The bit line and source line control module is used to control the bit line and source line driving module to output corresponding operating voltages to the bit line and source line of the floating gate transistor array module according to the control signal of the main control module, so that the floating gate transistor array module is in the target working mode; The substrate potential control module is used to control the substrate potential of the floating gate transistors in the floating gate transistor array module; The negative voltage charge pump module is used to provide the negative voltage required in the erasing mode for the word line programming and erasing driving module.

2. The memory and computing integrated chip according to claim 1, wherein The floating gate transistor array module is a NAND Flash array module, and the NAND Flash array module includes floating gate transistors arranged in A rows and B columns. Every B floating gate transistors are connected in series as a row. The source electrodes of the first floating gate transistors in each row of floating gate transistors are all connected to the source line to form a column of ground selection transistors. The drain electrodes of the last floating gate transistors in each row of floating gate transistors are connected to the bit line corresponding to the row. The gate electrodes of all floating gate transistors in each column of floating gate transistors are all connected to a word line, where A and B are both positive integers.

3. The memory and computing integrated chip according to claim 1, wherein The floating gate transistor array module is a NOR Flash array module. The sources of all the floating gate transistors in the NOR Flash array module are connected to a source line, the drains are connected to a bit line, and the gates of each column of floating gate transistors are connected to a word line.

4. The computing-in-memory chip according to claim 1, wherein the word line programming and erasing driving module includes a first level conversion circuit module, a voltage clamping module, and a high voltage transmission module. The first level conversion circuit module is connected to the voltage clamping module, and the voltage clamping module is connected to the high voltage transmission module.

5. The computing-in-memory chip according to claim 1, wherein the word line reading driving module includes a second level conversion circuit module, a signal driving module, and a transmission gate module. The second level conversion circuit module is connected to the signal driving module, and the signal driving module is connected to the transmission gate module; the signal driving module includes a first field effect transistor and a second field effect transistor. The source of the first field effect transistor is connected to an analog reading voltage, the gate is connected to the second level conversion circuit module, and the drain is connected to the drain of the second field effect transistor. The source of the second field effect transistor is connected to the reference ground voltage of the analog reading voltage, and the gate is connected to the second level conversion circuit module; the drains of the first field effect transistor and the second field effect transistor are both connected to the transmission gate module.

6. The computing-in-memory chip according to claim 1, wherein the bit line and source line driving module includes a first-stage cross-coupled structure module, a second-stage cross-coupled structure module, a state transmission stage module, and a blocking control module. The first-stage cross-coupled structure module is connected to the second-stage cross-coupled structure module, the second-stage cross-coupled structure module is connected to the state transmission stage module, and the state transmission stage module is connected to the blocking control module.

7. The computing-in-memory chip according to claim 1, wherein the bit line and source line control module includes a positive high voltage level conversion circuit, a reference ground voltage conversion circuit, a negative high voltage level conversion circuit, and a gating circuit. The positive high voltage level conversion circuit, the reference ground voltage conversion circuit, and the negative high voltage level conversion circuit are all connected to the gating circuit.

8. The computing-in-memory chip according to claim 1, wherein the negative voltage charge pump module includes a four-phase clock generation circuit, a charge pump circuit, an operational amplifier, an oscillator, a logic operation module, a buffer, and a feedback voltage regulation circuit. The four-phase clock generation circuit is connected to the charge pump circuit. The operational amplifier is connected to the buffer through a resistor and is also connected to the reference ground voltage. The outputs of the operational amplifier and the oscillator are inputs to the logic operation module. The four-phase clock generation circuit receives the output signal of the logic operation module and outputs a clock signal to the charge pump circuit. The charge pump circuit is connected to the feedback voltage regulation circuit.

9. The computing-in-memory chip according to claim 1, wherein The word line control module includes a plurality of cascaded flip-flops and a plurality of cascaded latches, and each of the flip-flops is connected to one of the latches.

10. A storage device, characterized in that, The storage device includes the computing-in-memory chip according to any one of claims 1 to 9.

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