Capacitor arrangement method based on thermal modeling technology

Abstract

The invention provides a capacitor arrangement method based on a thermal modeling technology, and the method comprises the steps: obtaining the loss factor parameters of a first capacitor and a second capacitor, and obtaining the thermal resistance parameters of the first capacitor and the second capacitor; obtaining power loss parameters of the first capacitor and the second capacitor based on the loss factor parameters; based on the preset number of the first capacitors and the second capacitors, the first capacitors and the second capacitors are arranged through a preset layout, and multiple capacitor distribution modes are obtained; on the basis of the power loss parameters, the average core temperature of the multiple capacitance distribution modes is obtained; selecting a capacitance distribution mode corresponding to the minimum average core temperature to arrange the capacitors; wherein the thermal resistance parameters comprise core shell thermal resistance and shell environment thermal resistance. Through the above method, the maximum temperature and the average temperature of the electrolytic capacitors are reduced, so that the heat distribution of the electrolytic capacitors in the capacitor bank is more uniform, and the risk of premature thermal aging failure of individual electrolytic capacitors is reduced.

Description

Technical Field

[0001] The present invention relates to the field of capacitor arrangement, and more specifically, to a capacitor arrangement method based on thermal modeling technology. Background Art

[0002] Currently, in the prior art, in the sequential arrangement of capacitors, due to position reasons, the temperatures of individual capacitors are uneven, resulting in a poor thermal distribution of the capacitor bank. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art or related technologies.

[0004] To this end, a first aspect of the present invention provides a capacitor arrangement method based on thermal modeling technology.

[0005] A second aspect of the present invention provides a computer-readable storage medium.

[0006] In view of this, a first aspect of the present invention provides a capacitor arrangement method based on thermal modeling technology, including: obtaining loss factor parameters of a first capacitor and a second capacitor; obtaining thermal resistance parameters of the first capacitor and the second capacitor; obtaining power loss parameters of the first capacitor and the second capacitor based on the loss factor parameters; arranging the first capacitor and the second capacitor in a staggered layout manner based on a preset number of the first capacitor and the second capacitor to obtain multiple capacitor distribution modes; obtaining average core temperatures of the multiple capacitor distribution modes based on the power loss parameters; selecting the capacitor distribution mode corresponding to the minimum average core temperature to arrange the capacitors; wherein the thermal resistance parameters include core-shell thermal resistance and shell-environment thermal resistance.

[0007] In addition, the capacitor arrangement method based on thermal modeling technology provided in the above technical solution of the present invention may further have the following additional technical features: In some technical solutions of the present invention, optionally, obtaining power loss parameters of the first capacitor and the second capacitor based on the loss factor parameters includes: obtaining equivalent resistance values of the first capacitor and the second capacitor; obtaining current passing values of the first capacitor and the second capacitor; obtaining power loss parameters based on the current passing values and the equivalent resistance values.

[0008] In some technical solutions of the present invention, optionally, obtaining thermal resistance parameters of the first capacitor and the second capacitor includes: obtaining core-shell thermal resistances of the first capacitor and the second capacitor; obtaining shell-environment thermal resistance of the first capacitor based on the cooling method of the first capacitor; obtaining shell-environment thermal resistance of the second capacitor based on the cooling method of the second capacitor.

[0009] In some technical solutions of the present invention, optionally, based on the preset quantities of the first capacitor and the second capacitor, the first capacitor and the second capacitor are arranged in a staggered layout manner to obtain various capacitor distribution modes, including: obtaining the preset arrangement positions of the capacitors through the staggered layout manner; and obtaining various capacitor distribution modes through permutation and combination based on the preset quantities of the first capacitor and the second capacitor.

[0010] In some technical solutions of the present invention, optionally, based on the power loss parameters, the average core temperatures of various capacitor distribution modes are obtained respectively, including: obtaining the coupling thermal resistance between adjacent capacitors based on the distance between adjacent capacitors; obtaining the capacitor housing temperature based on the power loss parameters; obtaining the capacitor core temperature based on the capacitor housing temperature, the coupling thermal resistance and the power loss; and obtaining the average core temperature based on all the capacitor core temperatures of the current capacitor distribution mode; wherein, the capacitor housing temperature includes the housing temperature of the first capacitor and the housing temperature of the second capacitor.

[0011] In some technical solutions of the present invention, optionally, the obtaining of the capacitor housing temperature based on the power loss parameters includes: obtaining the ambient temperature; and obtaining the capacitor housing temperature based on the ambient temperature, the power loss parameters, the coupling thermal resistance and the housing ambient thermal resistance.

[0012] Through the technical solution of the present invention, the calculation accuracy almost the same as that of the finite element simulation can be obtained; the calculation time is about 1 s, which is better than the calculation time of dozens of minutes or even several hours required by the finite element simulation, and there is no need to damage the capacitor structure; the maximum temperature and the average temperature of the electrolytic capacitor are reduced, so that the thermal distribution of the electrolytic capacitors inside the capacitor bank is more uniform, the risk of premature thermal aging failure of individual electrolytic capacitors is reduced, and the long-term operation life of the electrolytic capacitor and the overall capacitor bank is improved.

[0013] The second aspect of the present invention provides a computer-readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the product evaluation method based on ability quantization of any one of the above technical solutions is implemented.

[0014] The additional aspects and advantages of the present invention will be partly given in the following description, partly will become obvious from the following description, or be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 FIG. is a flowchart of a capacitor arrangement method based on a thermal modeling technique according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0017] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0018] Next, refer to Figure 1 Describe a capacitor layout method based on a thermal modeling technique according to some embodiments of the present invention.

[0019] As Figure 1 shown, a first aspect of the present invention provides a capacitor layout method based on a thermal modeling technique, including: Step 102, obtaining the loss factor parameters of the first capacitor and the second capacitor; Step 104, obtaining the thermal resistance parameters of the first capacitor and the second capacitor; First, the present application selects two different resistors. Then, because the resistors are different, their parameters, performances, etc. will also be different. Then, before layout, the present application needs to obtain the relevant parameters of the capacitors, that is, obtain the loss factor parameters of the first capacitor and the second capacitor, and obtain the thermal resistance parameters of the first capacitor and the second capacitor.

[0020] Step 106, based on the loss factor parameters, obtaining the power loss parameters of the first capacitor and the second capacitor; In step 106, first substitute the loss factor parameters into the power loss model, and then obtain the power loss parameters of the first capacitor and the second capacitor.

[0021] Step 108, based on the preset quantities of the first capacitor and the second capacitor, arranging the first capacitor and the second capacitor through a preset layout to obtain various capacitor distribution modes; In step 108, respectively obtain the set quantities expected to be obtained for the two types of capacitors, and arrange the two types of capacitors according to the preset arrangement positions of the capacitors. Then, there will definitely be various situations at this time. Then, after determining the preset quantities and the preset layout of the first capacitor and the second capacitor, various capacitor distribution modes are obtained.

[0022] Step 110, based on the power loss parameters, respectively obtaining the average core temperatures of various capacitor distribution modes; Step 110, further obtain the average core temperatures of various capacitor distribution modes according to the power loss parameters obtained in step 106.

[0023] Step 112: Select the capacitance distribution method corresponding to the minimum average core temperature to arrange the capacitors. Among them, the thermal resistance parameters include the core-shell thermal resistance and the shell-environment thermal resistance.

[0024] Finally, to make the thermal distribution of the capacitors more uniform, select the capacitance distribution method corresponding to the minimum average core temperature to arrange the capacitors.

[0025] Through the above method, the maximum temperature and the average temperature of the electrolytic capacitors are reduced, the thermal distribution of the electrolytic capacitors inside the capacitor bank is made more uniform, the risk of premature thermal aging failure of individual electrolytic capacitors is reduced, and the long-term operating life of the electrolytic capacitors and the overall capacitor bank is improved.

[0026] Further, in some embodiments of the present invention, based on the loss factor parameters, the power loss parameters of the first capacitor and the second capacitor are obtained, including: obtaining the equivalent resistance values of the first capacitor and the second capacitor; obtaining the current passing values of the first capacitor and the second capacitor; and obtaining the power loss parameters based on the current passing values and the equivalent resistance values.

[0027] It should be noted that the current passing value is the capacitance value of the capacitor when the capacitor is energized.

[0028] Specifically, the calculation formula for the power loss parameter is: . Wherein, is the power loss parameter. is the current passing value, is the equivalent resistance value of the i-th capacitor.

[0029] Further, in some embodiments of the present invention, the thermal resistance parameters of the first capacitor and the second capacitor are obtained, including: Obtaining the core-shell thermal resistances of the first capacitor and the second capacitor; It should be noted that the core-shell thermal resistance of any capacitor can be obtained from the technical manual provided by the capacitor manufacturer. For the convenience of understanding, it can be regarded as a constant.

[0030] Based on the cooling method of the first capacitor, obtaining the shell-environment thermal resistance of the first capacitor; Based on the cooling method of the second capacitor, obtaining the shell-environment thermal resistance of the second capacitor.

[0031] Specifically, the current cooling method of the capacitor can be divided into cooling with an air-cooling device and without an air-cooling device. Under the two cooling methods, the Nusselt number is different.

[0032] Further, in some embodiments of the present invention, based on the preset quantities of the first capacitor and the second capacitor, various capacitor distribution patterns are obtained by preset layout for arranging the first capacitor and the second capacitor, including: obtaining the preset arrangement positions of the capacitors by preset layout; and obtaining various capacitor distribution patterns by permutation and combination based on the preset quantities of the first capacitor and the second capacitor.

[0033] In this embodiment, according to the information of the preset layout, it is possible to know which positions can place capacitors, and thus know the arrangement positions of all capacitors. Then, according to the preset quantities of the confirmed first capacitor and second capacitor, various different capacitor distribution patterns are obtained by permutation and combination.

[0034] Further, in some embodiments of the present invention, based on the power loss parameters, the average core temperatures of various capacitor distribution patterns are respectively obtained, including: obtaining the coupling thermal resistance between adjacent capacitors based on the distance between adjacent capacitors; obtaining the capacitor housing temperature based on the power loss parameters; obtaining the capacitor core temperature based on the capacitor housing temperature, the coupling thermal resistance, and the power loss; and obtaining the average core temperature based on all the capacitor core temperatures of the current capacitor distribution pattern; wherein the capacitor housing temperature includes the housing temperature of the first capacitor and the housing temperature of the second capacitor.

[0035] In this embodiment, first, the coupling thermal resistance between adjacent capacitors is obtained, and then the capacitor housing temperature can be obtained based on the power loss parameters.

[0036] On this basis, the capacitor core temperature is obtained according to the capacitor housing temperature, the coupling thermal resistance, and the power loss; the average core temperature is obtained based on all the capacitor core temperatures of the current capacitor distribution pattern; wherein the capacitor housing temperature includes the housing temperature of the first capacitor and the housing temperature of the second capacitor.

[0037] Further, in some embodiments of the present invention, it is characterized in that obtaining the capacitor housing temperature based on the power loss parameters includes: obtaining the ambient temperature; and obtaining the capacitor housing temperature based on the ambient temperature, the power loss parameters, the coupling thermal resistance, and the housing ambient thermal resistance.

[0038] Specifically, the calculation formula for the capacitor housing temperature is: . Wherein, T a is the ambient temperature, T c,i , T c,j are respectively the housing temperatures of the i-th and j-th capacitors. P loss,i ( t ) is the power loss parameter of the i-th capacitor. The coupling thermal resistance between adjacent capacitors is Rij and the ambient thermal resistance of the capacitor housing is R i-amb .

[0039] Specifically, the calculation formula for the core temperature of the capacitor is: . Wherein, T i is the core temperature of the capacitor, R h-c,i the core housing thermal resistance.

[0040] The second aspect of the present invention provides a computer-readable storage medium, on which a program or instructions are stored. When the program or instructions are executed by a processor, the capacitance arrangement method based on thermal modeling technology in any of the above embodiments is implemented, and thus has all the beneficial technical effects of the capacitance arrangement method based on thermal modeling technology in any of the above embodiments.

[0041] Among them, the computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc, etc.

[0042] The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above devices, but is not limited thereto. A non-exhaustive list of more specific examples of the computer-readable storage medium includes: portable computer floppy disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, static random access memories, portable compact disc read-only memories, digital versatile disks, memory cards, floppy disks, encoding mechanical devices (such as punched cards or grooves with raised structures recording instructions), and any suitable combination of the above devices. The computer-readable storage medium used herein should not be construed as a signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media, or electrical signals transmitted through wires.

[0043] In the claims, the specification and the drawings of the present invention, the term "a plurality of" means two or more, unless otherwise explicitly defined. The orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings. This is only for more convenient description of the present invention and to simplify the description process, rather than to indicate or imply that the device or element referred to must have the specific orientation described, be constructed and operated in a specific orientation. Therefore, these descriptions should not be construed as limitations on the present invention; terms such as "connection", "installation", "fixation", etc. should all be understood in a broad sense. For example, "connection" can be a fixed connection between multiple objects, a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects, or an indirect connection between multiple objects through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances of the above data.

[0044] In the claims, the specification and the drawings of the present invention, the description of terms such as "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In the claims, the specification and the drawings of the present invention, the schematic representation of the above terms does not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0045] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for capacitor arrangement based on thermal modeling technology, characterized in that, Including: Obtaining the loss factor parameters of the first capacitor and the second capacitor; Obtaining the thermal resistance parameters of the first capacitor and the second capacitor; Based on the loss factor parameters, obtaining the power loss parameters of the first capacitor and the second capacitor; Based on the preset quantities of the first capacitor and the second capacitor, arranging the first capacitor and the second capacitor through a preset layout to obtain various capacitor distribution modes; Based on the power loss parameters, respectively obtaining the average core temperatures of various capacitor distribution modes; Selecting the capacitor distribution mode corresponding to the minimum average core temperature to arrange the capacitors; Wherein, the thermal resistance parameters include the core-shell thermal resistance and the shell-environment thermal resistance.

2. The method for arranging capacitors based on thermal modeling technology according to claim 1, wherein Based on the loss factor parameters, obtaining the power loss parameters of the first capacitor and the second capacitor, including: Obtaining the equivalent resistance values of the first capacitor and the second capacitor; Obtaining the passing current values of the first capacitor and the second capacitor; Based on the passing current values and the equivalent resistance values, obtaining the power loss parameters.

3. The method for capacitor layout based on thermal modeling technology according to claim 1, wherein The obtaining the thermal resistance parameters of the first capacitor and the second capacitor includes: Obtaining the core-shell thermal resistance of the first capacitor and the second capacitor; Based on the cooling method of the first capacitor, obtaining the shell-environment thermal resistance of the first capacitor; Based on the cooling method of the second capacitor, obtaining the shell-environment thermal resistance of the second capacitor.

4. The method for arranging capacitors based on thermal modeling technology according to claim 1, wherein The arranging the first capacitor and the second capacitor through a preset layout based on the preset quantities of the first capacitor and the second capacitor to obtain various capacitor distribution modes includes: Through the preset layout, obtaining the preset arrangement positions of the capacitors; Based on the preset quantities of the first capacitor and the second capacitor, obtaining various capacitor distribution modes through the permutation and combination method.

5. The method for capacitor arrangement based on thermal modeling technology according to claim 3, wherein, The respectively obtaining the average core temperatures of various capacitor distribution modes based on the power loss parameters includes: Based on the distance between adjacent capacitors, obtaining the coupling thermal resistance between adjacent capacitors; Based on the power loss parameters, calculating the capacitor shell temperature; Based on the capacitor shell temperature, the coupling thermal resistance and the power loss, calculating the capacitor core temperature; Based on all the capacitor core temperatures of the current capacitor distribution mode, obtaining the average core temperature; Wherein, the capacitor shell temperature includes the shell temperature of the first capacitor and the shell temperature of the second capacitor.

6. The method for arranging capacitors based on thermal modeling technology according to claim 5, wherein The calculating the capacitor shell temperature based on the power loss parameters includes: Obtaining the ambient temperature; Based on the ambient temperature, the power loss parameters, the coupling thermal resistance and the shell-environment thermal resistance, obtaining the capacitor shell temperature.

7. A computer-readable storage medium, on which a program or instruction is stored, characterized in that When the program or the instruction is executed by a processor, the product evaluation method based on ability quantification according to any one of claims 1 to 6 is implemented.

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