Neural network circuit based on resistive random access memory
Through the neural network circuit based on the resistive variable memory, the isolation conversion module and current mirroring unit are used to solve the problem of large peripheral circuit area and high power consumption in the integrated memory and computing architecture, and a neural network circuit with high integration, low energy consumption and low latency are realized, which improves the computing efficiency.
Patent Information
- Application Number
- CN202510348893.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2025-07-18
AI Technical Summary
In the existing integrated storage and computing architecture, the peripheral circuit area is large and the power consumption is high. The analog-to-digital converter leads to low computing efficiency, making it difficult to achieve neural network circuits with high integration, low energy consumption and low latency.
The neural network circuit based on the resistive variable memory is adopted, and the storage array is connected through the isolation conversion module, which eliminates the analog-to-digital converter, and uses the current mirror unit and the inverting unit to achieve proportional signal scaling and isolation, reducing the scale of the peripheral circuit.
It realizes high-integration, low-power, and low-latency neural network circuits without analog-to-digital converters, adapts to the expansion of neural networks of different scales and improves computing efficiency.
Smart Images
Figure CN120340563A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the fields of microelectronics technology and semiconductor integrated circuits, and specifically to a neural network circuit based on a resistive random access memory, which is applicable to the hardware integration implementation of a neural network in a memory-computation integrated architecture. Background Art
[0002] In the era of big data, technologies such as artificial intelligence and neural networks have developed rapidly. Problems such as the "memory wall" and "energy consumption wall" of the traditional von Neumann architecture have greatly restricted the further improvement of computing power. The memory-computation integrated architecture combines storage units and computing units, saving the time and power consumption of frequent data transfer between the processor and the memory, and is considered an effective way to break through the current von Neumann bottleneck. In the memory-computation architecture, the memory array simultaneously undertakes the functions of computing and storage, and generally performs computations by applying voltage signals and taking its current as the result of the product-sum addition. In existing memory-computation architecture chips, the area of the peripheral circuit is generally several times or even more than a dozen times that of the storage array, and the power consumption exceeds 60% of the total computing power consumption. A large number of analog-to-digital converters and their attached operational amplifier groups are used in the peripheral circuit, resulting in a large amount of power consumption and area loss; the reuse of a small number of modules will cause additional data delays and reduce the computing efficiency. This problem has gradually become a new bottleneck for improving performance and computing power. Therefore, it is of great significance for the development of memory-computation integrated technology and the improvement of computing power to construct a memory-computation integrated circuit that integrates a highly integrated, low-power, low-latency, and flexibly configurable storage array and peripheral circuit starting from the basic circuit structure. Summary of the Invention
[0003] Aiming at the defects of the prior art, the present invention provides a neural network circuit based on a resistive random access memory. The circuit connects different storage arrays through an isolation conversion module to form a basic neural network signal transmission circuit; and programs the storage units separately through a programming unit. The circuit effectively reduces the scale of the peripheral circuit of the memory-computation integrated architecture, reduces the overall power consumption of the hardware memory-computation circuit, improves the computing efficiency, and has good scalability to adapt to neural networks of different scales.
[0004] To solve the above technical problems, the technical solution adopted by the present invention is: a neural network circuit based on a resistive random access memory, including n storage arrays, a programming unit connected to each storage array for programming the storage array, and an isolation conversion module for cascading the n storage arrays together. The isolation conversion module is connected between the front-layer storage array and the rear-layer storage array, and is used to complete the equal-proportion scaling of the input and output of the storage array and the isolation between different storage arrays; where n is a positive integer greater than or equal to one.
[0005] Further, the isolation conversion module includes a current mirror unit. The input end of the current mirror unit is connected to the output end of the previous-layer memory array, and the output end of the current mirror unit is connected to the output end of the subsequent-layer memory array.
[0006] Further, the isolation conversion module includes a current mirror unit and an inverting unit. The input end of the inverting unit is connected to the output end of the previous-layer memory array, the output end of the inverting unit is connected to the input end of the current mirror unit, and the output end of the current mirror unit is connected to the output end of the subsequent-layer memory array.
[0007] Further, the programming unit includes M transistors, where M is the number of columns of the memory array. The control electrode of the transistor is connected to the programming pulse signal, the first signal electrode of the transistor is connected to the programming voltage, and the second signal electrode of the transistor is connected to the control electrode of the memory cell.
[0008] Further, the inverting unit includes a single-stage amplifier circuit and a resistor. The single-stage amplifier circuit includes an input MOS transistor and a load MOS transistor. The input MOS transistor is connected in a common-source configuration, and the load MOS transistor is connected in a diode configuration. Moreover, the input MOS transistor and the load MOS transistor are connected in series between the working voltage and the ground. The gate of the input MOS transistor serves as the input end of the inverting unit and is connected to the input voltage. The connection point between the input MOS transistor and the load MOS transistor is connected to one end of the resistor, and the other end of the resistor serves as the output end of the inverting unit.
[0009] Further, when the number of cascaded layers is small, the load MOS transistor and the resistor of the inverting unit can be omitted to simplify the circuit structure. That is, the inverting unit includes an input MOS transistor. The gate of the input MOS transistor serves as the input end of the inverting unit and is connected to the input voltage, and the drain of the input MOS transistor serves as the output end of the inverting unit.
[0010] Further, take the first one of the n memory arrays as the first memory array. The first memory array and the isolation conversion module are connected to form a voltage-current type connection circuit. The input end of the first memory array is connected to the input voltage signal, and the output end of the first memory array is connected to the input end of the current mirror unit. Take the other memory arrays except the first memory array among the n memory arrays as the second memory arrays. The second memory arrays and the isolation conversion module are connected to form a current-current type connection circuit. The input end of the second memory array is connected to the power supply signal, and the output end of the second memory array is connected to the output end of the current mirror unit.
[0011] Further, the current mirror unit realizes single-channel input single-channel output, single-channel input multi-channel output, multi-channel input single-channel output, and multi-channel input multi-channel output.
[0012] Further, the transistor is a MOS transistor, the control electrode is the gate of the MOS transistor, the first signal electrode is the drain of the MOS transistor, and the second signal electrode is the source of the MOS transistor.
[0013] Further, the memory array is a non-volatile memory array, and the storage medium includes NAND Flash, NOR Flash, ferroelectric memory, and magnetic memory.
[0014] Advantages of the present invention: In the circuit of the present invention, through the conversion of the input voltage - output current and input current - output voltage - output current of the signal type, the cascaded expansion of multi-layer neural network calculation can be realized. The analog-to-digital conversion process of voltage and current signals by sampling circuits such as ADCs is omitted in this circuit, reducing the circuit scale. In the present invention, the memory array adopts a fully parallel mode of calculation, improving the operation efficiency. In the present invention, the power consumption of the peripheral circuit is almost 0 under static working conditions, and all its power consumption is used to complete the calculation function, greatly reducing the power consumption of the memristive neural network circuit. Description of the Drawings
[0015] Figure 1 is the schematic diagram of the neural network circuit in Embodiment 1; Figure 2 is the schematic diagram of the memory array and the programming strobe circuit in Embodiment 1; Figure 3 is the schematic diagram of the memory cell in Embodiment 1; Figure 4 is the schematic diagram of the current mirror unit and the inverting unit in Embodiment 1; Figure 5 is the schematic diagram of the voltage - current type connection circuit in Embodiment 1; Figure 6 is the schematic diagram of the current - current type connection circuit. Detailed Embodiments
[0016] The present invention will be further described below with reference to the drawings and specific embodiments.
[0017] Embodiment 1 This embodiment discloses a neural network circuit based on a resistive random access memory, as Figure 1 shown, including n memory arrays, where n is a positive integer and n ≥ 1. In this embodiment, n = 3, that is Figure 1The first storage array (N*M), the second storage array (M*L), and the third storage array (L*P) in it. The input signal enters from the first storage array and is sequentially transmitted backward, and finally outputs from the third storage array. Each storage array is connected with a programming unit, and the programming unit is used to select a single storage cell and perform programming. An isolation conversion module is provided between two layers of storage arrays, and the isolation conversion module is used to complete the equal-proportion scaling of the input voltage and the output current and the isolation between different storage arrays.
[0018] In this embodiment, the storage array integration structure includes, but is not limited to, memory structures such as crossbar array structures and three-dimensional stacking structures. For example, Figure 2 As shown, the two signal electrodes of each storage cell are connected to the same-name electrodes of adjacent storage cells, and the extending directions of the two electrodes are perpendicular and cross-shaped, forming an array arrangement of N rows and M columns (the first storage array). The storage array is a non-volatile memory, which is composed of multiple storage cells and stores information through physical properties such as the resistance or conductance of the storage cells. The corresponding storage media include, but are not limited to, NAND Flash, NOR Flash, ferroelectric memories, magnetic memories, and memristors.
[0019] For example, Figure 3 As shown, the storage cell in this embodiment is a 1T1R structure composed of a transistor and a memristor, which is a common memristor storage cell and can reduce the leakage current interference caused by adjacent memristor units during the read operation. Figure 3 In it, T1 represents the transistor, and R1 represents the memristor. The source electrode of the transistor T1 is used as the input end of the storage cell to connect the input voltage or current In[1:N]. The gate electrode of the transistor T1 is the control electrode and is connected to the programming circuit. The drain electrode of the transistor T1 is connected to one end of the memristor R1, and the other end of the memristor R1 is used as the output end of the storage cell to output the calculation result. That is, the input voltage In[1:N] is input through the input end In[1:N] of the storage cell, and the output current is used as the calculation result and input to the input end of the current mirror unit at the output end Out[1:M]. In other embodiments, the storage cell can also adopt structures such as 1R, 1T, 1T1R, and 2T2R.
[0020] In this embodiment, the first storage array inputs a voltage signal, and outputs a current signal as the calculation result; for the other storage arrays, inputs a current signal and outputs a voltage signal as the calculation result. Among them, the storage array stores the weight values of the neural network, and its size is related to the neural network design.
[0021] The input signal of the storage array includes the input of a DC or pulsed voltage or current, and parameters such as the frequency, amplitude, and pulse width of the voltage or current signal can be configured; the input signal cooperates with the two signal electrodes of the storage cell to complete at least one of the following operations on the storage cell: data writing, data reading (calculation), and data erasing.
[0022] As Figure 1 shown, the programming unit is connected between the programming pulse and the memory array to perform at least one of the following functions: programming the device, array erasure, introducing feedback according to the network output, and participating in weight update. As Figure 2 shown, the programming unit includes M transistors, where M is the number of columns of the memory array. The control electrodes of the transistors are connected to the programming pulse signal, the first signal electrodes of the transistors are connected to the programming voltage V PE , and the second signal electrodes of the transistors are connected to the control electrodes of the memory cells. In this embodiment, the transistors are NMOS transistors, the control electrodes are the gates of the NMOS transistors, the first signal electrodes are the drains of the NMOS transistors, and the second signal electrodes are the sources of the NMOS transistors. In other embodiments, the transistor type can also be triodes, field effect transistors, flash memories, 2D material field effect transistors, etc.
[0023] The control method of the programming unit is as follows: the control electrode determines the programming time and number through the gating control signal; the programming signal connected to the first electrode cooperates with the input signal of the memory cell to achieve the direction and magnitude of the programming voltage.
[0024] The isolation conversion unit is connected to the outputs and inputs of the front and rear layer memory arrays to complete the equal-proportion scaling of the input voltage and output current and the isolation between different memory arrays. The isolation conversion module has two implementation methods. For example, between the one-to-one connected neural network layers, the isolation conversion module includes a current mirror unit. The input end of the current mirror unit is connected to the output end of the front layer memory array, and the output end of the current mirror unit is connected to the input end of the rear layer memory array. In this embodiment, the isolation conversion module between the first memory array and the second memory array only has the current mirror unit.
[0025] Between the one-to-many or many-to-many connected neural network layers, the isolation conversion module includes a current mirror unit and an inverting unit. The input end of the inverting unit is connected to the output end of the upper layer memory array, the output end of the inverting unit is connected to the input end of the current mirror unit of this layer, and the output end of the current mirror unit is connected to the input end of the rear layer memory array. In this embodiment, the isolation conversion module between the second memory array and the third memory array includes a current mirror unit and an inverting unit.
[0026] In this neural network circuit, the current mirror unit can mirror the output current of the previous layer network to the next layer network as an input signal; the inverting unit can invert the voltage output signal of the previous layer network and convert it into a current signal, and then input it to the next layer network through the current mirror unit. The current mirror unit can achieve single-channel input and single-channel output, single-channel input and multi-channel output, multi-channel input and single-channel output, and multi-channel input and multi-channel output. The current mirror unit can set the transistor conductivity through process or electrical means to complete at least one of the following functions: current equal-ratio amplification and reduction, multi-memory array cascade expansion, and analog neuron activation function. The function of the current mirror unit is to copy the input current to the output end in equal proportion, and its structure is a simple 2T structure, a cascode 4T structure, a low-voltage cascode 4T structure, and other circuit structures that can achieve current copying.
[0027] As Figure 4 shown, part A in the figure represents the current mirror unit, which includes a current mirror circuit and two ports: a current input port and a current output port; the current mirror circuit mirrors and copies the input current and outputs approximately equal current from the output port, including but not limited to current mirror structures such as simple structures, cascode structures, and low-voltage cascode structures that can complete the above functions.
[0028] The current mirror unit can complete the linear addition of currents at the input end and simulate the input accumulation function of neurons within the allowable accuracy; design different copying ratios according to the size of the memory array, and achieve multi-channel copied current output through multi-mirror tubes. Based on the minimum operating voltage at the input end, the current mirror unit can simulate the output of the non-linear activation function of neurons, such as ReLU.
[0029] As Figure 4As shown in the figure, part B in the figure represents an inverting unit. The inverting unit includes a single-stage amplifier circuit, a resistor R2, and two ports: a voltage input terminal and a current output terminal. The single-stage amplifier circuit is composed of an input MOS transistor T2 and a load MOS transistor T3. The input MOS transistor T2 is connected in a common-source configuration, and the load MOS transistor T3 is connected in a diode configuration, which can achieve a linear proportional output of the input and output voltages. The input MOS transistor T2 and the load MOS transistor T3 are connected in series between the operating voltage VDD and the ground. The voltage input terminal of the inverting unit is the gate of the input MOS transistor T2. One end of the resistor R2 is connected to the drain of the input MOS transistor, and the other end of the resistor R2 is the current output terminal of the inverting unit. In this embodiment, two PMOS transistors are used in the inverting unit. The gate of the input MOS transistor is connected to the input voltage as the input terminal of the inverting unit. The source of the input MOS transistor is connected to the operating voltage. The drain of the input MOS transistor is connected to the source of the load MOS transistor. The gate and the drain of the load MOS transistor are connected together and grounded. One end of the resistor is connected to the drain of the input MOS transistor, and the other end of the resistor is used as the output terminal of the inverting unit to output current. In other embodiments, the input MOS transistor and the load MOS transistor can also use NMOS transistors. Depending on whether PMOS or NMOS is used, the specific source-drain connection relationship is slightly different.
[0030] In Figure 4 the circuit shown, the current mirror unit copies the output current of the previous array and uses it as the input signal of the next memory array. At the same time, the input current generates a voltage drop across the memristors in the memory array, causing the voltage at the input terminal of the inverting unit to change, which is the calculation result of this unit. The inverting unit inverts the voltage calculation result and acts on a standard resistor to generate a current linearly related to the input voltage, which is the final output result of this unit.
[0031] In this embodiment, the first memory array is connected to the isolation conversion module to form a voltage-current type connection circuit, as Figure 5 shown. The input terminals of the first memory array are connected to the input voltage signals vin1, vin2,..., vinN. The output terminal of the first memory array outputs a current signal I total , and the current signal I total is connected to the input terminal of the current mirror unit. Figure 5 In 11 、R 12 、...、R 1N constitute the first memory array, and R 21 、R 22 、...、R 2NForm the second storage array. In the circuit structure connecting the first storage array and the second storage array, the multi-input multi-output structure of the current type can be realized by means of the current summation function of the current lines at the input end of the current mirror and the structure capable of multiplexing currents. The accuracy of the current line summation is related to the input impedance of the current mirror circuit. By improving the current mirror structure, adjusting the process, expanding the array scale and other methods, the input impedance of the current mirror circuit can be reduced as much as possible to reduce the current accumulation error.
[0032] In this embodiment, other storage arrays are connected to the isolation conversion module to form a current-current type connection circuit, such as Figure 6 shown. The input end of other storage arrays is connected to the power supply signal, and the output end is connected to the output end of the current mirror unit; wherein, the output end of the current mirror unit is connected to the voltage input end of the inverting unit, and the current output end of the inverting unit is connected to the input end of the next-layer current mirror unit. Due to the complexity of the voltage in the summing circuit, the voltage output has an advantage only in the one-to-one connection circuit. The multi-input multi-output connection in other storage arrays is indispensable. Therefore, by adding an inverting unit to convert the voltage output into a current output, the multi-input multi-output circuit can be completed by means of the current mirror. In different neural network designs, both of these situations will occur, and different circuit structures can be designed according to different neural network structures.
[0033] This embodiment demonstrates the circuit structure and design concept of this circuit design. Without conflict, circuit structures with similar functions or structures can be used to replace the circuit of the embodiment of the present disclosure, and new embodiments can be obtained by combining similar features. The above are all specific implementation manners of the present disclosure. Modifications or improvements made without departing from the circuit structure and design mentioned in the present disclosure fall within the scope protected by the claims of the present disclosure.
Claims
1. A neural network circuit based on a resistive random access memory, characterized in that: It includes n memory arrays, a programming unit connected to each memory array for programming the memory array, and an isolation conversion module for cascading the n memory arrays together. The isolation conversion module is connected between the front-layer memory array and the rear-layer memory array, and is used to complete the equal-proportion scaling of the input and output of the memory array and the isolation between different memory arrays; where n is a positive integer greater than or equal to one.
2. The neural network circuit based on a resistive random access memory according to claim 1, wherein: The isolation conversion module includes a current mirror unit. The input end of the current mirror unit is connected to the output end of the front-layer memory array, and the output end of the current mirror unit is connected to the output end of the rear-layer memory array.
3. The neural network circuit based on a resistive random access memory according to claim 1, wherein: The isolation conversion module includes a current mirror unit and an inverting unit. The input end of the inverting unit is connected to the output end of the front-layer memory array, the output end of the inverting unit is connected to the input end of the current mirror unit, and the output end of the current mirror unit is connected to the output end of the rear-layer memory array.
4. The neural network circuit based on a resistive random access memory according to claim 1, characterized in that: The programming unit includes M transistors, where M is the number of columns of the memory array. The control electrodes of the transistors are connected to the programming pulse signal, the first signal electrodes of the transistors are connected to the programming voltage, and the second signal electrodes of the transistors are connected to the control electrodes of the memory cells.
5. The neural network circuit based on a resistive random access memory according to claim 3, characterized in that: The inverting unit includes a single-stage amplifier circuit and a resistor. The single-stage amplifier circuit includes an input MOS transistor and a load MOS transistor. The input MOS transistor is connected in a common-source configuration, and the load MOS transistor is connected in a diode configuration. And the input MOS transistor and the load MOS transistor are connected in series between the working voltage and the ground. The gate of the input MOS transistor serves as the input end of the inverting unit and is connected to the input voltage. The connection point between the input MOS transistor and the load MOS transistor is connected to one end of the resistor, and the other end of the resistor serves as the output end of the inverting unit.
6. The neural network circuit based on a resistive random access memory according to claim 3, characterized in that: The inverting unit includes an input MOS transistor. The gate of the input MOS transistor serves as the input end of the inverting unit and is connected to the input voltage, and the drain of the input MOS transistor serves as the output end of the inverting unit.
7. The neural network circuit based on a resistive random access memory according to claim 1, wherein: Take the first one of the n memory arrays as the first memory array. The first memory array and the isolation conversion module are connected to form a voltage-current type connection circuit. The input end of the first memory array is connected to the input voltage signal, and the output end of the first memory array is connected to the input end of the current mirror unit; take the other memory arrays except the first memory array among the n memory arrays as the second memory array. The second memory array and the isolation conversion module are connected to form a current-current type connection circuit. The input end of the second memory array is connected to the power supply signal, and the output end of the second memory array is connected to the output end of the current mirror unit.
8. The resistive random access memory-based neural network circuit according to claim 2 or 3, characterized in that: The current mirror unit realizes single-channel input single-channel output, single-channel input multi-channel output, multi-channel input single-channel output, and multi-channel input multi-channel output.
9. The neural network circuit based on a resistive random access memory according to claim 4, wherein: The transistor is a MOS transistor. The control electrode is the gate of the MOS transistor, the first signal electrode is the drain of the MOS transistor, and the second signal electrode is the source of the MOS transistor.
10. The neural network circuit based on a resistive random access memory according to claim 1, wherein: The memory array is a non-volatile memory array, and the storage medium includes NAND Flash, NOR Flash, ferroelectric memory, magnetic memory, memristor.