Memory device, operating method, system, operating method, and storage medium

Abstract

The embodiment of the invention discloses a memory device and an operation method thereof, a memory system and an operation method thereof, and a storage medium, relates to the technical field of semiconductors, and can reduce the burden of data storage of the memory device and the probability of data loss in a power-down process, and improve the data recovery precision. A memory cell of the memory device is programmed to a first memory state after performing a first program operation, and data of the first memory state is programmed to a second memory state after performing a second program operation. The threshold voltage distribution width of the first storage state is greater than the threshold voltage distribution width of the second storage state. And the peripheral circuit is used for responding to re-electrification after power failure in the second programming operation process, and determining a second storage state corresponding to the second programming operation according to the first storage state and the identification information after the first programming operation. And re-performing the second program operation to cause the memory cell to be programmed to the second memory state.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor technology, including but not limited to a memory device and an operation method, a memory system and an operation method, and a storage medium. Background Art

[0002] Semiconductor memories can be roughly divided into two categories depending on whether the stored data is retained when power is lost. These two categories of semiconductor memories are: volatile memories and non-volatile memories. Volatile memories lose the stored data when power is lost, and non-volatile memories retain the stored data when power is lost.

[0003] During the abnormal power-off process of non-volatile memories, there are problems that some coarsely programmed data is not completely stored, and the amount of un-stored coarsely programmed data is large, which affects the efficiency of finely programmed data and causes data loss and inability to recover. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory device and an operation method, a memory system and an operation method, and a storage medium, which can reduce the burden of data storage in the memory device during power-off, reduce the probability of data loss, and are beneficial to improving the data recovery effect.

[0005] In a first aspect, embodiments of the present disclosure provide a memory device. The memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cells. The memory cells are programmed to a first storage state after performing a first programming operation, and the data in the first storage state is programmed to a second storage state after performing a second programming operation; the threshold voltage distribution width of the first storage state is greater than the threshold voltage distribution width of the second storage state.

[0006] The peripheral circuit is coupled to the memory cell array and is configured to: in response to a power-on again after a power-off during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data in the first storage state and identification information after the first programming operation; the identification information is used to characterize the second storage state corresponding to the second programming operation. And re-perform the second programming operation to program the memory cells to the second storage state.

[0007] In some examples, the peripheral circuit is configured to: during the first programming operation, generate the identification information corresponding to the second programming operation for the first storage state; and store the identification information.

[0008] In some examples, the memory cell array includes a plurality of memory blocks, and the peripheral circuit is configured to: store the identification information in a specified memory block among the plurality of memory blocks.

[0009] In some examples, the number of storage bits of the storage unit includes multiple bits, and the multiple storage bits correspond to multiple storage states. The peripheral circuit is configured to: generate the identification information in sequence according to the high-low order of the multiple storage states.

[0010] In some examples, the number of storage bits of the storage unit includes M bits, and the M storage bits correspond to 2M storage states; the identification information includes N-bit data, and the value of the identification information includes 2N data states; both M and N are positive integers.

[0011] The peripheral circuit is configured to: cyclically generate 2N data states corresponding to the value of the identification information in sequence according to the high-low order of the 2M storage states.

[0012] In some examples, the 2M storage states of the storage unit include: 2M first storage states after performing the first programming operation, and the threshold voltage distribution of the first storage state is the first threshold voltage distribution. And, 2M second storage states corresponding to the first storage state after performing the second programming operation; the threshold voltage distribution of the second storage state is the second threshold voltage distribution. Wherein, the range of each of the first threshold voltage distributions is wider than the range of the corresponding second threshold voltage distribution; there is an overlap in the ranges of multiple adjacent first threshold voltage distributions.

[0013] In some examples, the peripheral circuit is configured to: determine the target interval in which the storage unit is located after the first programming operation through P-order read voltages. The P-order read voltages divide the first threshold voltage distributions from the 1st to the 2Mth into P + 1 intervals, and each of the P + 1 intervals includes multiple consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information. P is a positive integer. And reprogram the data of the first storage state in the second programming operation according to the determined target interval and the value of the identification information, so that the storage unit is programmed to the second storage state.

[0014] In some examples, the number of the first threshold voltage distributions included in each interval is the same or different; the ranges of some of the first threshold voltage distributions span both sides of one order of the read voltage.

[0015] In some examples, the P - order read voltages include the 1st - order to the P - order read voltages with gradually increasing voltage values; the P + 1 intervals include the 1st to the P + 1 intervals. The peripheral circuit is configured to perform a first read operation through the 1st - order read voltage, determine the interval where the first storage state of the storage unit is located after the first programming operation and the identification information, perform the second programming operation on the storage units whose first storage state is in the 1st interval, and determine the second storage state corresponding to the first storage state.

[0016] Perform second to (P - 1)th read operations respectively through the 2nd - order to the (P - 1)th - order read voltages, respectively perform the second programming operation on the storage units whose first storage state is in the 2nd to the Pth intervals according to the interval where the first storage state is located and the identification information obtained from the second to the (P - 1)th read operations, and determine the second storage state corresponding to the first storage state.

[0017] And perform the Pth read operation respectively through the Pth - order read voltage, perform the second programming operation on the storage units whose first storage state is in the (P + 1)th interval according to the interval where the first storage state is located and the identification information obtained from the Pth read operation, and determine the second storage state corresponding to the first storage state.

[0018] In some examples, the number of storage bits of the storage unit is 4 bits, 4 storage bits correspond to 16 storage states, and the value of the identification information includes 4 data states.

[0019] The peripheral circuit is configured to determine the target interval where the first storage state of the storage unit is located after the first programming operation through 6 - order read voltages; wherein, the 1st - order read voltage is the median between the 1st and the 4th of the first threshold voltage distributions, the 2nd - order read voltage is the median between the 3rd and the 6th of the first threshold voltage distributions, the 3rd - order read voltage is the median between the 5th and the 8th of the first threshold voltage distributions, the 4th - order read voltage is the median between the 7th and the 10th of the first threshold voltage distributions, the 5th - order read voltage is the median between the 9th and the 12th of the first threshold voltage distributions, and the 6th - order read voltage is the median between the 11th and the 14th of the first threshold voltage distributions.

[0020] If the target interval where the first storage state is located after the first programming operation is the 1st interval and the value of the identification information is the first data state among the 4 data states, then the first storage state is in the 1st of the first threshold voltage distributions; perform the second programming operation on the storage unit so that the first storage state in the 1st of the first threshold voltage distributions is programmed to the second storage state.

[0021] In some examples, the peripheral circuit includes a page buffer, and the page buffer includes a plurality of latches. The peripheral circuit is configured to store the interval where the first storage state obtained in each read operation is located in a first latch among the plurality of latches, and store the identification information in a second latch and a third latch among the plurality of latches. And according to the data in the first latch, the second latch, and the third latch, store the data of the 4-bit first storage state to be programmed in the second programming operation in a fourth latch to a seventh latch among the plurality of latches.

[0022] In some examples, the memory cell array includes a plurality of word lines, and one word line is coupled to a plurality of the memory cells.

[0023] The peripheral circuit is configured to sequentially perform the first programming operation and the second programming operation on the memory cells coupled to the spaced word lines in the order of the physical positions of the plurality of word lines. Wherein, for the plurality of memory cells coupled to the same word line, the second programming operation is performed after the first programming operation.

[0024] In some examples, the plurality of word lines include a Qth word line, a (Q + 1)th word line, a (Q + 2)th word line, and a (Q + 3)th word line that are continuously arranged in physical positions. Q is a natural number.

[0025] The peripheral circuit is configured to perform the first programming operation on the memory cells coupled to the (Q + 1)th word line. After that, perform the second programming operation on the memory cells coupled to the Qth word line. After that, perform the first programming operation on the memory cells coupled to the (Q + 2)th word line. After that, perform the second programming operation on the memory cells coupled to the (Q + 1)th word line. After that, perform the first programming operation on the memory cells coupled to the (Q + 3)th word line. After that, perform the second programming operation on the memory cells coupled to the (Q + 2)th word line.

[0026] After the above-mentioned peripheral circuit controls the memory device to perform the first programming operation, the storage unit is programmed to the first storage state. The first storage state means that the width of the threshold voltage distribution of the storage unit is in a relatively large range. In the case of abnormal power-off of the memory device, the original data cannot be accurately restored only based on the first storage state. Therefore, the peripheral circuit further accurately determines the range of the threshold voltage distribution of the storage unit according to the identification information. The memory device uses a second programming operation to determine the second storage state of the storage unit based on the first storage state and the identification information. Based on this, in the case of abnormal power-off of the memory device, the memory device can obtain the original storage state of the storage unit through the identification information and the first storage state representing the second storage state. In this way, after reprogramming through the control of the peripheral circuit, the original storage state data is restored, and the storage state of the storage unit before abnormal power-off is obtained, improving the accuracy of data restoration and the performance and user experience of the memory device.

[0027] In a second aspect, an embodiment of the present application provides an operation method for a memory device. The operation method includes: in response to a power-on again after a power-off during a second programming operation, determining a second storage state corresponding to the second programming operation according to the data and identification information of the first storage state after the first programming operation. The identification information is used to characterize the second storage state corresponding to the second programming operation.

[0028] The storage unit in the memory device is programmed to the first storage state after performing the first programming operation, and the data of the first storage state is programmed to the second storage state after performing the second programming operation.

[0029] And re-performing the second programming operation so that the storage unit is programmed to the second storage state.

[0030] The beneficial effects of the above-mentioned operation method of the memory device are the same as those of the memory device provided in any of the above examples, and will not be elaborated here.

[0031] In a third aspect, an embodiment of the present application provides a memory system. The memory system includes a memory device and a memory controller.

[0032] The memory device includes a plurality of storage units. The storage unit is programmed to the first storage state after performing the first programming operation, and the data of the first storage state is programmed to the second storage state after performing the second programming operation.

[0033] The memory controller is coupled to the memory device and is configured to: in response to a power-on after a power-off during the second programming operation, determine a second storage state corresponding to the second programming operation according to data and identification information of the first storage state after the first programming operation; the identification information is used to characterize the second storage state corresponding to the second programming operation. And control the memory device to re-perform the second programming operation so that the storage unit is programmed to the second storage state.

[0034] In some examples, the memory controller is configured to: before the first programming operation, send a generation instruction; the generation instruction instructs the memory device to generate the identification information of the second storage state corresponding to the first storage state during the first programming operation. After the first programming operation, store the identification information fed back by the memory device.

[0035] In some examples, the memory system further includes a buffer, and the memory controller is configured to: store the identification information in the memory device; or store the identification information in the buffer and transfer the identification information stored in the buffer to the memory device during a power-off delay period after a power-off. And after the power-on again, read back the identification information in the memory device to the buffer.

[0036] In some examples, the number of storage bits of the storage unit includes multiple bits, and multiple storage bits correspond to multiple storage states. The memory controller is configured to control the memory device to sequentially generate the identification information according to the high-low order of the multiple storage states.

[0037] In some examples, the number of storage bits of the storage unit includes M bits, M storage bits correspond to 2M storage states, the identification information includes N-bit data, and the value of the identification information includes 2N data states. Both M and N are positive integers.

[0038] The memory controller is configured to control the memory device to sequentially and cyclically generate 2N data states corresponding to the value of the identification information according to the high-low order of the 2M storage states.

[0039] In some examples, the 2M storage states of the storage cell include: 2M first storage states after performing the first programming operation, and the threshold voltage distribution of the first storage state is a first threshold voltage distribution. And, 2M second storage states corresponding to the first storage state after performing the second programming operation; the threshold voltage distribution of the second storage state is a second threshold voltage distribution. Wherein, the range of each first threshold voltage distribution is wider than the range of the corresponding second threshold voltage distribution; there is an overlap in the ranges of multiple adjacent first threshold voltage distributions.

[0040] In some examples, the memory controller is configured to: determine a target interval in which the storage cell is located after the first programming operation through a P-level read voltage. The P-level read voltage divides the first threshold voltage distributions from the 1st to the 2Mth into P + 1 intervals, and each of the P + 1 intervals includes multiple consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information. The P is a positive integer.

[0041] And according to the determined target interval and the value of the identification information, reprogram the data of the first storage state in the second programming operation so that the storage cell is programmed to the second storage state.

[0042] In some examples, the number of first threshold voltage distributions included in each interval is the same or different; the ranges of some first threshold voltage distributions span both sides of the first-order read voltage.

[0043] In some examples, the P-level read voltage includes the 1st to the Pth read voltages with gradually increasing voltage values; the P + 1 intervals include the 1st to the P + 1st intervals.

[0044] The memory controller is configured to: perform a first read operation through the 1st-order read voltage to determine the interval in which the first storage state of the storage cell is located after the first programming operation and the identification information, perform the second programming operation on the storage cells whose first storage state is in the 1st interval, and determine the second storage state corresponding to the first storage state.

[0045] Perform second to (P - 1)th read operations respectively through the 2nd to the (P - 1)th read voltages, and respectively perform the second programming operation on the storage cells whose first storage state is in the 2nd to the Pth intervals according to the intervals in which the first storage state is located and the identification information obtained from the second to the (P - 1)th read operations, and determine the second storage state corresponding to the first storage state.

[0046] Performing a P-th read operation through the P-th order read voltage respectively, and according to the interval where the first storage state is located and the identification information obtained from the P-th read operation, performing the second programming operation on the storage cells in which the first storage state is in the P+1 interval, and determining the second storage state corresponding to the first storage state.

[0047] In some examples, the number of storage bits of the storage cell includes 4 bits, and 4 storage bits correspond to 16 storage states, and the values of the identification information include 4 data states.

[0048] The memory controller is configured to: determine the target interval where the first storage state of the storage cell is located after the first programming operation through 6-order read voltages; wherein, the first-order read voltage is the median between the first and fourth first threshold voltage distributions, the second-order read voltage is the median between the third and sixth first threshold voltage distributions, the third-order read voltage is the median between the fifth and eighth first threshold voltage distributions, the fourth-order read voltage is the median between the seventh and tenth first threshold voltage distributions, the fifth-order read voltage is the median between the ninth and twelfth first threshold voltage distributions, and the sixth-order read voltage is the median between the eleventh and fourteenth first threshold voltage distributions.

[0049] If the target interval where the first storage state is located after the first programming operation is the first interval and the value of the identification information is the first data state among the 4 data states, then the first storage state is in the first first threshold voltage distribution; performing the second programming operation on the storage cell so that the first storage state in the first first threshold voltage distribution is programmed to the second storage state.

[0050] In some examples, the memory device further includes a peripheral circuit, the peripheral circuit includes a page buffer, and the page buffer includes a plurality of latches.

[0051] The memory controller is configured to: store the interval where the first storage state obtained from each read operation is located in the first latch among the plurality of latches, and store the identification information in the second latch and the third latch among the plurality of latches.

[0052] According to the data in the first latch, the second latch and the third latch, store the data of the 4-bit first storage state to be programmed in the second programming operation in the fourth latch to the seventh latch among the plurality of latches.

[0053] In some examples, the memory device includes a plurality of word lines, and one word line is coupled to a plurality of the storage cells.

[0054] The memory controller is configured to control the memory device to perform the first programming operation and the second programming operation on the spaced word lines in sequence according to the physical positions of the multiple word lines. Among them, multiple memory cells coupled to the same word line perform the second programming operation after performing the first programming operation.

[0055] In some examples, the multiple word lines include the Qth word line, the (Q + 1)th word line, the (Q + 2)th word line, and the (Q + 3)th word line whose physical positions are continuously set; Q is a natural number.

[0056] The memory controller is configured to control the memory device to perform the first programming operation on the memory cells coupled to the (Q + 1)th word line. After that, perform the second programming operation on the memory cells coupled to the Qth word line. Then, perform the first programming operation on the memory cells coupled to the (Q + 2)th word line. After that, perform the second programming operation on the memory cells coupled to the (Q + 1)th word line. After that, perform the first programming operation on the memory cells coupled to the (Q + 3)th word line. After that, perform the second programming operation on the memory cells coupled to the (Q + 2)th word line.

[0057] The memory cells in the above memory system are programmed to a first storage state under the control of the memory controller after performing the first programming operation. The first storage state means that the width of the threshold voltage distribution of the memory cells is a relatively large range, and the original data cannot be accurately restored only based on the first storage state. For this reason, the memory controller further accurately determines the range of the threshold voltage distribution of the memory cells according to the identification information. The memory device adopts the second programming operation to determine the second storage state of the memory cells through the first storage state and the identification information, obtain the original data before the memory cells are powered off, improve the accuracy of data recovery, and improve the performance and user experience of the memory device.

[0058] In a fourth aspect, an embodiment of the present application further provides an operation method for a memory system. The operation method includes: in response to a power-on again after a power-off during the second programming operation, determining the second storage state corresponding to the second programming operation according to the data programmed after the first programming operation and the identification information; the identification information is used to characterize the second storage state corresponding to the second programming operation.

[0059] The memory cells in the memory device of the memory system are programmed to a first storage state after performing the first programming operation, and the data in the first storage state is programmed to the second storage state after performing the second programming operation.

[0060] and control the memory device to re - perform the second programming operation so that the storage unit is programmed to the second storage state.

[0061] The beneficial effects of the operation method of the above - mentioned memory system are the same as those of the memory system provided in any of the above examples, and will not be elaborated here.

[0062] In a fifth aspect, an embodiment of the present application provides a storage medium. An executable instruction is stored on the storage medium. When the executable instruction is executed, the steps of the operation method of the memory device provided in any example of the second aspect or the memory system provided in any example of the fourth aspect can be implemented.

[0063] The beneficial effects of the storage medium provided in this embodiment are the same as those of the operation method of the memory device provided in any example of the second aspect or the memory system provided in any example of the fourth aspect, and will not be elaborated again. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In the drawings, similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0065] Figure 1 It is a schematic structural diagram of an electronic system provided by an embodiment of the present application;

[0066] Figure 2 It is a schematic structural diagram of a storage medium provided by an embodiment of the present application;

[0067] Figure 3 It is a schematic structural diagram of another storage medium provided by an embodiment of the present application;

[0068] Figure 4 It is a schematic structural diagram of a memory system provided by an embodiment of the present application Figure 1 ;

[0069] Figure 5 It is a schematic structural diagram of a memory system provided by an embodiment of the present application Figure 2 ;

[0070] Figure 6 It is a schematic diagram of the threshold voltage distribution of a storage unit provided by an embodiment of the present application;

[0071] Figure 7 It is a schematic structural diagram of a memory system provided by an embodiment of the present application Figure 3 ;

[0072] Figure 8Schematic diagram of a memory device including a page buffer bank provided by an embodiment of the present application;

[0073] Figure 9 Schematic diagram of a page buffer including a latch provided by an embodiment of the present application;

[0074] Figure 10 Flowchart of an operation method of a memory system provided by an embodiment of the present application;

[0075] Figure 11 Schematic diagram of a memory device provided by an embodiment of the present application Figure 1 ;

[0076] Figure 12 Schematic diagram of a memory device provided by an embodiment of the present application Figure 2 ;

[0077] Figure 13 Schematic diagram of a memory device provided by an embodiment of the present application Figure 3 ;

[0078] Figure 14 Flowchart of an operation method of a memory device provided by an embodiment of the present application. Detailed implementation manners

[0079] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0081] As used in this application, the terms "first", "second" and similar terms do not denote any order, quantity or importance, but are merely used to distinguish different components. Similarly, terms such as "a", "an" or "the" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "comprising" or "including" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" or "joined" are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0082] It should be understood that the phrase "an embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrase "in an embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0083] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including such element.

[0084] To thoroughly understand this application, detailed steps and detailed structures will be presented in the following description to explain the technical solution of this application. The preferred embodiments of this application are described in detail below. However, in addition to these detailed descriptions, this application may have other implementation manners.

[0085] Currently, memories including memory cells of a multi-level storage type store data in a two-step programming manner. For example, the memory cells are first roughly programmed and then finely programmed to store data. That is to say, the effect of storing data is achieved only after the fine programming operation is completed. Among them, the rough programming operation and the fine programming operation operate on different memory pages at the same time, and there is a certain time difference between them.

[0086] In this way, in the case of abnormal power failure of the memory, data backup and recovery are only performed through the error correction codes adopted in some embodiments. If there is a large amount of data for which the coarse programming operation has not been performed, the power failure speed of the memory will be accelerated, affecting the effect of data backup; and for the data that has been subjected to the coarse programming operation of the memory but not the fine programming operation, some of the data that has only been coarsely programmed will be lost, and the corresponding recovery data cannot be obtained, reducing the user experience.

[0087] It should be noted that the operation of data programming includes a coarse programming operation (coarse program operation) and a fine programming operation (fine program operation). The coarse programming operation can form a rough threshold voltage distribution. The fine programming operation can finely narrow the threshold voltage distribution formed by the coarse programming operation.

[0088] For this reason, as Figure 1 shown, an embodiment of the present application shows an electronic system 10. By way of example, the electronic system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 32 therein.

[0089] Please continue to refer to Figure 1 , the electronic system 10 may include a host 20 and a memory system 30.

[0090] The host 20 may be a processor of the electronic device (for example, a central processing unit (CPU) or a system on chip (SoC) (for example, an application processor (AP))). The host 20 may be configured to send data to the memory system 30 or receive data from the memory system 30.

[0091] The memory system 30 includes a memory controller 31 and one or more memory devices 32, as well as other integrated circuit structures for signal transmission. Among them, the memory controller 31 and one or more memory devices 32 may be integrally packaged in the same storage medium 40 (refer to Figure 2 and Figure 3 ). In this way, it is beneficial to apply the memory system 30 to different types of terminal electronic products.

[0092] Exemplarily, the types of the storage medium 40 integrating the integrated memory controller 31 and one or more memory devices 32 include: Universal Flash Storage (UFS), Embedded MultiMedia Card (eMMC), or other types of storage devices.

[0093] There are multiple ways of integrating the integrated circuit of the storage medium 40. For example, it can be a memory card 410 formed by integrating a single memory device 32 and a memory controller 31 (as Figure 2 shown), or it can be a solid-state drive (SSD) 420 formed by integrating multiple memory devices 32 and a memory controller 31 (as Figure 3 shown).

[0094] Exemplarily, the memory card 410 can include one or more types of storage devices such as a Personal Computer Memory Card International Association (PC) card, a CompactFlash (CF) card, a SmartMedia (SM) card, a Memory Stick, a Multi-Media Card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMC micro), a Secure Digital (SD) card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), and UFS.

[0095] Wherein, please continue to refer to Figure 2 , the memory card 410 further includes a memory card connector 41. The memory card connector 41 is configured to couple the memory card 410 to a host (e.g., Figure 1 the host 20 in). For example, the memory card connector 41 includes a gold finger.

[0096] Alternatively, please continue to refer to Figure 3 , the SSD 420 further includes an SSD connector 41. The SSD connector 41 is configured to couple the SSD 420 to a host (e.g., Figure 1 the host 20 in). For example, the SSD connector 41 includes a gold finger.

[0097] It can be understood that the storage capacity and / or operating speed of the SSD 420 is greater than that of the memory card 410.

[0098] The memory controller 31 and the memory device 32 (and the host 20) integrated in the same storage device are coupled, and the memory controller 31 is configured to control the memory device 32.

[0099] Exemplarily, the memory controller 31 can be designed to operate in a low-duty-cycle environment. For example, it is used to operate in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive; or to operate in other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. Again exemplarily, the memory controller 31 can be designed to operate in a high-duty-cycle environment, for example, to operate in a Solid State Drive (SSD) or an embedded Multi-Media Card (eMMC). Among them, the SSD or eMMC can be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0100] Furthermore, the memory controller 31 can manage the data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control operations such as reading, erasing, and programming of the memory device 32; it can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; it can also be configured to process the Error Checking and Correction (ECC) of the data read from or written to the memory device 32.

[0101] In addition, the memory controller 31 can also perform any other suitable functions, such as formatting the memory device 32, or communicating with external devices according to a specific communication protocol (for example, Figure 1communicate with the host 20. For example, the memory controller 31 can communicate with the host 20 through at least one of various interface protocols. Among them, the interface protocols include one or more of the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the Peripheral Component Interconnect Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Development Equipment (IDE) protocol, the Firewire protocol, etc.

[0102] The above memory device 32 can include, but is not limited to, one or more memories such as NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0103] Based on the above description, in this application, the memory device 32 is a semiconductor memory. For example, a solid-state electronic device (such as a NAND-type memory) for storing data information made by semiconductor integrated circuit technology is used as an example for the description of subsequent embodiments. The subsequent examples of this application do not limit the specific internal structures of the memory device 32 and the memory controller 31.

[0104] It can be understood that, for the convenience of distinguishing the adaptation adjustments made by the memory device 32 and the memory controller 31 when applied to different memory systems 30. For example, based on the various structures of the memory device 32 exemplified in the foregoing content, and the generation logic of the control instructions output by the memory controller 31 to the memory device 32, the memory device (such as a NAND-type memory) provided in the subsequent examples of this application will be described by taking the memory device 60 applied to the memory system 50 as an example.

[0105] To solve the above problems, in some embodiments, as Figures 4 - 9 shown, an embodiment of this application provides a memory system 50.

[0106] As Figure 4 shown, the memory system 50 includes a memory device 60 and a memory controller 51.

[0107] The memory device 60 includes a plurality of memory cells 611. The memory cells 611 are programmed to a first storage state after performing a first programming operation, and the data in the first storage state is programmed to a second storage state after performing a second programming operation.

[0108] The memory controller 51 is coupled to the memory device 60 and is configured to: in response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data in the first storage state and the identification information after the first programming operation. The identification information is used to characterize the second storage state corresponding to the second programming operation. And control the memory device 60 to perform the second programming operation again, so that the memory cells 611 are programmed to the second storage state.

[0109] Exemplarily, the first programming operation includes a rough programming operation, and the second programming operation includes a fine programming operation.

[0110] The memory cells 611 in the above memory system 60 are programmed to a first storage state under the control of the memory controller 51 after performing the first programming operation. The first storage state means that the width of the threshold voltage distribution of the memory cells 611 is in a relatively large range, and the original data cannot be accurately restored only based on the first storage state. For this reason, the memory controller 51 further accurately determines the range of the threshold voltage distribution of the memory cells 611 according to the identification information. The memory device 60 uses the second programming operation to determine the second storage state of the memory cells 611 through the first storage state and the identification information. Based on this, in the case of an abnormal power failure of the memory device 60, the memory device 60 can obtain the original storage state of the memory cells 611 through the memory cells 611 in the second storage state, and then realize data recovery through reprogramming of the original storage state to obtain the storage state of the memory cells 611 before the abnormal power failure.

[0111] It can be seen that, compared with the data of the storage state of the storage unit 611 determined only by the first storage state, the data determined by the second storage state obtained from the first storage state and the identification information in the embodiments of the present application is more accurate, and can restore the original data of the storage unit 611 that was not stored during the power-down process, improving the performance and user experience of the memory device 60.

[0112] In some examples, the memory controller 51 is configured to send a generation instruction before the first programming operation. The generation instruction instructs the memory device 60 to generate identification information of the second storage state corresponding to the second programming operation during the first programming operation.

[0113] After the first programming operation, the identification information fed back by the memory device 60 is stored.

[0114] It can be understood that there is a one-to-one correspondence relationship among the "first storage state", the "second storage state" and the "identification information", and this relationship is preset (similar to a mapping table), and the "identification information" that can represent the second storage state corresponding to the "first storage state" is screened through the "generation instruction".

[0115] In this way, before the first programming operation, the memory controller 51 sends a generation instruction to control the memory device 60 to generate, specifically, the identification information corresponding to the first storage state, and stores the identification information for subsequent use in the second programming operation.

[0116] In some examples, as Figure 4 shown, the memory device 60 includes a plurality of word lines WL, and one word line WL is coupled to a plurality of storage units 611.

[0117] The memory controller 51 is configured to: control the memory device 60 to perform the first programming operation and the second programming operation on the spaced word lines WL in sequence according to the physical position order of the plurality of word lines WL. Among them, the plurality of storage units 611 coupled to the same word line WL perform the second programming operation after the first programming operation.

[0118] Exemplarily, please continue to refer to Figure 4 , the plurality of word lines WL include the Qth word line WL, the (Q + 1)th word line WL, the (Q + 2)th word line WL, and the (Q + 3)th word line WL whose physical positions are continuously set. Q is a natural number.

[0119] The memory controller 51 is configured to: control the memory device 60 to perform a first programming operation on the memory cell 611 coupled to the (Q + 1)-th word line WL; thereafter, perform a second programming operation on the memory cell 611 coupled to the Q-th word line WL; thereafter, perform a first programming operation on the memory cell 611 coupled to the (Q + 2)-th word line WL; thereafter, perform a second programming operation on the memory cell 611 coupled to the (Q + 1)-th word line WL; thereafter, perform a first programming operation on the memory cell 611 coupled to the (Q + 3)-th word line WL; thereafter, perform a second programming operation on the memory cell 611 coupled to the (Q + 2)-th word line WL.

[0120] As Figure 5 shown, in some examples, the memory system 50 further includes a buffer 52. The buffer 52 is configured to temporarily store data.

[0121] The memory controller 51 is configured to: store identification information in the memory device 60; or, store the identification information in the buffer 52 and transfer the identification information stored in the buffer 52 to the memory device 60 during a power-down delay period after power-down; and after power-on again, read back the identification information in the memory device 60 to the buffer 52.

[0122] In this way, the identification information can be stored in the cache circuit structure inside the memory device 60, or can be stored in the buffer 52 in the memory system 50, and the information is transmitted through the memory controller 51, which can be set according to actual requirements, improving the application scope of the memory device 60 and the memory system 50.

[0123] Based on the correspondence relationship between the "first storage state", "second storage state" and "identification information" mentioned above, the specific "identification information" is related to the storage state of the memory cell 611. The following examples exemplarily illustrate the determination methods of the "identification information" and the "second storage state".

[0124] In some examples, the storage bits of the memory cell 611 include multiple bits, and the multiple storage bits correspond to multiple storage states.

[0125] The memory controller 51 is configured to: control the memory device 60 to generate identification information in sequence according to the high-low order of the multiple storage states.

[0126] Exemplarily, the storage bits of the memory cell 611 are related to the storage type. The storage type of the memory cell 611 includes any one of single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC), etc.

[0127] For example, the storage type of the storage unit 611 is (Multi Level Cell, MLC), the number of storage bits is 2 bits, and the number of storage states is 2 2 types. For example, the storage states include four types: "00", "01", "10", and "11". The memory controller 51 controls the memory device 60 to generate identification information in sequence according to the high and low levels of the 4 storage states. For example, the identification information "0" corresponding to the "00" storage state, the identification information "1" corresponding to the "01" storage state, the identification information "2" corresponding to the "10" storage state, and the identification information "3" corresponding to the "11" storage state.

[0128] In some examples, the number of storage bits of the storage unit 611 includes M bits, and the M storage bits correspond to 2 M storage states, the identification information includes N-bit data, and the values of the identification information include 2 N data states. Both M and N are positive integers.

[0129] The memory controller 51 is configured to: control the memory device 60 to sequentially and cyclically generate 2 M data states corresponding to the values of the identification information according to the high and low order of the 2 N storage states.

[0130] Exemplarily, as Figure 6 shown, the storage type of the storage unit 611 is QLC, the number of storage bits is 4 bits, and the number of storage states is 2 4There are 16 states. For example, the storage states include "1111", "1110", "0110", "0010", "0011", "0001", "0000", "0100", "1100", "1000", "1010", "1011", "1001", "1101", "0101", and "0111". The memory controller 51 controls the memory device 60 to sequentially generate identification information corresponding to the 16 storage states in a cyclic manner according to the high and low levels of the 16 storage states. For example, the data state of the identification information corresponding to the "1111" storage state is "0", the data state of the identification information corresponding to the "1110" storage state is "1", the data state of the identification information corresponding to the "0110" storage state is "2", and the data state of the identification information corresponding to the "0010" storage state is "3"; the data state of the identification information corresponding to the "0011" storage state is "0", the data state of the identification information corresponding to the "0001" storage state is "1", the data state of the identification information corresponding to the "0000" storage state is "2", and the data state of the identification information corresponding to the "0100" storage state is "3"; the data state of the identification information corresponding to the "1100" storage state is "0", the data state of the identification information corresponding to the "1000" storage state is "1", the data state of the identification information corresponding to the "1010" storage state is "2", and the data state of the identification information corresponding to the "1011" storage state is "3"; the data state of the identification information corresponding to the "1001" storage state is "0", the data state of the identification information corresponding to the "1101" storage state is "1", the data state of the identification information corresponding to the "0101" storage state is "2", and the data state of the identification information corresponding to the "0111" storage state is "3".

[0131] The 2 M storage states of the above storage unit 611 include: 2 M first storage states after performing the first programming operation, and the threshold voltage distribution of the first storage states is the first threshold voltage distribution. And, 2 M second storage states corresponding to the first storage states after performing the second programming operation; the threshold voltage distribution of the second storage states is the second threshold voltage distribution.

[0132] Among them, the range of each first threshold voltage distribution is wider than the range of the corresponding second threshold voltage distribution. There is an overlap in the ranges of adjacent multiple first threshold voltage distributions.

[0133] That is to say, the original data of the memory cell 611 cannot be accurately restored based only on the first storage state. The memory device 60 uses a second programming operation to determine the second storage state of the memory cell 611 based on the first storage state and identification information. Based on this, in the case of abnormal power-off of the memory device 60, the memory device 60 can obtain the original storage state of the memory cell 611 through the memory cell in the second storage state, and then realize data restoration after reprogramming through the original storage state, and obtain the storage state of the memory cell 611 before abnormal power-off.

[0134] It should be noted that the identification information includes N-bit data, and the value of N is related to the number of intervals divided by the threshold voltage distribution of the memory cell 611, so as to avoid the same value of the identification information existing in the same interval, so that it is impossible to determine which threshold voltage range corresponds to the second storage state of the first storage state according to the identification information.

[0135] For example, in the case where two or more adjacent threshold voltage distributions overlap, the same read voltage value will read at least two threshold voltage distributions that meet the conditions. In this way, in the subsequent data restoration process, it is impossible to determine which threshold voltage range the storage state of the current memory cell 611 is in. Based on this, N-bit identification information needs to be set to distinguish the threshold voltage distributions with overlapping ranges, so as to improve the accuracy of data restoration.

[0136] In some examples, the memory controller 51 is configured to: determine the target interval in which the memory cell is located after the first programming operation through the P-order read voltage. The P-order read voltage divides the first to the second M first threshold voltage distributions into P + 1 intervals. Each of the P + 1 intervals includes a plurality of consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information. P is a positive integer.

[0137] And according to the determined target interval and the value of the identification information, reprogram the data in the first storage state in the second programming operation, so that the memory cell 611 is programmed to the second storage state.

[0138] The above-mentioned P-order read voltage includes the first-order to the P-order read voltages with gradually increasing voltage values. The P + 1 intervals include the first to the P + 1 intervals.

[0139] It can be understood that the P-order read voltage can enable the identification information corresponding to the threshold voltage distribution in one interval to be different. In this way, after determining the target interval where the first storage state of the currently read memory cell 611 is located, the second storage state can be directly determined according to the identification information, improving the efficiency and accuracy of the second programming operation and the accuracy of data restoration.

[0140] Exemplarily, as Figure 6 shown, the storage type of the storage unit 611 is QLC, including sixteen storage states. The P-bit 6 and the 6th order read voltage divide the 16 first threshold voltage distributions into 7 intervals. Among them, the value of the 6th order read voltage is determined based on the values of the first threshold voltage distributions from low to high. For example, the first first threshold voltage distribution corresponds to the erased state of the storage unit 611, and the values of the second to the fourth first threshold voltage distributions determine the 1st order read voltage, the values of the third to the sixth first threshold voltage distributions determine the 2nd order read voltage, the values of the fifth to the eighth first threshold voltage distributions determine the 3rd order read voltage, the values of the seventh to the tenth first threshold voltage distributions determine the 4th order read voltage, the values of the ninth to the twelfth first threshold voltage distributions determine the 5th order read voltage, and the values of the eleventh to the fourteenth first threshold voltage distributions determine the 6th order read voltage.

[0141] The memory controller 51 is configured to: perform a first read operation through the 1st order read voltage to determine the interval and identification information in which the first storage state of the storage unit 611 is located after the first programming operation, perform a second programming operation on the storage unit 611 whose first storage state is in the 1st interval, and determine the second storage state corresponding to the first storage state.

[0142] Perform second to (P - 1)th read operations respectively through the 2nd to (P - 1)th order read voltages, and respectively perform a second programming operation on the storage units whose first storage state is in the 2nd to Pth intervals according to the interval and identification information of the first storage state obtained from the second to (P - 1)th read operations, and determine the second storage state corresponding to the first storage state.

[0143] And perform the Pth read operation through the Pth order read voltage, perform a second programming operation on the storage units whose first storage state is in the (P + 1)th interval according to the interval and identification information of the first storage state obtained from the Pth read operation, and determine the second storage state corresponding to the first storage state.

[0144] Exemplarily, as Figure 6 shown, the number of storage bits of the storage unit 611 includes 4 bits, the 4 storage bits correspond to 16 storage states, and the value of the identification information includes 4 data states.

[0145] The memory controller 51 is configured to determine the target interval in which the first storage state of the memory cell 611 is located after the first programming operation through six-order read voltages. Among them, the first-order read voltage is the median between the first and fourth first threshold voltage distributions, the second-order read voltage is the median between the third and sixth first threshold voltage distributions, the third-order read voltage is the median between the fifth and eighth first threshold voltage distributions, the fourth-order read voltage is the median between the seventh and tenth first threshold voltage distributions, the fifth-order read voltage is the median between the ninth and twelfth first threshold voltage distributions, and the sixth-order read voltage is the median between the eleventh and fourteenth first threshold voltage distributions.

[0146] If the target interval in which the first storage state is located after the first programming operation is the first interval and the value of the identification information is the first data state among the four data states (e.g., "0"), then the first storage state is in the first first threshold voltage distribution. A second programming operation is performed on the memory cell 611 to program the first storage state in the first first threshold voltage distribution to the second storage state.

[0147] If the target interval in which the first storage state is located after the first programming operation is the first interval and the value of the identification information is the second data state among the four data states (e.g., "1"), then the first storage state is in the second first threshold voltage distribution. A second programming operation is performed on the memory cell 611 to program the first storage state in the second first threshold voltage distribution to the second storage state.

[0148] If the target interval in which the first storage state is located after the first programming operation is the first interval and the value of the identification information is the third data state among the four data states (e.g., "2"), then the first storage state is in the third first threshold voltage distribution. A second programming operation is performed on the memory cell 611 to program the first storage state in the third first threshold voltage distribution to the second storage state.

[0149] If the target interval in which the first storage state is located after the first programming operation is the second interval and the value of the identification information is the fourth data state among the four data states (e.g., "3"), then the first storage state is in the fourth first threshold voltage distribution. A second programming operation is performed on the memory cell 611 to program the first storage state in the fourth first threshold voltage distribution to the second storage state.

[0150] If the target interval where the first storage state is located after the first programming operation is the second interval and the value of the identification information is the first data state among the four data states (for example, "0"), then the first storage state is in the fifth first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the fifth first threshold voltage distribution to the second storage state.

[0151] If the target interval where the first storage state is located after the first programming operation is the third interval and the value of the identification information is the second data state among the four data states (for example, "1"), then the first storage state is in the sixth first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the sixth first threshold voltage distribution to the second storage state.

[0152] If the target interval where the first storage state is located after the first programming operation is the third interval and the value of the identification information is the third data state among the four data states (for example, "2"), then the first storage state is in the seventh first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the seventh first threshold voltage distribution to the second storage state.

[0153] If the target interval where the first storage state is located after the first programming operation is the fourth interval and the value of the identification information is the fourth data state among the four data states (for example, "3"), then the first storage state is in the eighth first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the eighth first threshold voltage distribution to the second storage state.

[0154] If the target interval where the first storage state is located after the first programming operation is the fourth interval and the value of the identification information is the first data state among the four data states (for example, "0"), then the first storage state is in the ninth first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the ninth first threshold voltage distribution to the second storage state.

[0155] If the target interval where the first storage state is located after the first programming operation is the fifth interval and the value of the identification information is the second data state among the four data states (for example, "1"), then the first storage state is in the tenth first threshold voltage distribution. A second programming operation is performed on the storage unit 611 to program the first storage state in the tenth first threshold voltage distribution to the second storage state.

[0156] If the target interval where the first storage state is located after the first programming operation is the 5th interval and the value of the identification information is the third data state among the 4 data states (e.g., "2"), then the first storage state is in the 11th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 11th first threshold voltage distribution to the second storage state.

[0157] If the target interval where the first storage state is located after the first programming operation is the 6th interval and the value of the identification information is the fourth data state among the 4 data states (e.g., "3"), then the first storage state is in the 12th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 12th first threshold voltage distribution to the second storage state.

[0158] If the target interval where the first storage state is located after the first programming operation is the 6th interval and the value of the identification information is the first data state among the 4 data states (e.g., "0"), then the first storage state is in the 13th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 13th first threshold voltage distribution to the second storage state.

[0159] If the target interval where the first storage state is located after the first programming operation is the 7th interval and the value of the identification information is the second data state among the 4 data states (e.g., "1"), then the first storage state is in the 14th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 14th first threshold voltage distribution to the second storage state.

[0160] If the target interval where the first storage state is located after the first programming operation is the 7th interval and the value of the identification information is the third data state among the 4 data states (e.g., "2"), then the first storage state is in the 15th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 15th first threshold voltage distribution to the second storage state.

[0161] If the target interval where the first storage state is located after the first programming operation is the 7th interval and the value of the identification information is the fourth data state among the 4 data states (e.g., "3"), then the first storage state is in the 16th first threshold voltage distribution. A second programming operation is performed on the storage cell 611 to program the first storage state in the 16th first threshold voltage distribution to the second storage state.

[0162] In some examples, the number of first threshold voltage distributions included in each interval is the same or different. The ranges of some of the first threshold voltage distributions span both sides of the first-order read voltage.

[0163] Exemplarily, as Figure 6 shown, the first interval includes three first threshold voltage distributions, the second to the sixth intervals each include two first threshold voltage distributions, and the seventh interval includes three first threshold voltage distributions. Since the range of the first threshold voltage distribution is relatively large, there may be a price difference region value between two or three adjacent first threshold voltage distributions. Therefore, when determining the first-order read voltage, the ranges of some first threshold voltage distributions straddle both sides of the first-order read voltage.

[0164] Based on this, the identification information of the first threshold voltage distributions set in the same region is different; and the identification information of the first threshold voltage distributions straddling both sides of the first-order read voltage is different from that of the first threshold voltage distributions existing only in one interval. When the storage state of the storage unit 611 is determined to be in the target region through the read voltage, a second programming operation can be performed according to the first threshold voltage distribution and the identification information to obtain the second storage state.

[0165] As Figure 7 shown, in some examples, the memory device 60 further includes a peripheral circuit 62, and the peripheral circuit 62 includes a page buffer 621. Further, as Figure 8 shown, the peripheral circuit 62 may include a page buffer group composed of multiple page buffers 621. The page buffer group can be coupled to the memory cell array 61 via multiple bit lines (BL1 to BLk). One page buffer 621 is coupled to the memory cell array 61 via one bit line. For example, as Figure 8 shown, multiple page buffers 621 can be respectively coupled to the memory cell array 61 via the corresponding bit lines BL1 to BLk.

[0166] Exemplarily, as Figure 7 shown, the page buffer 621 includes multiple latches 6210. By way of example, the latches 6210 in the page buffer 621 of the memory cell 611 may include a sense latch (S Latch), a low voltage latch (LVT Latch), four data latches (D Latch), and a cache latch (C Latch).

[0167] Among them, the sensing latch S Latch can be used to store prohibited information and verification information from the verification operation. The low-voltage latch LVT Latch can be used to store prohibited information and adjusted verification information from the verification operation. The data latch D Latch can be used to latch the data of a specified page of the storage unit. The cache latch C Latch is used for data exchange with the outside. For example, first transfer the external data to the cache latch C Latch, and then transfer it to the sensing latch S Latch through the cache latch C Latch. Another example is to transfer the data in the sensing latch S Latch to the cache latch C Latch, and then transfer it to the outside through the cache latch C Latch. The outside can be the memory controller 31 or the host 20, etc. Another example is that the cache latch C Latch can also be used for other functions, such as temporarily storing verification information. The present application does not specifically limit the type and quantity of the latches 6210 in the page buffer 621, and can be set according to actual needs.

[0168] As Figure 9 shown, the memory controller 51 is configured to store the interval where the first storage state obtained by each read operation is located in the first latch 6211 among the multiple latches 6210, and store the identification information in the second latch 6212 and the third latch 6213 among the multiple latches 6210.

[0169] According to the data in the first latch 6211, the second latch 6212, and the third latch 6213, store the 4-bit data of the first storage state to be programmed in the second programming operation in the fourth latch 6214 to the seventh latch 6217 among the multiple latches 6210.

[0170] Exemplarily, please continue to refer to Figure 9 , the storage type of the storage unit 611 is QLC, and the storage bit number is 4 bits. For example, the storage unit 611 stores 4 pages of data, namely Lower Page (LP), Middle Page (MP), Upper Page1 (UP1), and Upper Page2 (UP2). In the storage unit 611 where the read operation is currently being executed, the cache latch can be used to store the data of LP. Then, after the cache latch transfers the data of LP to the first data latch, the cache latch can be used to store the data of MP. Then, after the cache latch transfers the data of MP to the second data latch, the cache latch can be used to store the data of UP1. Then, after the cache latch transfers the data of UP1 to the third data latch, the cache latch can be used to store the data of UP2.

[0171] The above-mentioned memory controller 51 stores the interval where the first storage state obtained in each read operation is located (for example, multiple intervals divided by read voltages) in the first latch 6211 (for example, a sense latch).

[0172] The identification information characterizing the second storage state based on the first storage state is stored in the second latch 6212 (for example, a low-voltage latch) and the third latch 6213 (for example, a low-voltage latch).

[0173] According to the data in the first latch 6211, the second latch 6212, and the third latch 6213, the data of the 4-bit first storage state to be programmed in the second programming operation (for example, the data of LP, MP, UP1, and UP2) is stored in the fourth latch 6214 to the seventh latch 6217 (for example, 4 data latches).

[0174] In this way, some logical operations can be performed, such as determining the target interval and the second storage state of the storage unit 611 by combining the identification information and the first storage state.

[0175] In addition, the timing for the cache latch to release data can be set, enabling the first latch 6211 to the fourth latch 6212 to obtain more storage states of the storage unit 611 and increasing the amount of data recovered subsequently.

[0176] It should be noted that in the above example, 7 latches are used in the process of the memory controller 51 performing a read operation. In the case where the amount of stored data is small, the number of memories 6210 of the storage unit 611 can also be less than 7. For example, if the amount of stored data is small, the amount of corresponding identification information is also small, and the identification information can be stored in one latch 6210.

[0177] In addition, based on the method for storing data adopted in the embodiments of the present application, the number of data bits that the latch 6210 can store can be different according to the different storage types of the storage unit 611. For example, in the embodiments of the present application, the storage type of the storage unit 611 is QLC, and the first latch 6211 stores the first stored state data (for example, QLC has a first stored state of 4 bits); the second latch 6212 and the third latch 6213 store the identification information of all data (for example, one identification information is 1 bit, and 4 types of identification information have 4 bits, and the number of bits of the identification information corresponding to all the first stored states is more), and the number of identification information stored in the second latch 6212 and the third latch 6213 can be selected and set according to requirements; the fourth latch 6214 to the seventh latch 6217 each store 1 bit of data. It can be seen that the number of data bits stored in different latches 6210 can be different or the same. Among them, the number of data bits stored in the fourth latch 6214 to the seventh latch 6217 is the same; the number of data bits stored in the first latch 6211 and the second latch 6212 (or the third latch 6213) is different. The embodiments of the present application do not limit the specific number of latches 6210 and the amount of data stored in the latches 6210, as long as the principle of the data transmission method is satisfied.

[0178] As Figure 10 shown, the embodiments of the present application also provide an operation method for a memory system 50. The operation method includes: S100 and S200.

[0179] S100: The storage unit 611 in the memory device 60 of the memory system 50 is programmed to the first stored state after performing the first programming operation.

[0180] Exemplarily, the first programming operation includes a rough programming operation. After the storage unit 611 of the memory device 60 performs the rough programming operation, the programmed state of the storage unit 611 is the first stored state.

[0181] S100 further includes S110: Storing identification information in the buffer 52 of the memory system 50. The identification information corresponds to the first stored state one by one, and based on the target interval where the first stored state is located, the correspondence between the identification information and the first stored state is unique.

[0182] S200: In response to a power-on again after a power failure during the second programming operation, determine the second stored state corresponding to the second programming operation according to the data programmed after the first programming operation and the identification information. The identification information is used to characterize the second stored state corresponding to the second programming operation.

[0183] After the second programming operation is performed, the data in the first storage state is programmed into the second storage state. "Power-on again after power failure during the second programming operation" means that after a power failure occurs before the second programming operation is completed, the second programming operation is re-executed. The memory controller 51 controls the memory device 60 to re-perform the second programming operation so that the memory cell 611 is programmed into the second storage state.

[0184] Exemplarily, after a power failure occurs before the second programming operation is completed, when powering on again, the memory cell 611 in the first storage state needs to be re-performed the second programming operation. The second storage state is determined according to the first storage state and the identification information. Among them, the width of the threshold voltage distribution in the first storage state is greater than the width of the threshold voltage distribution in the second storage state. In this way, the data of the memory cell 611 in the obtained second storage state can be restored to the data before the power failure, achieving a good data recovery effect. And, the present application uses identification information to further accurately determine the value of the threshold voltage distribution of the memory cell 611. Compared with the method of data recovery only through the first storage state, the example of the present application improves the accuracy of data recovery.

[0185] In addition to the above-mentioned memory system 50 and its operation method, to solve the above problems, as Figures 11 - 13 shown, the embodiment of the present application also provides a memory device 60, which can also store more data and effectively recover data based on the stored data, improving the data recovery ability and user experience of the memory device 60.

[0186] In some embodiments, as Figure 11 shown, the memory device 60 may include a memory cell array 61 and a peripheral circuit 62 coupled to the memory cell array 61 and other circuit structures.

[0187] The memory cell array 61 is coupled to a plurality of bit lines BL. Exemplarily, the memory cell array 61 may be a NAND flash memory cell array. For example, the memory cell array 61 is a circuit structure arranged in the form of a NAND memory string array. Each NAND memory string extends vertically on the substrate. Exemplarily, each NAND memory string may include a plurality of memory cells (cell) 611 coupled in series and vertically stacked. Among them, each memory cell 611 transmits signals in a state of maintaining a continuous analog value (for example, voltage or charge), and the analog value of the memory cell 611 depends on the number of electrons captured in the area of the memory cell 611.

[0188] Exemplarily, each memory cell 611 in the memory cell array 61 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor. The present application does not limit this.

[0189] In some examples, the storage type of the above storage unit 611 includes any one of SLC, MLC, TLC, and QLC, etc.

[0190] For example, each storage unit 611 of SLC can store one bit of data and has two possible first storage states and second storage states. Among them, the first storage state (e.g., "0") corresponds to the first threshold voltage range, and the second storage state (e.g., "1") corresponds to the second threshold voltage range. In this way, the second storage state (e.g., "1") is used as the erase state, and the first storage state (e.g., "0") is used as the program state.

[0191] For another example, each storage unit of MLC can store two bits of data and has four possible first storage states, second storage states, third storage states, and fourth storage states. Among them, the first storage state (e.g., "11") corresponds to the first threshold voltage range, the second storage state (e.g., "01") corresponds to the second threshold voltage range, the third storage state (e.g., "10") corresponds to the third threshold voltage range, and the fourth storage state (e.g., "00") corresponds to the fourth threshold voltage range. In this way, the fourth storage state (e.g., "00") is used as the erase state, and the first storage state (e.g., "11"), the second storage state (e.g., "01"), and the third storage state (e.g., "10") are used as the program states.

[0192] Similarly, each storage unit of TLC can store three bits of data and has eight possible storage states. The eight storage states respectively correspond to eight threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the eight threshold voltage ranges is used as the erase state (e.g., "111"), and the remaining seven threshold voltage ranges are used as the program states. And, each storage unit of QLC can store four bits of data and has sixteen possible storage states. The sixteen storage states respectively correspond to sixteen threshold voltage ranges, and the specific storage states are not elaborated here. Among them, one of the sixteen threshold voltage ranges is used as the erase state (e.g., "1111"), and the remaining fifteen threshold voltage ranges are used as the program states.

[0193] Please continue to refer to Figure 11, the above-mentioned peripheral circuit 62 can be coupled to the memory cell array 61 through bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). The peripheral circuit 62 is configured to apply voltage signals and / or current signals to each target memory cell 611 via the bit line BL, word line WL, source line SL, source select gate SSG, or drain select gate DSG, etc., and sense voltage signals and / or current signals from each target memory cell 611 to implement logical operations (such as programming, reading, or writing operations) of the memory cell array 61.

[0194] Exemplarily, the peripheral circuit 62 includes various types of circuit structures formed using metal-oxide-semiconductor (MOS) transistors. For example, as Figure 12 shown, the peripheral circuit 62 may include a row decoder / word line driver 620, a page buffer (PB) / sense amplifier 621, a column decoder / bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627, and a data bus 628, etc., of various circuit structures.

[0195] Based on the exemplary structures of the above-mentioned memory cell array 61 and peripheral circuit 62, in the case of abnormal power-off of the memory device 60, exemplarily, during the process of programming the memory cell 611 in the memory device 60, after the memory cell 6111 is programmed to the first storage state after performing the first programming operation, the data in the first storage state is programmed to the second storage state after performing the second programming operation. The threshold voltage distribution width of the first storage state is greater than that of the second storage state.

[0196] The peripheral circuit 62 is configured to: in response to power-on again after power-off during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data and identification information in the first storage state after the first programming operation. The identification information is used to characterize the second storage state corresponding to the second programming operation. And re-perform the second programming operation to program the memory cell to the second storage state.

[0197] Exemplarily, the first programming operation includes a rough programming operation, and the second programming operation includes a fine programming operation.

[0198] After the above-mentioned peripheral circuit 62 controls the memory device to perform the first programming operation, the memory cell 611 is programmed to the first storage state. The first storage state means that the width of the threshold voltage distribution of the memory cell 611 is within a relatively large range, and the original data cannot be accurately restored only based on the first storage state. Therefore, the peripheral circuit 62 further accurately determines the range of the threshold voltage distribution of the memory cell 611 according to the identification information. The memory device 60 uses the second programming operation to determine the second storage state of the memory cell 611 based on the first storage state and the identification information. Based on this, in the case of abnormal power-off of the memory device 60, the memory device 60 can obtain the original storage state of the memory cell 611 through the memory cell 611 in the second storage state, and then through the control of the peripheral circuit 62 for reprogramming, the data recovery of the original storage state is realized, and the storage state of the memory cell 611 before abnormal power-off is obtained, improving the accuracy of data recovery and the performance and user experience of the memory device 60.

[0199] In some examples, as Figure 11 shown, the memory cell array 61 includes a plurality of word lines WL, and one word line WL is coupled to a plurality of memory cells 611.

[0200] The peripheral circuit 62 is configured to: sequentially perform the first programming operation and the second programming operation on the memory cells 611 coupled to the spaced word lines WL in the order of the physical positions of the plurality of word lines WL. Among them, for the plurality of memory cells 611 coupled to the same word line WL, the second programming operation is performed after the first programming operation.

[0201] Exemplarily, please continue to refer to Figure 11 , the plurality of word lines WL include the Qth word line, the (Q + 1)th word line, the (Q + 2)th word line, and the (Q + 3)th word line whose physical positions are continuously set. Q is a natural number.

[0202] The peripheral circuit is configured to: perform the first programming operation on the memory cells 611 coupled to the (Q + 1)th word line; then, perform the second programming operation on the memory cells 611 coupled to the Qth word line; then, perform the first programming operation on the memory cells 611 coupled to the (Q + 2)th word line; then, perform the second programming operation on the memory cells 611 coupled to the (Q + 1)th word line; then, perform the first programming operation on the memory cells 611 coupled to the (Q + 3)th word line; then, perform the second programming operation on the memory cells 611 coupled to the (Q + 2)th word line.

[0203] In some examples, the peripheral circuit 62 is configured to: during the first programming operation, generate the identification information of the second programming operation corresponding to the first storage state; and store the identification information.

[0204] Exemplarily, as Figure 12As shown, the memory cell array 61 includes a plurality of memory blocks 610. The peripheral circuit 62 is configured to store identification information in a designated memory block 610 among the plurality of memory blocks 610.

[0205] By partitioning the memory blocks 610, the storage efficiency of the identification information is improved, and the occupied space of the identification information is reduced, which is beneficial to increasing the amount of data stored in the memory cells 611 in the first storage state. Furthermore, the amount of data for data recovery is increased, and the performance and user experience of the memory device 60 are improved.

[0206] It can be understood that the identification information is stored in a designated memory block 610, and this designated memory block 610 can be any memory block 610 with a preset address, so as to facilitate the storage and screening of the identification information according to the address of the designated memory block 610 quickly, and improve the efficiency of obtaining the identification information. In addition, in the case of a large amount of identification information, multiple designated memory blocks 610 can be set for storing the identification information. The present application does not limit the specific structure of the designated memory block 610.

[0207] In some examples, the storage bit number of the memory cells 611 includes multiple bits, and the multiple storage bits correspond to multiple storage states.

[0208] The peripheral circuit 62 is configured to: generate identification information in sequence according to the high - low order of the multiple storage states.

[0209] Exemplarily, the storage bit number of the memory cells 611 is related to the storage type. The storage type of the memory cells 611 is MLC, the storage bit number is 2 bits, and the number of storage states is 2 2 types. For example, the storage states include four types: "00", "01", "10", and "11". The peripheral circuit 62 controls the memory device 60 to generate identification information in sequence according to the high - low order of the 4 storage states. For example, the identification information corresponding to the "00" storage state is "0", the identification information corresponding to the "01" storage state is "1", the identification information corresponding to the "10" storage state is "2", and the identification information corresponding to the "11" storage state is "3".

[0210] In some examples, the storage bit number of the memory cells 611 includes M bits, and the M storage bits correspond to 2 M storage states. The identification information includes N - bit data, and the value of the identification information includes 2 N data states. Both M and N are positive integers.

[0211] The peripheral circuit 62 is configured to: according to M the high - low order of the storage states, cyclically generate the 2 N data states corresponding to the values of the identification information in sequence.

[0212] Exemplarily, as Figure 6As shown, the storage type of the storage unit 611 is QLC, the number of storage bits is 4 bits, and the number of storage states is 2 4 kinds. For example, the storage states include sixteen kinds: "1111", "1110", "0110", "0010", "0011", "0001", "0000", "0100", "1100", "1000", "1010", "1011", "1001", "1101", "0101", and "0111". The peripheral circuit 62 controls the memory device 60 to sequentially generate identification information corresponding to the sixteen storage states in a cyclic manner according to the high and low levels of the sixteen storage states. For example, the identification information corresponding to the storage state of "1111" is "0", the identification information corresponding to the storage state of "1110" is "1", the identification information corresponding to the storage state of "0110" is "2", and the identification information corresponding to the storage state of "0010" is "3"; the identification information corresponding to the storage state of "0011" is "0", the identification information corresponding to the storage state of "0001" is "1", the identification information corresponding to the storage state of "0000" is "2", and the identification information corresponding to the storage state of "0100" is "3"; the identification information corresponding to the storage state of "1100" is "0", the identification information corresponding to the storage state of "1000" is "1", the identification information corresponding to the storage state of "1010" is "2", and the identification information corresponding to the storage state of "1011" is "3"; the identification information corresponding to the storage state of "1001" is "0", the identification information corresponding to the storage state of "1101" is "1", the identification information corresponding to the storage state of "0101" is "2", and the identification information corresponding to the storage state of "0111" is "3".

[0213] The above-mentioned 2 M storage states of the storage unit 611 include: 2 M first storage states after performing the first programming operation, and the threshold voltage distribution of the first storage states is the first threshold voltage distribution. And 2 M second storage states corresponding to the first storage states after performing the second programming operation. The threshold voltage distribution of the second storage states is the second threshold voltage distribution.

[0214] Among them, the range of each first threshold voltage distribution is wider than the range of the corresponding second threshold voltage distribution. There is an overlap in the ranges of adjacent first threshold voltage distributions.

[0215] That is to say, the range of each first threshold voltage distribution is wider than the range of the corresponding second threshold voltage distribution, and the original data of the storage unit 611 cannot be accurately restored only based on the first storage state. Moreover, due to the overlap in the ranges of adjacent first threshold voltage distributions, errors are likely to occur only based on the first storage state, resulting in an essential difference between the restored data and the original data. In the example of the present application, during the process of performing the second programming operation, combining the identification information and the first storage state can improve the accuracy of data restoration.

[0216] It should be noted that the identification information includes N-bit data, and the value of N is related to the number of intervals into which the threshold voltage distribution of the storage unit 611 is divided, so as to avoid the same value of the identification information existing within the same interval, so that it is impossible to determine which threshold voltage range of the second storage state corresponds to the first storage state according to the identification information. For example, in the case where two or more adjacent threshold voltage distributions overlap, at least two threshold voltage distributions that meet the conditions will be read for the same read voltage value. In this way, during the subsequent data recovery process, it is impossible to determine which threshold voltage range the storage state of the current storage unit 611 is in. Based on this, it is necessary to set N-bit identification information to distinguish the threshold voltage distributions with overlapping ranges, so as to improve the accuracy of data recovery.

[0217] In some examples, the peripheral circuit 62 is configured to: determine the target interval in which the storage unit is located after the first programming operation through P-order read voltages. The P-order read voltages divide the first to the second M first threshold voltage distributions into P + 1 intervals, and each of the P + 1 intervals includes a plurality of consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information. P is a positive integer; and re-program the data of the first storage state in the second programming operation according to the determined target interval and the value of the identification information, so that the storage unit 611 is programmed to the second storage state.

[0218] The above-mentioned P-order read voltages include the first-order to the P-order read voltages with gradually increasing voltage values. The P + 1 intervals include the first to the P + 1 intervals.

[0219] It can be understood that the P-order read voltages can enable the identification information corresponding to the threshold voltage distributions within one interval to be different. In this way, after determining the target interval where the first storage state of the currently read storage unit 611 is located, the second storage state can be directly determined according to the identification information, improving the efficiency and accuracy of the second programming operation and the accuracy of data recovery.

[0220] The peripheral circuit 62 is configured to: perform a first read operation through the first-order read voltage to determine the interval and identification information in which the first storage state of the storage unit 611 is located after the first programming operation, perform a second programming operation on the storage unit 611 whose first storage state is in the first interval, and determine the second storage state corresponding to the first storage state.

[0221] Perform second to (P - 1)th reading operations through the second to (P - 1)th order reading voltages respectively. According to the intervals where the first storage states obtained from the second to (P - 1)th reading operations are located and the identification information, perform a second programming operation on the storage cells 611 whose first storage states are in the second to Pth intervals, and determine the second storage state corresponding to the first storage state.

[0222] And perform the Pth reading operation through the Pth order reading voltage respectively. According to the interval where the first storage state obtained from the Pth reading operation is located and the identification information, perform a second programming operation on the storage cells whose first storage states are in the (P + 1)th interval, and determine the second storage state corresponding to the first storage state.

[0223] In some examples, the number of storage bits of the storage cell 611 includes 4 bits, and the 4 storage bits correspond to 16 storage states, and the values of the identification information include 4 data states.

[0224] The peripheral circuit 62 is configured to: determine the target interval where the first storage state of the storage cell 611 is located after the first programming operation through 6 order reading voltages. Among them, the first order reading voltage is the median between the first and fourth of the first threshold voltage distributions, the second order reading voltage is the median between the third and sixth first threshold voltage distributions, the third order reading voltage is the median between the fifth and eighth first threshold voltage distributions, the fourth order reading voltage is the median between the seventh and tenth first threshold voltage distributions, the fifth order reading voltage is the median between the ninth and twelfth first threshold voltage distributions, and the sixth order reading voltage is the median between the eleventh and fourteenth first threshold voltage distributions;

[0225] If the target interval where the first storage state is located after the first programming operation is the first interval and the value of the identification information is the first data state among the 4 data states, then the first storage state is in the first first threshold voltage distribution; perform the second programming operation on the storage cell so that the first storage state in the first first threshold voltage distribution is programmed to the second storage state.

[0226] In some examples, the number of first threshold voltage distributions included in each interval is the same or different. The ranges of some first threshold voltage distributions span both sides of an order reading voltage.

[0227] Exemplarily, as Figure 6 shown, the first interval includes three first threshold voltage distributions, the second to sixth intervals each include two first threshold voltage distributions, and the seventh interval includes three first threshold voltage distributions. Since the ranges of the first threshold voltage distributions are relatively large, there may be spread region values between two or three adjacent first threshold voltage distributions. Therefore, when determining an order reading voltage, the ranges of some first threshold voltage distributions span both sides of the order reading voltage.

[0228] Based on this, the identification information of the first threshold voltage distribution set in the same area is different; and the identification information of the first threshold voltage distribution across both sides of the first read voltage is different from the identification information of the first threshold voltage distribution existing only in one interval, so that when determining the target area where the storage state of the storage unit 611 is located through the read voltage, a second programming operation can be performed according to the first threshold voltage distribution and the identification information to obtain a second storage state.

[0229] In some examples, as Figure 9 shown, the peripheral circuit 62 includes a page buffer 621, and the page buffer 621 includes a plurality of latches 6210.

[0230] The peripheral circuit 62 is configured to: store the interval where the first storage state obtained by each read operation is located in the first latch 6211 among the plurality of latches 6210, and store the identification information in the second latch 6212 and the third latch 6213 among the plurality of latches 6210.

[0231] And according to the data in the first latch 6211, the second latch 6212, and the third latch 6213, store the data of the 4-bit first storage state to be programmed in the second programming operation in the fourth latch 6214 to the seventh latch 6217 among the plurality of latches 6210.

[0232] For example, please continue to refer to Figure 9 , the first latch 6211 is a cache latch and can store the first storage state of the storage unit 611 under the current read operation. The second latch 6212 and the third latch 6213 are data latches and store the identification information characterizing the second storage state based on the first storage state. The fourth latch 6214, the fifth latch 6215, the sixth latch 6216, and the seventh latch 6217 are low-voltage latches and can perform some logical operations, such as combining the identification information and the first storage state to determine the target interval and the second storage state of the storage unit 611.

[0233] In the storage unit 611 where the current read operation is being performed (for example, a QLC storage type, including LP, MP, UP1, and UP2), the peripheral circuit 62 stores the interval where the first storage state obtained by each read operation is located (for example, multiple intervals divided by the read voltage) in the first latch 6211 (for example, a sense latch).

[0234] Store the identification information characterizing the second storage state based on the first storage state in the second latch 6212 (for example, a low-voltage latch) and the third latch 6213 (for example, a low-voltage latch).

[0235] According to the data in the first latch 6211, the second latch 6212, and the third latch 6213, the 4-bit data of the first storage state to be programmed in the second programming operation (such as the data of LP, MP, UP1, and UP2) is stored in the fourth latch 6214 to the seventh latch 6217 (such as data latches).

[0236] In this way, some logical operations can be performed, such as determining the target interval and the second storage state of the storage unit 611 by combining the identification information and the first storage state.

[0237] In addition, the timing for the cache latch to release data can be set, enabling the first latch 6211 to the fourth latch 6212 to obtain more storage states of the storage unit 611 and increasing the amount of data recovered subsequently.

[0238] As Figure 14 shown, an embodiment of the present application further provides an operation method for a memory device 60. The operation method includes: S10 and S20.

[0239] S10: The storage unit 611 in the memory device 60 is programmed to the first storage state after performing the first programming operation.

[0240] Exemplarily, the first programming operation includes a rough programming operation. After the storage unit 611 of the memory device 60 performs the rough programming operation, the programmed state of the storage unit 611 is the first storage state.

[0241] S10 further includes S11: Storing identification information in the memory device 60. The identification information corresponds one-to-one with the first storage state, and based on the target interval where the first storage state is located, the correspondence between the identification information and the first storage state is unique.

[0242] S20: In response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data of the first storage state and the identification information after the first programming operation. The identification information is used to characterize the second storage state corresponding to the second programming operation.

[0243] After performing the second programming operation, the data of the first storage state is programmed to the second storage state. And "a power-on again after a power failure during the second programming operation" means that after a power failure occurs before the second programming operation is completed, the second programming operation is re-executed. The peripheral circuit 62 controls the memory device 60 to re-perform the second programming operation so that the storage unit 611 is programmed to the second storage state.

[0244] Exemplarily, after a power failure occurs before the second programming operation is completed, when power is restored again, the second programming operation needs to be performed on the storage unit 611 in the first storage state again. The second storage state is determined according to the first storage state and the identification information. Among them, the width of the threshold voltage distribution of the first storage state is greater than the width of the threshold voltage distribution of the second storage state. In this way, the data of the storage unit 611 in the obtained second storage state can be restored to the data before the power failure, achieving a good data recovery effect. Moreover, in this application, the identification information is used to further accurately determine the value of the threshold voltage distribution of the storage unit 611. Compared with the method of data recovery only through the first storage state, the example of this application improves the accuracy of data recovery.

[0245] S20 further includes S21: The memory device 60 reads the second storage state obtained after the recovery of the storage unit 611 and continues to perform other operations (such as programming or erasing operations).

[0246] Based on the memory device 60 and its operation method, and the memory system 50 and its operation method provided above, a storage medium 40 provided in this application stores executable instructions. When the executable instructions are executed, the steps of the operation method of the memory device 60 or the memory system 50 provided in any of the above embodiments can be implemented.

[0247] As described above, only the embodiments of the present disclosure are provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory device, characterized in that, Comprising: A memory cell array including a plurality of memory cells; After performing a first programming operation, the memory cells are programmed to a first storage state, and after performing a second programming operation, the data in the first storage state is programmed to a second storage state; the threshold voltage distribution width of the first storage state is greater than that of the second storage state; Peripheral circuitry coupled to the memory cell array and configured to: In response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data in the first storage state and the identification information after the first programming operation; the identification information is used to characterize the second storage state corresponding to the second programming operation; And Re-perform the second programming operation to program the memory cells to the second storage state.

2. The memory device according to claim 1, wherein The peripheral circuitry is configured to: During the first programming operation, generate the identification information of the second programming operation corresponding to the first storage state; And Store the identification information.

3. The memory device according to claim 2, wherein The memory cell array includes a plurality of memory blocks, and the peripheral circuitry is configured to: Store the identification information in a specified memory block among the plurality of memory blocks.

4. The memory device according to claim 2, wherein The number of storage bits of the memory cells includes multiple bits, and multiple storage bits correspond to multiple storage states; The peripheral circuitry is configured to: Generate the identification information in sequence according to the high-low order of the multiple storage states.

5. The memory device according to claim 4, wherein The number of storage bits of the storage unit includes M bits, and the M storage bits correspond to 2 M storage states; the identification information includes N-bit data, and the value of the identification information includes 2 N data states; both M and N are positive integers; The peripheral circuitry is configured to: According to the high and low order of the 2 M storage states, the 2 N data states corresponding to the value of the identification information are cyclically generated in sequence.

6. The memory device according to claim 5, wherein The 2 of the storage unit M storage states include: After performing the first programming operation, 2 M of the first storage states, and the threshold voltage distribution of the first storage state is the first threshold voltage distribution; and, two M second storage states corresponding to the first storage state after performing the second programming operation; the threshold voltage distribution of the second storage state is a second threshold voltage distribution; Wherein, the range of each of the first threshold voltage distributions is wider than that of the corresponding second threshold voltage distribution; there is an overlap between the ranges of adjacent first threshold voltage distributions.

7. The memory device according to claim 6, wherein The peripheral circuitry is configured to: Determine a target interval in which the storage cell is located after the first programming operation by using a P-level read voltage; the P-level read voltage divides the first to second M M first threshold voltage distributions into P + 1 intervals, each of the P + 1 intervals includes a plurality of consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information; P is a positive integer; And Re-program the data in the first storage state during the second programming operation according to the determined target interval and the value of the identification information, so that the memory cells are programmed to the second storage state.

8. The memory device according to claim 7, wherein The number of the first threshold voltage distributions included in each interval is the same or different; the ranges of some of the first threshold voltage distributions span both sides of the first-order read voltage.

9. The memory device according to claim 7, wherein, The P-order read voltage includes the 1st to Pth order read voltages with gradually increasing voltage values; the P + 1 intervals include the 1st to P + 1 intervals; the peripheral circuitry is configured to: Perform a first read operation through the 1st order read voltage to determine the interval where the first storage state of the memory cells is located after the first programming operation and the identification information, perform the second programming operation on the memory cells whose first storage state is in the 1st interval, and determine the second storage state corresponding to the first storage state; Perform second to P - 1th read operations through the 2nd to P - 1th order read voltages respectively, and respectively perform the second programming operation on the memory cells whose first storage state is in the 2nd to Pth intervals according to the intervals where the first storage state is located and the identification information obtained from the second to P - 1th read operations, and determine the second storage state corresponding to the first storage state; And Perform the P-th read operation through the P-th order read voltage. According to the interval where the first storage state is located and the identification information obtained from the P-th read operation, perform the second programming operation on the storage cells in which the first storage state is in the (P + 1)-th interval, and determine the second storage state corresponding to the first storage state.

10. The memory device according to claim 9, wherein, The storage bits of the storage cells include 4 bits, and the 4 storage bits correspond to 16 storage states. The values of the identification information include 4 data states; the peripheral circuit is configured to: Determine the target interval where the first storage state of the storage cells is located after the first programming operation through 6-order read voltages; wherein, the first-order read voltage is the median between the first and fourth of the first threshold voltage distributions, the second-order read voltage is the median between the third and sixth first threshold voltage distributions, the third-order read voltage is the median between the fifth and eighth first threshold voltage distributions, the fourth-order read voltage is the median between the seventh and tenth first threshold voltage distributions, the fifth-order read voltage is the median between the ninth and twelfth first threshold voltage distributions, and the sixth-order read voltage is the median between the eleventh and fourteenth first threshold voltage distributions; If the target interval where the first storage state is located after the first programming operation is the first interval and the value of the identification information is the first data state among the 4 data states, then the first storage state is in the first of the first threshold voltage distributions; perform the second programming operation on the storage cells to program the first storage state in the first of the first threshold voltage distributions to the second storage state.

11. The memory device according to claim 10, wherein The peripheral circuit includes a page buffer, and the page buffer includes a plurality of latches; the peripheral circuit is configured to: Store the interval where the first storage state obtained from each read operation is located in the first latch among the plurality of latches, and store the identification information in the second and third latches among the plurality of latches; and According to the data in the first latch, second latch, and third latch, store the data of the 4-bit first storage state to be programmed in the second programming operation in the fourth to seventh latches among the plurality of latches.

12. The memory device according to claim 1, wherein The storage cell array includes a plurality of word lines, and one word line is coupled to a plurality of the storage cells; The peripheral circuit is configured to: sequentially perform the first programming operation and the second programming operation on the storage cells coupled to the spaced word lines in the order of the physical positions of the plurality of word lines; wherein, for the plurality of storage cells coupled to the same word line, the second programming operation is performed after the first programming operation.

13. The memory device according to claim 12, wherein, The plurality of word lines include the Q-th word line, the (Q + 1)-th word line, the (Q + 2)-th word line, and the (Q + 3)-th word line with physically consecutive positions; Q is a natural number; The peripheral circuit is configured to: Perform the first programming operation on the storage cells coupled to the (Q + 1)-th word line; then, perform the second programming operation on the storage cells coupled to the Q-th word line. After that, perform the first programming operation on the memory cells coupled to the (Q + 2)-th word line; After that, perform the second programming operation on the memory cells coupled to the (Q + 1)-th word line; After that, perform the first programming operation on the memory cells coupled to the (Q + 3)-th word line; After that, perform the second programming operation on the memory cells coupled to the (Q + 2)-th word line.

14. A method for operating a memory device, characterized in that, Comprising: In response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data and identification information of the first storage state after the first programming operation; the identification information is used to characterize the second storage state corresponding to the second programming operation; The memory cells in the memory device are programmed to a first storage state after performing the first programming operation, and the data of the first storage state is programmed to the second storage state after performing the second programming operation; and Re-perform the second programming operation so that the memory cells are programmed to the second storage state.

15. A memory system, characterized in that, Comprising: A memory device including a plurality of memory cells; The memory cells are programmed to a first storage state after performing a first programming operation, and the data of the first storage state is programmed to a second storage state after performing a second programming operation; A memory controller coupled to the memory device and configured to: In response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data and identification information of the first storage state after the first programming operation; the identification information is used to characterize the second storage state corresponding to the second programming operation; and Control the memory device to re-perform the second programming operation so that the memory cells are programmed to the second storage state.

16. The memory system according to claim 15, wherein, The memory controller is configured to: Before the first programming operation, send a generation instruction; the generation instruction instructs the memory device to generate the identification information of the second storage state corresponding to the first storage state during the first programming operation; After the first programming operation, store the identification information fed back by the memory device.

17. The memory system according to claim 16, wherein The memory system further includes a buffer, and the memory controller is configured to: Store the identification information in the memory device; or, store the identification information in the buffer and transfer the identification information stored in the buffer to the memory device during the power-down delay period after a power failure; and After the power-on again, read back the identification information in the memory device to the buffer.

18. The memory system according to claim 16, wherein The number of storage bits of the memory cells includes multiple bits, and multiple storage bits correspond to multiple storage states; The memory controller is configured to: control the memory device to generate the identification information in sequence according to the high-low order of the multiple storage states.

19. The memory system according to claim 18, wherein, The storage bit number of the storage unit includes M bits, and the M storage bits correspond to 2 M storage states. The identification information includes N-bit data, and the value of the identification information includes 2 N data states; both M and N are positive integers; The memory controller is configured to control the memory device to sequentially and cyclically generate the data states corresponding to the values of the identification information according to the high-low order of the two M storage states. N There are two types of data states.

20. The memory system according to claim 19, wherein The 2 M storage states of the storage unit include: After performing the first programming operation, within 2 M of the first storage states, the threshold voltage distribution of the first storage state is a first threshold voltage distribution; and, two of the second storage states corresponding to the first storage state after performing the second programming operation; the threshold voltage distribution of the second storage state is a second threshold voltage distribution; M two of the second storage states; the threshold voltage distribution of the second storage state is a second threshold voltage distribution; Wherein, the range of each of the first threshold voltage distributions is wider than the range of the corresponding second threshold voltage distributions; there is an overlap between the ranges of adjacent first threshold voltage distributions.

21. The memory system according to claim 20, wherein The memory controller is configured to: Determine a target interval in which the memory cell is located after the first programming operation by using a P-stage read voltage; the P-stage read voltage divides the first threshold voltage distributions from the 1st to the 2nd M into P + 1 intervals, each of the P + 1 intervals includes a plurality of consecutive first threshold voltage distributions, and different first threshold voltage distributions in each interval correspond to different values of the identification information; P is a positive integer; and According to the determined target interval and the value of the identification information, reprogram the data in the first storage state in the second programming operation so that the storage cell is programmed to the second storage state.

22. The memory system according to claim 21, wherein The number of the first threshold voltage distributions included in each interval is the same or different; the ranges of some of the first threshold voltage distributions span both sides of the first-order read voltage.

23. The memory system according to claim 21, wherein The P-order read voltages include the 1st to Pth read voltages with gradually increasing voltage values; the P + 1 intervals include the 1st to P + 1st intervals; The memory controller is configured to: Perform a first read operation through the 1st-order read voltage to determine the interval where the first storage state of the storage cell is located after the first programming operation and the identification information, perform the second programming operation on the storage cells whose first storage state is in the 1st interval, and determine the second storage state corresponding to the first storage state; Perform second to P - 1th read operations through the 2nd to P - 1th read voltages respectively, and respectively perform the second programming operation on the storage cells whose first storage state is in the 2nd to Pth intervals according to the interval where the first storage state is located and the identification information obtained from the second to P - 1th read operations, and determine the second storage state corresponding to the first storage state; and Perform a Pth read operation through the Pth read voltage, and perform the second programming operation on the storage cells whose first storage state is in the P + 1th interval according to the interval where the first storage state is located and the identification information obtained from the Pth read operation, and determine the second storage state corresponding to the first storage state.

24. The memory system according to claim 23, wherein, The storage bit number of the storage cell includes 4 bits, and the 4 storage bits correspond to 16 storage states, and the value of the identification information includes 4 data states; The memory controller is configured to: Determine the target interval where the first storage state of the storage cell is located after the first programming operation through 6-order read voltages; wherein, the 1st-order read voltage is the median between the 1st and 4th first threshold voltage distributions, the 2nd-order read voltage is the median between the 3rd and 6th first threshold voltage distributions, the 3rd-order read voltage is the median between the 5th and 8th first threshold voltage distributions, the 4th-order read voltage is the median between the 7th and 10th first threshold voltage distributions, the 5th-order read voltage is the median between the 9th and 12th first threshold voltage distributions, and the 6th-order read voltage is the median between the 11th and 14th first threshold voltage distributions; If the target interval where the first storage state is located after the first programming operation is the 1st interval and the value of the identification information is the first data state among the 4 data states, then the first storage state is in the 1st first threshold voltage distribution; perform the second programming operation on the storage cell so that the first storage state in the 1st first threshold voltage distribution is programmed to the second storage state.

25. The memory system according to claim 24, wherein, The memory device further includes a peripheral circuit, the peripheral circuit includes a page buffer, and the page buffer includes a plurality of latches; The memory controller is configured to: Store the interval where the first storage state obtained in each read operation is located in the first latch among the multiple latches, and store the identification information in the second latch and the third latch among the multiple latches; According to the data in the first latch, the second latch, and the third latch, store the data of the 4-bit first storage state to be programmed in the second programming operation in the fourth latch to the seventh latch among the multiple latches.

26. The memory system according to claim 15, wherein The memory device includes multiple word lines, and one word line is coupled to multiple memory cells; The memory controller is configured to: control the memory device to perform the first programming operation and the second programming operation on the spaced word lines in sequence according to the physical positions of the multiple word lines; wherein, multiple memory cells coupled to the same word line perform the second programming operation after performing the first programming operation.

27. The memory system according to claim 26, wherein, The multiple word lines include the Qth word line, the (Q + 1)th word line, the (Q + 2)th word line, and the (Q + 3)th word line that are continuously arranged in physical positions; Q is a natural number; The memory controller is configured to: Control the memory device to perform the first programming operation on the memory cells coupled to the (Q + 1)th word line; then, perform the second programming operation on the memory cells coupled to the Qth word line; Then, perform the first programming operation on the memory cells coupled to the (Q + 2)th word line; Then, perform the second programming operation on the memory cells coupled to the (Q + 1)th word line; Then, perform the first programming operation on the memory cells coupled to the (Q + 3)th word line; Then, perform the second programming operation on the memory cells coupled to the (Q + 2)th word line.

28. A method for operating a memory system, characterized in that, Include: In response to a power-on again after a power failure during the second programming operation, determine the second storage state corresponding to the second programming operation according to the data programmed after the first programming operation and the identification information; the identification information is used to characterize the second storage state corresponding to the second programming operation; The memory cells in the memory device of the memory system are programmed to the first storage state after performing the first programming operation, and the data of the first storage state is programmed to the second storage state after performing the second programming operation; and Control the memory device to re-perform the second programming operation so that the memory cells are programmed to the second storage state.

29. A storage medium, characterized in that, An executable instruction is stored on the storage medium, and when the executable instruction is executed, the steps of the method described in claim 14 or 28 can be implemented.

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