Failure chip screening method

Abstract

The invention provides a failure chip screening method, which comprises the following steps: providing a chip to be tested, the chip comprising a plurality of storage units in an array form, the plurality of storage units being divided into a plurality of sectors, control lines in each sector being connected through a metal line, and control lines in different sectors being disconnected; voltage is applied to the adjacent control lines in the same sector, so that the voltage difference between the adjacent control lines in the same sector is the same as the voltage difference between the adjacent control lines in different sectors; performing write operation and read operation on the chip to judge whether the metal wires between the adjacent control wires in the same sector are broken down or not; and if the metal wires between the adjacent control wires in the same sector are broken down, the chip is considered to be invalid. According to the invention, invalid chips of two adjacent rows of storage units in the same sector are screened out in advance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a method for screening defective chips. Background Art

[0002] During the production process of chips, due to process or design problems, a small number of defective chips will appear. If the defective chips cannot be effectively screened out and flow to the client, it will increase the difficulty of problem-solving and the cost investment in the later stage. The split-gate flash memory is a device in the chip, and its failure can directly cause the failure of the chip where it is located. And there are multiple split-gate flash memories on a wafer, and the multiple split-gate flash memories are arranged in multiple rows and columns. Please refer to Figure 1 , the split-gate flash memory includes: a substrate 100, a floating gate oxide layer 101, a floating gate 102, an ONO layer 103, a first control gate 104, a second control gate 105, and a first sidewall 106 that are sequentially located on the substrate 100. A word line 107 is formed between the first control gate 104 and the second control gate 105. The word line 107 is separated from the first sidewall 106, the first control gate 104, and the second control gate 105 by a second sidewall 108 and a third sidewall 109. The word line 107 is separated from the floating gate 102 by the second sidewall 108. In other memory cells, the control gate can be a third control gate or a fourth control gate, and one floating gate and one control gate can be used as a memory cell. Please refer to Figure 2 , the word lines of all split-gate flash memories are connected together in the row direction, and a single word line is called a row. The figure includes a first word line WL0, a second word line WL1, a third word line WL2, and a fourth word line WL3. The control gates on one side of the word line are connected together in the row direction as a control line, and a single control line is called a row. For example, Figure 1 the first control gate 104 in Figure 2 is connected together in the row direction as a first control line CG0, and the second control gate 105 is connected together in the row direction as a second control line CG1.

[0003] After the chip is fabricated, it will be tested. After the test, a series of defective chips will be analyzed. It is found that some of the failed samples all exhibit row failures, and the adjacent two rows of memory cells in the same sector all fail simultaneously. For example, the memory cells in the rows where the first control line CG0 and the second control line CG1 are located fail simultaneously. The adjacent two rows of memory cells in adjacent sectors do not fail simultaneously. For example, the memory cells in the rows where the second control line CG1 and the third control line CG2 are located do not fail simultaneously. The existing chip testing methods cannot screen out in advance the situation where the adjacent two rows of memory cells in the same sector fail simultaneously, resulting in the outflow of such defective chips and causing a yield problem. Summary of the Invention

[0004] The purpose of the present invention is to provide a screening method for defective chips, which can screen out in advance the chips in which the adjacent two rows of memory cells in the same sector fail.

[0005] To achieve the above purpose, the present invention provides a screening method for defective chips, including:

[0006] Providing a chip to be tested, the chip includes a plurality of memory cells in an array form, the plurality of memory cells are divided into a plurality of sectors, and the control lines in each sector are connected by metal wires, and the control lines in different sectors are disconnected;

[0007] Applying voltages to adjacent control lines in the same sector respectively, so that the voltage difference between the adjacent control lines in the same sector is the same as the voltage difference between the adjacent control lines in different sectors;

[0008] Performing a write operation and a read operation on the chip to determine whether the metal wire between the adjacent control lines in the same sector is broken through;

[0009] If the metal wire between the adjacent control lines in the same sector is broken through, it is considered that the chip fails.

[0010] Optionally, in the screening method for defective chips, the method of performing a write operation and a read operation on the chip to determine whether the metal wire between the adjacent control lines in the same sector is broken through includes:

[0011] If the written value and the read value are different, the metal wire between the adjacent control lines in the same sector is broken through;

[0012] If the written value and the read value are the same, it is considered that the control line between the adjacent control lines in the same sector is not broken through.

[0013] Optionally, in the screening method for defective chips, the written value and the read value being different includes: the written value is 00 and the read value is 11.

[0014] Optionally, in the method for screening failed chips, the written value being different from the read value includes: the written value being 11 and the read value being 00.

[0015] Optionally, in the method for screening failed chips, if the control lines between adjacent control lines in the same sector are not broken down, the chip is considered qualified.

[0016] Optionally, in the method for screening failed chips, the voltage difference between adjacent control lines in different sectors is 7.8V - 9V.

[0017] Optionally, in the method for screening failed chips, the sector includes 2N adjacent rows of the storage units, where N is a positive integer.

[0018] Optionally, in the method for screening failed chips, the sector includes 2 adjacent rows of the storage units.

[0019] Optionally, in the method for screening failed chips, different sectors include an adjacent first sector and second sector. The first sector includes a first control line and a second control line, the second sector includes a third control line and a fourth control line, the first control line and the second control line are connected, and the third control line and the fourth control line are connected.

[0020] Optionally, in the method for screening failed chips, voltages are respectively applied to the first control line and the second control line such that the voltage difference between the first control line and the second control line is 7.8V - 9V.

[0021] In the method for screening failed chips provided by the present invention, it includes: providing a chip to be tested, the chip including a plurality of storage units in an array form, the plurality of storage units being divided into a plurality of sectors, the control lines within each sector being connected by metal lines, and the control lines of different sectors being disconnected; respectively applying voltages to adjacent control lines in the same sector such that the voltage difference between adjacent control lines in the same sector is the same as the voltage difference between adjacent control lines in different sectors; performing a write operation and a read operation on the chip to determine whether the metal line between adjacent control lines in the same sector is broken down; if the metal line between adjacent control lines in the same sector is broken down, the chip is considered failed. By respectively applying voltages to adjacent control lines in the same sector such that the voltage difference between adjacent control lines in the same sector is the same as the voltage difference between adjacent control lines in different sectors, the present invention performs a breakdown test on the metal line between adjacent control lines in the same sector in advance, and if it breaks down, the chip is considered failed. Thus, chips with adjacent two rows of storage units in the same sector failing are screened out in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1It is a schematic structural diagram of a split-gate memory;

[0023] Figure 2 It is a schematic structural diagram of the distribution of memory cells;

[0024] Figure 3 It is a flowchart of a method for screening failed chips according to an embodiment of the present invention;

[0025] In the figure: 100 - substrate, 101 - floating gate oxide layer, 102 - floating gate, 103 - ONO layer, 104 - first control gate, 105 - second control gate, 106 - first sidewall, 107 - word line, 108 - second sidewall, 109 - third sidewall. Detailed implementation manners

[0026] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0027] In the following text, terms such as "first" and "second" are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that, under appropriate circumstances, these terms used in this way can be replaced. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described herein can be added to the method.

[0028] Moreover, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be an intervening layer. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. Additionally, the references to "on" and "under" each layer can be based on the drawings.

[0029] Please refer to Figure 3 , the present invention provides a method for screening failed chips, including:

[0030] S11: Provide a chip to be tested, the chip includes a plurality of memory cells in an array form, the plurality of memory cells are divided into a plurality of sectors, the control lines in each sector are connected through metal wires, and the control lines of different sectors are disconnected;

[0031] S12: Apply voltages to adjacent control lines in the same sector respectively, such that the voltage difference between adjacent control lines in the same sector is the same as the voltage difference between adjacent control lines in different sectors;

[0032] S13: Perform write and read operations on the chip to determine whether the metal line between adjacent control lines in the same sector is broken through;

[0033] S14: If the metal line between adjacent control lines in the same sector is broken through, it is considered that the chip fails.

[0034] In the embodiment of the present invention, the method for performing write and read operations on the chip to determine whether the metal line between adjacent control lines in the same sector is broken through includes: after performing a write operation on the chip, if the written value and the read value are different, it is considered that the metal line between adjacent control lines in the same sector is broken through. For example, if the written value is 00 and the read value is 11, or if the written value is 11 and the read value is 00, it is considered that the written value and the read value are different, and the metal line between adjacent control lines in the same sector is broken through. If the written value and the read value are the same, it is considered that the control lines between adjacent control lines in the same sector are not broken through. If the control lines between adjacent control lines in the same sector are not broken through, it is considered that the chip is qualified.

[0035] In the embodiment of the present invention, the voltage difference between adjacent control lines in different sectors is 7.8V to 9V. To make the control lines in different sectors adjacent, naturally, the different sectors in the adjacent control lines in different sectors refer to adjacent sectors. Therefore, voltages need to be applied to adjacent control lines in the same sector respectively, such that the voltage difference between adjacent control lines in the same sector is 7.8V to 9V.

[0036] Preferably, a sector includes 2N adjacent rows of memory cells, where N is a positive integer. In the embodiment of the present invention, the sector includes 2 adjacent rows of memory cells. For example, please refer to Figure 2 , in the embodiment of the present invention, different sectors include an adjacent first sector and a second sector. The first sector includes a first control line CG0 and a second control line CG1, and the second sector includes a third control line CG2 and a fourth control line CG3. The first control line CG0 and the second control line CG1 are connected, and the third control line CG2 and the fourth control line CG3 are connected. Apply voltages to the first control line CG0 and the second control line CG1 respectively, such that the voltage difference between the first control line CG0 and the second control line CG1 is 7.8V to 9V, and then determine whether the metal line between the first control line CG0 and the second control line CG1 is broken through.

[0037] In summary, in the method for screening failed chips provided by the embodiments of the present invention, it includes: providing a chip to be tested, the chip includes a plurality of memory cells in an array form, the plurality of memory cells are divided into a plurality of sectors, the control lines in each sector are connected through metal wires, and the control lines of different sectors are disconnected; applying voltages to adjacent control lines in the same sector respectively, so that the voltage difference between adjacent control lines in the same sector is the same as the voltage difference between adjacent control lines in different sectors; performing a write operation and a read operation on the chip to determine whether the metal wire between adjacent control lines in the same sector is broken through; if the metal wire between adjacent control lines in the same sector is broken through, it is considered that the chip fails. By applying voltages to adjacent control lines in the same sector respectively, the present invention makes the voltage difference between adjacent control lines in the same sector the same as the voltage difference between adjacent control lines in different sectors, and performs a breakdown test on the metal wire between adjacent control lines in the same sector in advance. If it is broken through, it is considered that the chip fails. Thus, the chips in which adjacent two rows of memory cells in the same sector fail are screened out in advance.

[0038] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art within the technical field, without departing from the technical solution of the present invention, makes any form of equivalent substitution or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which are within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A screening method for failed chips, characterized in that, Including: Providing a chip to be tested, the chip includes a plurality of memory cells in an array form, the plurality of memory cells are divided into a plurality of sectors, control lines within each sector are connected through metal wires, and control lines of different sectors are disconnected; Applying voltages to adjacent control lines in the same sector respectively, so that the voltage difference between adjacent control lines in the same sector is the same as the voltage difference between adjacent control lines in different sectors; Performing a write operation and a read operation on the chip to determine whether the metal wire between adjacent control lines in the same sector is broken down; If the metal wire between adjacent control lines in the same sector is broken down, it is considered that the chip fails.

2. The screening method for defective chips according to claim 1, characterized in that, The method for performing a write operation and a read operation on the chip to determine whether the metal wire between adjacent control lines in the same sector is broken down includes: If the written value and the read value are different, the metal wire between adjacent control lines in the same sector is broken down; If the written value and the read value are the same, it is considered that the control lines between adjacent control lines in the same sector are not broken down.

3. The screening method for failed chips according to claim 2, characterized in that, The written value and the read value being different includes: the written value is 00 and the read value is 11.

4. The screening method for failed chips according to claim 2, characterized in that, The written value and the read value being different includes: the written value is 11 and the read value is 00.

5. The screening method for failed chips according to claim 1, characterized in that, If the control lines between adjacent control lines in the same sector are not broken down, it is considered that the chip is qualified.

6. The screening method for failed chips according to claim 1, wherein The voltage difference between adjacent control lines in different sectors is 7.8V to 9V.

7. The screening method for failed chips according to claim 1, characterized in that, The sector includes 2N adjacent rows of the memory cells, where N is a positive integer.

8. The screening method for failed chips according to claim 4, characterized in that, The sector includes 2 adjacent rows of the memory cells.

9. The screening method for failed chips according to claim 8, characterized in that, Different sectors include an adjacent first sector and a second sector, the first sector includes a first control line and a second control line, the second sector includes a third control line and a fourth control line, the first control line and the second control line are connected, and the third control line and the fourth control line are connected.

10. The screening method for failed chips according to claim 9, characterized in that, Applying voltages to the first control line and the second control line respectively, so that the voltage difference between the first control line and the second control line is 7.8V to 9V.

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