Encoding metadata information in codeworks

Abstract

The invention relates to encoding metadata information in a codeword. In some embodiments, a memory device may encode a codeword that encodes a plurality of data bits, a plurality of parity bits, and at least one metadata bit. The memory device may perform a first decoding program using the codeword to determine a first set of decoded bits by using a first hypothetical value for the at least one metadata bit. The memory device may perform a second decoding program to determine a second set of decoded bits by using a second hypothetical value for the at least one metadata bit. The memory device may determine whether the first hypothetical value of the at least one metadata bit or the second hypothetical value of the at least one metadata bit is a value of the at least one metadata bit using the first set of decoded bits and the second set of decoded bits.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 621,747, filed on January 17, 2024, entitled "Encoding Metadata Information in a Codeword" and assigned to its assignee. The disclosure of the prior application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices, memory device operations, and, for example, encoding metadata information in a codeword. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. A memory device includes memory cells. A memory cell is an electronic circuit capable of being programmed to a data state among two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value (commonly represented by binary "1" or binary "0"). As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a set of memory cells. To access the stored information, the electronic device can read from or sense the stored state of the set of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (such as NAND memory and NOR memory), and others. A memory device can be volatile or non-volatile. Non-volatile memory (such as flash memory) can store data for a long time even in the absence of an external power source. Volatile memory (such as DRAM) loses stored data over time unless the volatile memory is refreshed by a power source. In some instances, a memory device can be associated with a Compute Express Link (CXL). For example, a memory device can be a CXL-compliant memory device and / or can include a CXL interface. Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory device that includes: one or more components configured to: receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure to determine a first syndrome, wherein the first decoding procedure is based on a first assumed value of the metadata bits; performing a second decoding procedure to determine a second syndrome, wherein the second decoding procedure is based on a second assumed value of the metadata bits; and selecting one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits using the first syndrome and the second syndrome.

[0007] Another embodiment of the present disclosure provides a method that includes: encoding a codeword encoding a plurality of data bits associated with a portion of a memory, a plurality of parity bits associated with error correction of the plurality of data bits, and at least one metadata bit; performing a first decoding procedure using the codeword to determine a first set of decoded bits, wherein the first decoding procedure is based on a first assumed value of the at least one metadata bit; performing a second decoding procedure using the codeword to determine a second set of decoded bits, wherein the second decoding procedure is based on a second assumed value of the at least one metadata bit; and using the first set of decoded bits and the second set of decoded bits to determine whether the first assumed value of the at least one metadata bit or the second assumed value of the at least one metadata bit is the value of the at least one metadata bit.

[0008] Yet another embodiment of the present disclosure provides a memory device that includes: a plurality of error correction code engines, wherein each error correction code engine of the plurality of error correction code engines includes a plurality of decoders, and wherein each error correction code engine is configured to: receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: using a first decoder of the plurality of decoders to perform a first decoding procedure to determine a first syndrome, wherein the first decoding procedure is based on a first assumed value of the metadata bits; using a second decoder of the plurality of decoders to perform a second decoding procedure to determine a second syndrome, wherein the second decoding procedure is based on a second assumed value of the metadata bits; and selecting one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits based on the first syndrome, the second syndrome, and syndromes determined by one or more other error correction code engines of the plurality of error correction code engines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A diagram illustrating an example system capable of encoding metadata information in a codeword.

[0010] Figures 2A to 2E A diagram of an example associated with an error correction code.

[0011] Figures 3A to 3F A diagram of an example associated with encoding metadata information in a codeword.

[0012] Figure 4 A flowchart of an example method associated with encoding metadata information in a codeword. DETAILED DESCRIPTION

[0013] Host data or similar data can be stored in a memory using multiple dies or similar components, for example, by striping the host data across multiple data dies and one or more parity dies. The data dies can be used to store the host data, and the parity dies can be used to store parity bits for error correction, for example, for the purpose of correcting corrupted or unreadable data in the data dies. In some cases, the parity dies can be used to store bits used in conjunction with a chip kill protection scheme, where the data stored on a given die can be corrected when the entire die of the memory becomes unavailable. However, the chip kill protection scheme relies on full redundancy for error correction and / or does not allow metadata bits to be transmitted along with the codeword during a read operation. However, in some examples, it may be beneficial to transmit metadata information along with the codeword, for example, by transmitting one or more Compute Express Link (CXL) metadata bits, poison bits, Trusted Execution Environment (TEE) bits, and / or other types of metadata bits. Since traditional chip kill protection schemes rely on full redundancy and thus do not support metadata bit transmission, memory devices employing chip kill protection need to forego metadata transmission, resulting in a reduction in the reliability of the memory system and / or data corruption, leading to increased power, computing, storage, and other resource consumption for identifying and correcting memory operation errors.

[0014] Some embodiments described herein implement the transmission of metadata bits together with codewords, thereby resulting in improved information flow, increased reliability of the memory system, and reduced power, computation, storage, and other resource consumption required to identify and correct memory operation errors. In some embodiments, the metadata bits can be added to the codeword by shortening the data portion of the code, thereby enabling the metadata to be encoded into the codeword without storing the metadata within the data portion of the memory stripe (e.g., within the data die) and / or without transmitting the metadata bits in the channel. The decoder can perform parallel decoding of the codeword to identify the value of the metadata bits, e.g., by decoding the codeword using multiple hypotheses of the value of the metadata bits and / or by identifying which of the hypotheses results in a set of correctly decoded bits. Thus, the metadata bits can be encoded within the codewords in the memory system, resulting in improved reliability and accuracy of data storage and transmission, reduced data corruption incidents, enhanced system stability, enhanced data security and confidentiality, reduced latency for high-priority data processing, rapid identification and isolation of corrupted data, and overall more efficient memory system operation.

[0015] Figure 1 FIG. is a diagram illustrating an example system 100 capable of encoding metadata information in a codeword. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120, shown as memory devices 120-1 to 120-N (where N≥1). The memory devices may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., the memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via respective memory interfaces 145 (shown as memory interfaces 145-1 to 145-N (where N≥1)).

[0016] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or an airplane), and / or an Internet of Things (IoT) device. Host system 105 may include a host processor 150. Host processor 150 may include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 may include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or another type of processing component.

[0017] The memory system 110 can be any electronic device or equipment configured to store data in a memory. For example, the memory system 110 can be a hard disk, a solid state drive (SSD), a flash memory system (such as a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (such as a secure digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0018] The memory system controller 115 can be any device configured to control the operation of the memory system 110 and / or the operation of the memory device 120. For example, the memory system controller 115 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the memory system controller 115 can communicate with the host system 105 and can instruct one or more memory devices 120 regarding memory operations performed by the one or more memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 can provide instructions regarding memory operations performed by the local controller 125 in conjunction with the corresponding memory device 120 to the local controller 125.

[0019] The memory device 120 can include a local controller 125 and one or more memory arrays 130. In some embodiments, the memory device 120 includes a single memory array 130. In some embodiments, each memory device 120 of the memory system 110 can be implemented in a separate semiconductor package or on a separate die that includes the corresponding local controller 125 and the corresponding memory array 130 of the memory device 120. The memory system 110 can include multiple memory devices 120.

[0020] The local controller 125 can be any device configured to control the memory operations of the memory device 120 in which the local controller 125 is included (e.g., and not control the memory operations of other memory devices 120). For example, the local controller 125 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, the local controller 125 can communicate with the memory system controller 115 and can control operations performed on the memory array 130 coupled to the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 can be an SSD controller, and the local controller 125 can be a NAND controller.

[0021] The memory array 130 can include an array of memory cells configured to store data. For example, the memory array 130 can include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some embodiments, the memory system 110 can include one or more volatile memory arrays 135. The volatile memory arrays 135 can include SRAM arrays and / or DRAM arrays and other examples. The one or more volatile memory arrays 135 can be included in the memory system controller 115, one or more memory devices 120, and / or both the memory system controller 115 and one or more memory devices 120. In some embodiments, the memory system 110 can include both non-volatile memory capable of maintaining stored data after the memory system 110 is powered off and volatile memory (e.g., the volatile memory arrays 135) that requires power to maintain stored data and loses stored data after the memory system 110 is powered off. For example, the volatile memory arrays 135 can cache data read from or written to non-volatile memory and / or can cache instructions executed by the controller of the memory system 110.

[0022] The host interface 140 enables communication between the host system 105 (e.g., the host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 can include, for example, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, an NVMe interface, a USB interface, a Universal Flash Storage (UFS) interface, an eMMC interface, a Double Data Rate (DDR) interface, and / or a DIMM interface.

[0023] The memory interface 145 enables communication between the memory system 110 and the memory device 120. The memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0024] In some instances, the memory system 110 may be a Compute Express Link (CXL)-compliant memory system (sometimes referred to herein simply as a CXL memory system), and / or one or more of the memory devices 120 may be CXL-compliant memory devices (sometimes referred to herein simply as CXL memory devices). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached devices, which allows for resource sharing to achieve higher performance, reduced software stack complexity, and reduced total system cost. CXL is designed as an industry open standard interface for high-speed communication. CXL technology is built on the PCIe infrastructure, leveraging the PCIe physical and electrical interfaces to provide advanced protocols in the fabric, such as input / output (I / O) protocols, memory protocols, and coherence interfaces.

[0025] In some instances, the memory system 110 may include a PCIe / CXL interface (e.g., the host interface 140 may be associated with the PCIe / CXL interface), which may be a physical interface configured to connect a CXL memory system and / or a CXL memory device to a CXL-compliant host device. In such instances, the PCIe / CXL interface may comply with the CXL physical connection standard specification, ensuring broad compatibility and ease of integration into existing systems using the CXL protocol. Additionally or alternatively, the CXL memory system and / or the CXL memory device may be designed to efficiently interface with a computing system (e.g., the host system 105) by leveraging the CXL protocol. For example, the CXL memory system and / or the CXL memory device may be configured to utilize the high-speed, low-latency interconnect capabilities of CXL, such as for the purpose of adapting the CXL memory system and / or the CXL memory device to high-performance computing, data center applications, artificial intelligence (AI) applications, and / or similar applications.

[0026] A CXL memory system and / or a CXL memory device may include a CXL memory controller (such as memory system controller 115 and / or local controller 125), which may be configured to manage the data flow between a memory array (such as volatile memory array 135 and / or memory array 130) and a CXL interface (such as a PCIe / CXL interface, such as host interface 140). In some instances, the CXL memory controller may be configured to handle one or more CXL protocol layers, such as: an I / O layer (such as a layer associated with the CXL.io protocol, which may be used for purposes such as device discovery, configuration, initialization, I / O virtualization, direct memory access (DMA) using non-uniform load-store semantics, and / or similar purposes); a cache coherence layer (such as a layer associated with the CXL.cache protocol, which may be used for purposes such as caching host memory using a modified, exclusive, shared, invalid (MESI) coherence protocol or similar purposes); or a memory protocol layer (such as a layer associated with the CXL.memory (sometimes referred to as CXL.mem) protocol, which may enable the CXL memory device to expose host-managed device memory (HDM) to permit host devices to manage and access memory similar to native DDR connected to the host); and other instances.

[0027] The CXL memory system and / or the CXL memory device may further include and / or be associated with one or more high-bandwidth memory modules (HBMMs) or similar memory arrays (such as volatile memory array 135 and / or memory array 130). For example, the CXL memory system and / or the CXL memory device may include multiple layers of DRAM (such as stacked and / or interconnected via advanced through-silicon via (TSV) technology) in order to maximize storage density and / or enhance the data transfer speed between memory layers. Additionally or alternatively, the CXL memory system and / or the CXL memory device may include a power management unit, which may be configured to regulate the power consumption associated with the CXL memory system and / or the CXL memory device and / or may be configured to improve the energy efficiency of the CXL memory system and / or the CXL memory device. Additionally or alternatively, the CXL memory system and / or the CXL memory device may include additional components, such as one or more error correction code (ECC) engines, such as for the purpose of detecting and / or correcting data errors to ensure data integrity and / or improve the overall reliability of the CXL memory system and / or the CXL memory device.

[0028] Although the example memory system 110 described above includes the memory system controller 115, in some embodiments, the memory system 110 does not include the memory system controller 115. For example, an external controller (e.g., included in the host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Additionally, as used herein, "controller" may refer to the memory system controller 115, the local controller 125, or the external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of the operations may be performed by the memory system controller 115, and a second subset of the operations may be performed by the local controller 125. Additionally, the term "memory device" may refer to the memory system 110 or the memory device 120, depending on the context.

[0029] A controller (e.g., the memory system controller 115, the local controller 125, or the external controller) may control operations performed on a memory (e.g., the memory array 130), for example, by executing one or more instructions. For example, the memory system 110 and / or the memory device 120 may store one or more instructions in the memory as firmware, and the controller may execute the one or more instructions. Additionally or alternatively, the controller may receive one or more instructions from the host system 105 and / or the memory system controller 115 and may execute the one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) may store a set of instructions (e.g., one or more instructions or code) for execution by the controller. The controller may execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, the execution of the set of instructions by the controller causes the controller, the memory system 110, and / or the memory device 120 to perform one or more operations or methods described herein. In some embodiments, instead of or in combination with one or more instructions, hardwired circuitry may be used to perform one or more operations or methods described herein. Additionally or alternatively, the controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands".

[0030] For example, a controller (such as memory system controller 115, local controller 125, or external controller) may transmit signals to and / or receive signals from a memory (such as one or more memory arrays 130) based on one or more instructions, such as transferring (e.g., writing or programming) data to all or a portion of the memory (such as one or more memory cells, pages, sub-blocks, blocks, or planes of the memory), transferring (e.g., reading) data from all or a portion of the memory, and / or refreshing all or a portion of the memory. Additionally or alternatively, the controller may be configured to control access to the memory and / or provide a translation layer between the host system 105 and the memory (such as for mapping logical addresses to physical addresses of the memory array 130). In some embodiments, the controller may translate host interface commands (such as commands received from the host system 105) into memory interface commands (such as commands for performing operations on the memory array 130).

[0031] In some embodiments, Figure 1 one or more systems, apparatuses, devices, components, and / or controllers may be configured to: receive a codeword that encodes a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure to determine a first syndrome, where the first decoding procedure is based on using a first hypothesized value of the metadata bits; performing a second decoding procedure to determine a second syndrome, where the second decoding procedure is based on using a second hypothesized value of the metadata bits; and using the first syndrome and the second syndrome to select one of the first hypothesized value of the metadata bits or the second hypothesized value of the metadata bits as the value of the metadata bits.

[0032] In some embodiments, Figure 1 one or more systems, apparatuses, devices, components, and / or controllers may be configured to: encode a codeword that encodes a plurality of data bits associated with a portion of a memory, a plurality of parity bits associated with error correction of the plurality of data bits, and at least one metadata bit; use the codeword to perform a first decoding procedure to determine a first set of decoded bits, where the first decoding procedure is based on using a first hypothesized value of the at least one metadata bit; use the codeword to perform a second decoding procedure to determine a second set of decoded bits, where the second decoding procedure is based on using a second hypothesized value of the at least one metadata bit; and use the first set of decoded bits and the second set of decoded bits to determine whether the first hypothesized value of the at least one metadata bit or the second hypothesized value of the at least one metadata bit is the value of the at least one metadata bit.

[0033] In some embodiments, Figure 1One or more systems, apparatuses, devices, components, and / or controllers may include a plurality of error correction code engines, where each error correction code engine of the plurality of error correction code engines includes a plurality of decoders, and where each error correction code engine is configured to: receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure using a first decoder of the plurality of decoders to determine a first syndrome, where the first decoding procedure is based on using a first hypothesized value of the metadata bits; performing a second decoding procedure using a second decoder of the plurality of decoders to determine a second syndrome, where the second decoding procedure is based on using a second hypothesized value of the metadata bits; and selecting, based on the first syndrome, the second syndrome, and syndromes determined by one or more other error correction code engines of the plurality of error correction code engines, one of the first hypothesized value of the metadata bits or the second hypothesized value of the metadata bits as the value of the metadata bits.

[0034] Figure 1 The number and arrangement of components shown in are for illustration only. In fact, there may be additional components, fewer components, different components, or differently arranged components compared to the components shown in Figure 1 the components shown in. Additionally, Figure 1 two or more components shown in may be implemented within a single component, or Figure 1 a single component shown in may be implemented as multiple distributed components. Additionally or alternatively, Figure 1 a set of components (e.g., one or more components) shown in may perform one or more operations described as being performed by another set of components shown in Figure 1 the components shown in.

[0035] Figures 2A to 2E is a diagram of an example associated with an error correction code. The operations described in conjunction with Figures 2A to 2E may be performed by the memory system 110 and / or one or more components of the memory system 110 (e.g., the memory system controller 115, one or more memory devices 120, one or more local controllers 125, and / or one or more error correction code (ECC) engines associated with the memory system 110 and / or one or more memory devices 120).

[0036] As Figure 2A shown in and indicated by reference numeral 200, ECC may be used in conjunction with memory stripes (sometimes referred to as data blocks, data frames, and / or similar terms), and the memory stripes may correspond to those described above in conjunction with Figure 1The described volatile memory array 135. In some instances, a memory strip may be associated with a memory channel (e.g., a data path between the memory and other components of the memory device, such as a memory controller and / or a processor), where the "width" of the memory channel (e.g., measured in bits) refers to the number of bits that can be transferred in one operation and / or one memory cycle. For example, as described in more detail below, in some instances, a memory strip may be associated with a 40-bit channel, and thus, the memory device associated with the memory strip may be referred to as a 40-bit memory device. For example, the memory device may be a double data rate 5 (DDR5) 40-bit memory device or a similar device.

[0037] The memory strip may be associated with a plurality of memory dies for storing data bits and / or parity bits. In other words, in some instances, a plurality of data bits and / or parity bits may be striped across the plurality of dies associated with the memory strip. For example, Figure 2A The memory strip shown in is associated with 10 dies (e.g., 10 DRAM dies) indexed as die 0 to die 9, where dies 0 to 7 are used to store data bits (and thus are referred to as data dies, as indicated by reference numeral 202) and where dies 8 to 9 are used to store parity bits for error correction purposes (and thus are referred to as parity dies, as indicated by reference numeral 204). As indicated by reference numeral 206, each die may be associated with 16 bit lines (indexed as 0 to 15), and / or as indicated by reference numeral 208, each die may be configured in a "times 4" (x4) configuration such that each die includes 4 input / output pins (sometimes referred to as DQ pins). In this regard, each die is capable of storing 64 bits (e.g., 8 bytes). In some instances, the memory strip may be associated with 64 bytes of data (corresponding to 8 data dies indicated by reference numeral 202, each capable of storing 8 bytes) and 16 bytes of parity (corresponding to 2 parity dies indicated by reference numeral 204, each capable of storing 8 bytes). Additionally, as indicated by reference numeral 210, the memory strip may be associated with a 40-bit channel, where 32 bits may be associated with data bits (as indicated by reference numeral 212) and 8 bits may be associated with parity bits (as indicated by reference numeral 214).

[0038] In some instances, a parity die may store information such that, for example, in the event that an entire die fails, the information can be used in conjunction with ECC to correct data (sometimes referred to as die kill protection). In other words, an error correction system associated with a memory stripe is capable of correcting errors caused by an entire die failure. For example, as indicated by reference numeral 216, in some events, an entire die of a DRAM stack may fail (e.g., in the depicted example, die 3 fails). In such cases, the parity bits stored in the parity die may be encoded in such a way that the parity bits can be used to recover the data stored on the failed die.

[0039] More specifically, Figure 2B and 2C illustrate examples where the parity die is associated with a Reed - Solomon (RS) code and / or where the memory stripe is associated with an RS die kill protection scheme. As Figure 2B illustrated and as indicated by reference numeral 218, a die kill protection scheme may be obtained by using an RS code with 8 - bit symbols. In such cases, the size of the symbol set (sometimes referred to as q) used in the RS coding scheme for the 40 - bit memory stripe described above in Figure 2A may be equal to 256 (e.g., 2 8 ), the length of the RS codeword (sometimes referred to as n) may be 80 symbols, and the length of the data portion of the RS codeword (sometimes referred to as k) may be 64 symbols. In some instances, the RS code is capable of correcting up to t symbols, where t is equal to Thus, for the 8 - bit symbol example illustrated in Figure 2B , the RS code is capable of correcting up to symbols (e.g., 8 bytes), which is equal to the amount of data stored on one die. In this regard, in the event that an entire die of a memory stripe fails, an 8 - bit RS code may be used to provide die kill protection.

[0040] Similarly, as Figure 2C illustrated and as indicated by reference numeral 220, a die kill protection scheme may alternatively be obtained by using an RS code with 16 - bit symbols. In such cases, the size of the symbol set (e.g., q) used in the RS coding scheme for the 40 - bit data frame described above in Figure 2A may be equal to 65,536 (e.g., 2 16 ), the length of the RS codeword (e.g., n) may be 40 symbols, and the length of the data portion of the RS codeword (e.g., k) may be 32 symbols. Thus, the 16 - bit symbol example is capable of correcting up to 4 symbols (e.g., a symbol or 8 bytes), which is equal to the amount of data stored on a die. In this regard, in the event that an entire die of a memory stripe fails, a 16-bit RS code can also be used to provide chip kill protection.

[0041] In some other instances, non-binary Hamming codes can be used to provide chip kill protection for a memory, such as the 40-bit channel memory described above in connection with Figure 2A In some instances, the non-binary Hamming code used to provide chip kill protection for a memory stripe can use q elements of a Galois field (GF) as its symbols (sometimes referred to as GF(q)) and / or can be associated with a redundancy r (e.g., the non-binary Hamming code can use r parity check symbols). In such instances, the non-binary Hamming code can be a linear code with a length N (e.g., the length of the code can include N symbols) and a dimension K (e.g., the dimension of the code can be K symbols), where and where K = N – r. In some instances, the non-binary Hamming code can be considered a "perfect code" because the non-binary Hamming code is able to provide the most efficient error correction for a given set of parameters (e.g., the non-binary Hamming code can correct errors within a specific radius and does not waste any space on unnecessary redundancy). More specifically, the non-binary Hamming code can be a perfect code with a minimum distance of 3, where a set of Hamming balls of radius 1 centered on a codeword is a partition of the entire space of all possible patterns of N symbols in the alphabet GF(q), such that the entire space available for error correction is utilized. In some instances, a primitive non-binary Hamming code can be completely described by its parity check matrix H. In such instances, the columns of H can be all possible vectors of r symbols that are linearly independent of each other. That is, where α corresponds to a primitive element (e.g., an element that can generate all other non-zero elements of a finite field (e.g., GF(q)) through its powers).

[0042] As Figure 2D shown in Figure 2A and as indicated by reference numeral 222, in some instances, a chip kill protection scheme can use a non-binary Hamming code with 4-bit symbols. In such cases, the size (e.g., q) of the symbol set used in the non-binary Hamming coding scheme for the 40-bit memory stripe described above in connection with 4 can be equal to 16 (e.g., 2 Figure 2AThe described 40-bit memory stripe provides die kill protection. In other words, in an instance implementing 4-bit symbols, there can be 16 non-binary Hamming codewords per memory stripe, where each codeword covers one beat of a data burst.

[0043] Similarly, as Figure 2E shown in Figure 2A and as indicated by reference numeral 228, in some instances, a die kill protection scheme can use a non-binary Hamming code with 8-bit symbols. In such cases, the size of the symbol set (e.g., q) used in the non-binary Hamming coding scheme for the 40-bit memory stripe described above in connection with 8 can be equal to 256 (e.g., 2 Figure 2A ), the effective length of the non-binary Hamming codeword (e.g., n) can be 10 symbols, and the effective size of the non-binary Hamming codeword (e.g., k) can be 8 symbols. In such instances, as shown by reference numerals 230 and 232, 8 non-binary Hamming codewords can be used to provide die kill protection for the 40-bit memory stripe described above in connection with

[0044] In other words, in an instance implementing 8-bit symbols, there can be 8 non-binary Hamming codewords per memory stripe, where each codeword covers two beats of a data burst. In either case (e.g., non-binary Hamming code with 4-bit symbols or non-binary Hamming code with 8-bit symbols), each codeword contains no more than one symbol from each die. In this regard, because a non-binary Hamming decoder is capable of correcting up to one symbol in a codeword, the non-binary Hamming code die kill protection scheme has the ability to correct all symbols from a single die (e.g., a failing die). Figures 2B to 2DThe described chip kill protection scheme) may rely on full redundancy for error correction and thus does not permit metadata bits to be inserted into the payload. "Metadata bits" refer to additional information bits that may be included with the primary data (e.g., a codeword) to provide additional context, control information, or error detection capabilities, as well as other information. In some instances, the metadata bits do not form part of the actual data being stored or transmitted, but are used to enhance the functionality, reliability, and / or security of the memory system. In some examples, it may be beneficial to transmit the metadata bits along with the codeword, such as one or more CXL metadata bits (e.g., metadata bits that can be used to manage or optimize data transfer over the CXL interface, which may contain information about the data type, priority, and / or other control information related to the CXL protocol), poison bits (e.g., metadata bits that can be used to indicate that the data is in error and / or suspect, which may be set to indicate that the accompanying data block should not be used or trusted), TEE bits (e.g., metadata bits that can be used to indicate that the data is intended for or originated from a TEE and / or indicate that the data requires or has a specific level of security or confidentiality), and other types of metadata bits. Since the above-described chip kill protection scheme relies on full redundancy and thus cannot support metadata bit transmission, memory systems and / or memory devices employing the chip kill protection scheme need to forego metadata transmission, resulting in a reduction in the reliability of the memory system, data corruption, and / or high power, computational, storage, and other resource consumption for identifying and correcting memory operation errors.

[0045] Some embodiments described herein implement the transmission of metadata bits along with the codeword, thereby resulting in an improvement in the information flow and thus an increase in the reliability of the memory system and a reduction in the power, computational, storage, and other resource consumption originally required to identify and correct memory operation errors. In some embodiments, the metadata bits can be added to the codeword by shortening the data portion of the code, thereby enabling the metadata to be encoded into the codeword without storing the metadata within the data portion of the memory stripe and / or without transmitting the metadata bits over the channel. The decoder can perform parallel decoding of the codeword to identify the value of the metadata bits, such as by using multiple hypotheses of the value of the metadata bits to decode the codeword and / or by identifying which of the hypotheses results in a correct decoding syndrome. Thus, the metadata bits can be encoded within the codewords in the memory system, resulting in an improvement in the reliability and accuracy of data storage and transmission, a reduction in data corruption incidents, an enhancement of system stability, an enhancement of data security and confidentiality, a reduction in the latency for high-priority data processing, rapid identification and isolation of corrupted data, and overall more efficient memory system operation.

[0046] As indicated above, Figures 2A to 2E For illustration only. Other examples may differ from what is Figures 2A to 2E described.

[0047] Figures 3A to 3FFIG. is an example associated with encoding metadata information in a codeword. In conjunction with Figures 3A to 3F the operations described can be performed by the memory system 110 and / or one or more components of the memory system 110 (e.g., the memory system controller 115, one or more memory devices 120, and / or one or more local controllers 125).

[0048] As Figure 3A shown in and as indicated by reference numeral 300, a linear code (e.g., RS code, non-binary Hamming code, and / or similar codes) can be encoded for transmission in a channel, such as the 40-bit channel described above in conjunction with Figure 2A In such embodiments, the parity check of the systematic linear code can be given by the encoding equation p = dP, where p is a parity check vector of length N-K, d is a data vector of length K, and P is a parity check matrix of K rows and N-K columns. For ease of description, Figure 3A the parity check matrix shown in has K rows indicated as P i where i equals 0,..., K-1. As indicated by reference numeral 302, a codeword (shown as x) containing a parity check vector (e.g., p) and a data vector (e.g., d) can be transmitted through the channel to a decoder, which introduces noise such that the output of the channel can be different from the input of the channel. In this regard, the codeword transmitted in the channel can be represented as x = (p, d), and the codeword sensed at the decoder (shown as y) can be represented as y = (p', d').

[0049] As indicated by reference numeral 304, in some embodiments, the length of the data vector (e.g., d) can be shortened, e.g., for the purpose of reducing the length of the relevant part of the parity check matrix associated with the codeword (e.g., P). The shortening can include zeroing certain positions in the data vector before encoding the data vector (sometimes referred to herein as the shortening positions within the data vector and / or the shortened part of the data vector). For example, as shown in conjunction with reference numeral 304, the data vector (e.g., d) can include: a data portion (represented as D and indicated by reference numeral 306), which can contain data; and a shortened portion (indicated by reference numeral 308), which can be part of the data vector where all positions are set to 0. In this regard, since the shortened portion of the data vector is set to 0, only a part of the parity check matrix (e.g., P) is relevant for the purpose of encoding the parity check vector (e.g., p), as indicated by reference numeral 310. In other words, only the part of the parity check matrix that multiplies the data portion (e.g., D) of the parity check matrix is relevant for the purpose of encoding the parity check vector (e.g., p), because the remaining part of the parity check matrix will be multiplied by 0.

[0050] In some embodiments, a shortened code (e.g., the shortened data portion D of data vector d) can be utilized to convey additional bits (e.g., metadata bits or the like) to a decoder without actually transmitting the metadata bits in the channel. For example, in a chip kill protection scheme implementing an 8-bit symbol non-binary Hamming code, the length of the primitive code (e.g., the total number of symbol positions in the original unmodified non-binary Hamming code) can be In an embodiment where r = 2, and since q equals 256 (e.g., 2 8 ), N = 257. Additionally, the primitive size (e.g., the number of information symbols in the primitive non-binary Hamming code) can be K = N – r, which equals 257 - 2 or 255. Similarly, in a chip kill protection scheme implementing a 4-bit symbol non-binary Hamming code, the length of the primitive code (e.g., the total number of symbol positions in the original unmodified non-binary Hamming code) can be 17 (e.g., N = q + 1 = 16 + 1), and the primitive size can be K = N – r, which equals 17 - 2 or 15. As described above in connection with Figure 2D and 2E , the effective length required for chip kill protection of a 40-bit memory can be n = 10, and the effective size required for chip kill protection of a 40-bit memory can be k = 8. In such embodiments, the code used to transmit information can be shortened because only 8 out of the 15 available data positions in the 4-bit embodiment or 8 out of the 255 data positions in the 8-bit embodiment are needed to convey the data stored in the memory stripe. Thus, in some embodiments, metadata bits can be stored per codeword without adding any additional cells to the memory stripe, thereby enabling up to 8 metadata bits to be indicated per memory stripe in the 8-bit symbol embodiment (since there are 8 codewords per memory stripe, as described above in connection with Figure 2E ) or up to 16 metadata bits to be indicated per memory stripe in the 4-bit symbol embodiment (since there are 16 codewords per memory stripe, as described above in connection with Figure 2D ). In some other embodiments, more than one metadata bit can be indicated per codeword, for example, by increasing the complexity of the decoding component, as described in more detail below.

[0051] This can be more easily understood with reference to Figure 3B . As Figure 3Bshown and as indicated by reference numeral 312, in some embodiments, such as when ECC is associated with a 4-bit or 8-bit non-binary Hamming code and / or a 40-bit memory, the data portion (e.g., D) of the shortened code needs to be able to transmit 8 data symbols (indexed from 0 to 7). In such embodiments, the relevant portion of the parity-check matrix P may include 8 rows (indexed from 0 to 7 in the example shown in connection with reference numeral 312). However, the decoder may have the ability to decode more than 8 data symbols using the parity-check bits (e.g., the data symbols D may be a shortened portion of a non-binary Hamming code). For example, for a 4-bit symbol non-binary Hamming code, the decoder may have the ability to decode up to 15 data symbols (e.g., K = 15), but only 8 symbols are needed to transmit the data (e.g., D = 8). In this regard, the remaining portion of the data vector may be shortened, for example, by setting the positions to 0, as described above in connection with Figure 3A the reference numeral 304 in. As another example, for an 8-bit symbol non-binary Hamming code, the decoder may have the ability to decode up to 255 data symbols (e.g., K = 255), but only 8 symbols are needed to transmit the data. In this regard, the remaining portion of the data vector may be shortened, for example, by setting the positions to 0, as described above in connection with Figure 3A the reference numeral 304 in.

[0052] For certain error-correcting codes and / or memory stripes (e.g., 4-bit or 8-bit non-binary Hamming codes used in conjunction with a 40-bit memory stripe, as described above), there is at least one additional symbol in the data vector d that can be used for the purpose of transmitting metadata information. In other words, in some embodiments, the parity-check vector (e.g., p) is capable of providing error correction for up to a first number of bits (e.g., K), and the data vector (e.g., d) associated with the codeword may be associated with a second number of data bits (e.g., k) and / or a third number of zero bits (e.g., K - k), such that the second number is less than the first number (e.g., k < K). In such embodiments (e.g., the example shown in connection with reference numeral 314), the additional bits (e.g., metadata bits) may be encoded into the codeword. More specifically, as indicated by reference numeral 316, in this example, the 9th symbol (indexed as symbol 8, which is shown using a dotted line in Figure 3B and is sometimes referred to herein as D8) may be used to convey metadata information, and the corresponding 9th row of the parity-check matrix may be used to create a parity-check bit in the parity-check vector (e.g., p) associated with the metadata symbol. For example, D8 may be used to transmit one of A or B, where A and B are elements of a Galois field of dimension 2 m where m is the number of metadata bits being transmitted by the symbol (e.g., A, B ∈ GF(2 m)). In this regard, a particular value (e.g., one of A or B) may be selected to convey a first value of the metadata bit (sometimes referred to herein as F), and another value (e.g., the other of A or B) may be selected to convey a second value of the metadata bit. For example, in the case where one metadata bit per codeword is to be transmitted, if F=0, then D8 may be set to A, and if F=1, then D8 may be set to B.

[0053] In this regard, when the 9th symbol is set to A, the parity check vector calculated as dP may be equal to DP+A(1,α 8 ), and when the 9th symbol is set to B, the parity check vector can be equal to DP+B(1,α 8 ). Therefore and as indicated by reference numeral 317, when A=0, the parity check vector (e.g., p) becomes DP, and thus the codeword (e.g., x) transmitted in the channel (which, as described above, is equal to (p, d)) becomes (DP, D). Similarly, when B=1, the parity check vector (e.g., p) becomes DP+(1,α 8 ), and therefore the codeword (e.g. x) transmitted in the channel becomes (DP+(1,α 8 ),D).

[0054] Thus, the decoder is able to identify the value of the metadata bit (e.g., F) by decoding the vector (p, D). More specifically, the decoder may receive a vector (p, D) that may be corrupted (e.g., the decoder may combine the above Figure 3A Reference number 302 of describes receiving (p', D') in a similar manner. In this example, the 9th symbol of the data vector (e.g., D8) is not transmitted in the channel, and therefore the decoder cannot explicitly know the value of the metadata bit (e.g., F). Instead, the received vector (p, D) will include 2 parity symbols (e.g., p) and 8 data symbols (e.g., D). Using 2 parity symbols and 8 data symbols, the decoder is able to detect the value of the metadata bit (e.g., F) and is able to correct single symbol errors as needed. In such an implementation, the decoder can do so by performing parallel decoding of the received vector using the following two assumptions: a first assumption in which the value of the metadata bit (e.g., F) is 0 and a second assumption in which the value of the metadata bit is 1. In other words, the decoder can assume D8=A=0 in the first assumption, and the decoder can assume D8=B=1 in the second assumption. By using two different assumptions to decode the vector, the decoder will obtain two different sets of decoded bits and / or syndromes, sometimes referred to herein as S corresponding to the syndrome associated with the first assumption (e.g., F=0). H0 and S corresponding to the syndrome associated with the second hypothesis (e.g., F=1) H1 In this regard, S H0 can be equal to p+DP, and S H1may be equal to p + DP + (1, α 8 ). In other words, S H1 = S H0 + (1, α 8 )(e.g., S H1 ≠ S H0 ).

[0055] In conjunction with decoding the received codeword and / or determining two syndromes, the decoder can determine any detected errors associated with the codeword (and more specifically, associated with the data portion D of the codeword). For example, for a given syndrome and / or hypothesis, the decoder can determine that no error is detected (sometimes referred to herein as a 0 error (0E) result), a correctable error (CE) is detected, and / or an uncorrectable error (UE) is detected. Additionally or alternatively, a correctable error (e.g., CE) can be determined as one of the following: an error where the error location is in one of symbols 0 to 7 (sometimes referred to herein as D0 to D7), sometimes referred to herein as CE07; otherwise an error where the error location is in symbol 8 (e.g., D8), sometimes referred to herein as CE8. In this regard, after parallel decoding (e.g., decoding the received vector based on two hypotheses H0 and H1), the decoder will obtain two sets of results: one associated with the first hypothesis (sometimes referred to herein as {0E, CE07, CE8, UE} H0 ) and one associated with the second hypothesis (sometimes referred to herein as {0E, CE07, CE8, UE} H1 ). Using the results of the decoding process (e.g., {0E, CE07, CE8, UE} H0 and {0E, CE07, CE8, UE} H1 ), the decoder can detect the value of the metadata bit (e.g., F) and can correct any errors as needed. In other words, using the results of the parallel decoding process, the decoder can identify the correct hypothesis and correct any errors in the received codeword.

[0056] For example, Figure 3C shows an instance of a decoding table (indicated by reference numeral 318) that can be used by the decoder to determine the correct hypothesis using the two results of the parallel decoding process (e.g., using {0E, CE07, CE8, UE} H0 and {0E, CE07, CE8, UE} H1 ). As Figure 3CAs shown, the decoder can decode the codeword using a first hypothesis (e.g., H0) associated with a first hypothesized value of the metadata bit (e.g., F = 0) and can decode the codeword using a second hypothesis (e.g., H1) associated with a second hypothesized value of the metadata bit (e.g., F = 1), thereby obtaining two different sets of decoded bits (e.g., two different syndromes). In such embodiments, the possible outcome of each decoding process can be 0 detected errors (e.g., 0E), a correctable error detected in one of the first 8 symbols of the data vector (e.g., CE07), a correctable error detected in the 9th symbol of the data vector (e.g., CE8), or an uncorrectable error detected. In some embodiments, the decoder can determine which hypothesis is the correct hypothesis by identifying the cell in the decoding table corresponding to the result of the parallel decoding process.

[0057] In some instances, the results of two parallel decoding processes may not result in an indication of the correct hypothesis (e.g., an indication of the correct hypothesis), which is shown as an uncorrectable error (e.g., UE) in the decoding table. For example, if both decoding processes identify 0 errors (e.g., 0E), then the parallel decoding process cannot identify the correct hypothesis. Additionally, if both decoding processes identify a correctable error in symbols 1 through 8 (e.g., CE07), if both decoding processes identify a correctable error in the 9th symbol (e.g., CE8), or if both decoding processes identify an uncorrectable error (e.g., UE), then the parallel decoding process cannot identify the correct hypothesis. Further, if one of the decoding processes identifies a correctable error in the 9th symbol (e.g., CE8) and the other decoding process identifies an uncorrectable error (e.g., UE), then the parallel decoding process cannot identify the correct hypothesis.

[0058] However, in some cases, the results of two parallel decoding processes may indicate the correct hypothesis, which is shown as either "H0" in the decoding table (meaning the first hypothesis is the correct hypothesis) or "H1" in the decoding table (meaning the second hypothesis is the correct hypothesis). For example, if the first decoding process (e.g., the decoding process using H0) identifies 0 errors (e.g., 0E) and the second decoding process (e.g., the decoding process using H1) identifies a correctable error (e.g., one of CE07 or CE8) or an uncorrectable error (e.g., UE), then the parallel decoding process may indicate that the first hypothesis (e.g., H0) is the correct hypothesis. Similarly, if the second decoding process identifies 0 errors (e.g., 0E) and the first decoding process identifies a correctable error (e.g., one of CE07 or CE8) or an uncorrectable error (e.g., UE), then the parallel decoding process may indicate that the second hypothesis (e.g., H1) is the correct hypothesis. Additionally, if the first decoding process identifies a correctable error (e.g., CE07) in one of the first 8 data vector symbols and the second decoding process identifies a correctable error (e.g., CE8) or an uncorrectable error (e.g., UE) in the 9th data vector symbol, then the parallel decoding process may indicate that the first hypothesis (e.g., H0) is the correct hypothesis. Similarly, if the second decoding process identifies a correctable error (e.g., CE07) in one of the first 8 data vector symbols and the first decoding process identifies a correctable error (e.g., CE8) or an uncorrectable error (e.g., UE) in the 9th data vector symbol, then the parallel decoding process may indicate that the second hypothesis (e.g., H1) is the correct hypothesis.

[0059] Figure 3D Illustrate an example functional block diagram 320 associated with identifying values of metadata not explicitly stored in a memory stripe and / or not explicitly transmitted in a data channel using a parallel decoding process. As indicated by reference numeral 322, a data vector (e.g., D) may be provided to an encoder 324, such as a non-binary Hamming encoder or a similar encoder. In some embodiments, the data vector may be associated with a shortened code. For example, with respect to the above combination Figure 2AIn the described 40-bit memory, the data vectors can be associated with eight symbols indexed from 0 to 7 and shown as "07" in conjunction with encoder 324. In embodiments where a 4-bit non-binary Hamming code is utilized, this can represent a shortened code since only eight of the 15 available data vector symbols are used to transmit data. Similarly, in embodiments where an 8-bit non-binary Hamming code is utilized, this can represent a shortened code since only eight of the 255 available data vector symbols are used to transmit data. Additionally, as indicated by reference numeral 326, one or more metadata bits can be indicated to encoder 324. For example, in an embodiment where one metadata bit is to be transmitted to the decoder, the value of the metadata bit (e.g., F) can be one of 0 or 1, as described above. The metadata bit can be associated with one symbol of the data vector (e.g., d), such as the ninth symbol (indexed as symbol 8) in an example associated with the 40-bit memory described above. In this way, the encoder can encode a parity check vector (e.g., p) using a parity check matrix (e.g., P), a shortened data vector (e.g., D), and the value of one or more metadata bits (e.g., F). In other words, the memory device and / or memory system associated with the example functional block diagram 320 can encode a codeword that encodes a plurality of data bits (e.g., D) associated with a portion of the memory, a plurality of parity check bits (e.g., p) associated with error correction of the plurality of data bits, and at least one metadata bit (e.g., F). Figure 2A The parity check vector (e.g., p) and the shortened data vector (e.g., D) can be transmitted via channel 328 to one or more decoding components. For example, in conjunction with the above

[0060] The parity check vector (e.g., p) and the shortened data vector (e.g., D) can be transmitted via channel 328 to one or more decoding components. For example, in conjunction with the above Figure 2AIn the described example associated with the 40-bit memory, the codeword associated with shortening the data vector and the parity vector (which is based on the shortened data vector and one or more metadata bits, as described above) can be transmitted via the 40-bit channel to one or more decoding components. The codeword can be provided to the first decoder 330 and the second decoder 332 via channel 328. In other words, each decoder 330, 332 that will perform the parallel decoding process can receive the codeword encoding the data vector (e.g., D), the parity vector (e.g., p) associated with error correction of the data vector, and the metadata bits (e.g., F). Although, for ease of description, the first decoder 330 and the second decoder 332 are shown as separate decoders, in some instances, the two decoders 330, 332 can share common terms and / or components. Additionally, although, for ease of description, the encoder 324, the first decoder 330, and the second decoder 332 are shown as separate components, in some embodiments, the encoder 324, the first decoder 330, and / or the second decoder 332 can be associated with a common component (e.g., an error correction code (ECC) engine or a similar component). In other words, the memory system and / or the memory device can be associated with an ECC engine, where the ECC engine includes the encoder 324, the first decoder 330 (e.g., a decoder configured to perform a decoding procedure associated with a first hypothesis (e.g., H0)) and the second decoder 332 (e.g., a decoder configured to perform a second decoding procedure associated with a second hypothesis (e.g., H1)).

[0061] After receiving the codeword, the first decoder 330 can decode the codeword by using the first hypothesis (H0) (e.g., by assuming that one or more metadata bits are a first value, e.g., F = 0), thereby obtaining a first syndrome (S H0 )(e.g., a first set of decoded bits), a first error location (i H0 )(e.g., i ∈ [0,7] corresponding to CE07 or i = 8 corresponding to CE8) and / or a first error value (a HO ). Similarly, the second decoder 332 can decode the codeword by using the second hypothesis (H1) (e.g., by assuming that one or more metadata bits are a second value, e.g., F = 1), thereby obtaining a second syndrome (S H1 )(e.g., a second set of decoded bits), a second error location (i H1 ) and / or a second error value (a H1 ). In other words, the memory system and / or the memory device can determine the first symbol error associated with the first syndrome (e.g., S H0 ) and / or the second syndrome (e.g., S H1) the position in the second symbol error associated data vector (e.g., D) that is associated. As indicated by reference numeral 334, the decoders 330, 332 and / or the memory system and / or memory device associated with the decoders 330, 332 may determine the value of one or more metadata bits (e.g., F) based on the decoding result, e.g., by using the decoding table described above in connection with Figure 3C Description.

[0062] In other words, the memory system and / or memory device may determine the value of the metadata bit by: performing a first decoding procedure to determine a first syndrome (S H0 )(where the first decoding procedure is based on using a first assumed value of the metadata bit (e.g., F = 0)); performing a second decoding procedure to determine a second syndrome (S H1 )(where the second decoding procedure is based on using a second assumed value of the metadata bit (e.g., F = 1)); and using the first syndrome and the second syndrome to select one of the first assumed value of the metadata bit or the second assumed value of the metadata bit as the value of the metadata bit. Additionally or alternatively, the memory system may determine a first symbol error (e.g., i H0 and / or a H0 ) associated with the first syndrome or a second symbol error (e.g., i H1 and / or a H1 ) associated with the second syndrome and / or may select one of the first assumed value of the metadata bit or the second assumed value of the metadata bit as the value of the metadata bit by using at least one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome (e.g., by using the decoding table described above in connection with Figure 3C Description).

[0063] Although the two decoders 330, 332 are shown in connection with identifying a single metadata bit description, in some other embodiments, additional decoders may be used. For example, in an embodiment where multiple metadata bits m are encoded in a codeword, the number of assumptions to be considered will be 2 m , and thus 2 m decoders can be used. Additionally, once the correct syndrome and / or assumption is identified, the memory system and / or memory device may perform additional operations associated with the correct assumption and / or syndrome, such as correcting the symbol error associated with the correct syndrome and / or assumption.

[0064] In some embodiments, the decoding results from multiple ECC engines, where each engine includes an encoder component (e.g., encoder 324) and / or one or more decoder components (e.g., decoder 330 and / or decoder 332), can be used for the purpose of identifying the correct hypothesis and / or the value of one or more metadata bits. For example, in some embodiments, the memory device and / or memory system can be based on a first syndrome (e.g., S H0 ), a second syndrome (e.g., S H1 ), and syndromes determined by one or more ECC engines among multiple error correction code engines associated with the memory stripe and / or a portion of the memory, to select one of a first hypothesized value (e.g., 0) of the metadata bit or a second hypothesized value (e.g., 1) of the metadata bit as the value of the metadata bit (e.g., F).

[0065] For example, as shown in Figure 3E and 3F , the memory device and / or memory system can be associated with multiple ECC engines. More specifically, in the example embodiment 336 shown in Figure 3E , the memory stripe 338 can be associated with 10 dies (e.g., 8 data dies and 2 parity dies), and thus can correspond to the 40-bit memory described above in connection with Figure 2A . In an embodiment where an 8-bit symbol non-binary Hamming code is used, there can be 8 codewords in the memory stripe 338 (as described above in connection with Figure 2E ). Thus, as shown by reference numeral 340, the memory device and / or memory system can include Figure 3E 8 ECC engines indexed as engine 0 to engine 7. Each ECC engine can be associated with a corresponding codeword in the memory stripe 338 such that each engine is capable of encoding one or more metadata bits in the corresponding codeword and / or performing parallel decoding to identify one or more metadata bits, as described above in connection with Figure 3D . In some other embodiments, more or fewer ECC engines can be associated with the memory stripe. For example, in an example involving a 4-bit non-binary Hamming code (e.g., the example described above in connection with Figure 2D ), there can be 16 Hamming codewords per memory stripe and thus 16 ECC engines per 40-bit channel.

[0066] Similarly, in the example embodiment 342 shown in Figure 3F , the memory system and / or memory device can be associated with multiple memory stripes, and a group of one or more memory stripes can be associated with multiple ECC engines. For example, as indicated by reference numeral 344, the memory system and / or memory device can be a multi-row memory system and / or memory device, such as Figure 3FThe four - row memory system and / or memory device shown herein. In such embodiments, each group of four memory stripes may be associated with a corresponding set of ECC engines. For example, in an embodiment where an 8 - bit symbol non - binary Hamming code is used, the memory device and / or memory system may include 8 ECC engines for each group of memory stripes. More specifically, the first set of ECC engines 350 may perform encoding and / or parallel decoding on the memory stripes 352 of the first group, the second set of ECC engines 354 may perform encoding and / or parallel decoding on the memory stripes 356 of the second group, the third set of ECC engines 358 may perform encoding and / or parallel decoding on the memory stripes 360 of the third group, the fourth set of ECC engines 362 may perform encoding and / or parallel decoding on the memory stripes 364 of the fourth group, and so on. The sets of ECC engines 350, 354, 358, 362 may be controlled by a central controller 366 (such as the memory system controller 115 and / or the local controller 125), included in the central controller, and / or otherwise associated with the central controller.

[0067] In such embodiments, the results from multiple ECC engines (such as engines 0 to 7, as indicated by the reference numeral 340 in Figure 3E and / or the results from multiple sets of ECC engines (such as the sets of ECC engines 350, 354, 358, 362 shown in Figure 3F ) may be used to identify the correct hypothesis for a given memory stripe and / or one or more metadata bits associated with the given memory stripe. For example, a given ECC engine may determine two syndromes resulting from a parallel decoding process, where the first syndrome indicates a correctable error (such as CE07) in a first die and the second syndrome indicates a correctable error (such as CE07) in a second die. If other ECC engines associated with the same memory stripe (such as the ECC engines used to decode other codewords in the same memory stripe) identify a correctable error in the first die, then this may indicate that the first die has failed. Thus, the memory device may determine that the first hypothesis is the correct hypothesis because the first hypothesis identifies an error in the failing die while the second hypothesis does not.

[0068] As indicated above, Figures 3A to 3F is for illustration only. Other examples may be different from what is described with respect to Figures 3A to 3F .

[0069] Figure 4is a flowchart of an example method 400 associated with encoding metadata information in a codeword. In some embodiments, an ECC engine (e.g., one of the ECC engines described above in connection with 340 and / or an ECC engine that includes an encoder component (e.g., encoder 324) and / or one or more decoder components (e.g., decoders 330, 332)) may execute or may be configured to execute method 400. In some embodiments, another device or group of devices (e.g., memory system controller 115, local controller 125, encoder 324, first decoder 330, second decoder 332, one or more of the ECC engines described in connection with reference numeral 340, one or more groups of ECC engines 350, 354, 358, 362, and / or controller 366) separate from or including the ECC engine may execute or may be configured to execute method 400. Additionally or alternatively, one or more components of the ECC engine (e.g., memory system controller 115, local controller 125, encoder 324, first decoder 330, second decoder 332, one or more of the ECC engines described in connection with reference numeral 340, one or more groups of ECC engines 350, 354, 358, 362, and / or controller 366) may execute or may be configured to execute method 400. Thus, the means for performing method 400 may include an ECC engine and / or one or more components of the ECC engine. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the ECC engine, cause the ECC engine to execute method 400.

[0070] As Figure 4 shown, method 400 may include encoding a codeword that encodes a plurality of data bits (e.g., a data vector, e.g., D) associated with a portion of a memory, a plurality of parity bits (e.g., a parity vector, e.g., p) associated with error correction of the plurality of data bits, and at least one metadata bit (e.g., F) (block 410). As Figure 4 shown, method 400 may include performing a first decoding procedure using the codeword to determine a first set of decoded bits (e.g., a first syndrome, e.g., S H0 ), where the first decoding procedure is based on a first assumed value (e.g., 0 and / or H0) of the at least one metadata bit (block 420). As Figure 4 further shown, method 400 may include performing a second decoding procedure using the codeword to determine a second set of decoded bits (e.g., a second syndrome, e.g., S H1 ), where the second decoding procedure is based on a second assumed value (e.g., 1 and / or H1) of the at least one metadata bit (block 430). As Figure 4Further shown in, method 400 may include determining whether a first hypothesized value of at least one metadata bit or a second hypothesized value of at least one metadata bit is a value of at least one metadata bit (e.g., F) using a first set of decoded bits and a second set of decoded bits (block 440).

[0071] Method 400 may include additional aspects, such as any individual aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0072] In a first aspect, a plurality of parity bits can provide error correction for up to a first number of bits (e.g., K bits), wherein a plurality of data bits are associated with a data portion (e.g., D) and a shortened portion (e.g., a part of d set to 0), wherein the data portion is associated with a second number of bits (e.g., k) and wherein the second number of data bits is less than the first number of bits (e.g., k < K).

[0073] In a second aspect, either alone or in combination with the first aspect, method 400 includes determining a first symbol error (e.g., i H0 and / or a H0 ) associated with the first set of decoded bits or a second symbol error (e.g., i H1 and / or a H1 ) associated with the second set of decoded bits, wherein determining whether a first hypothesized value of at least one metadata bit or a second hypothesized value of at least one metadata bit is a value of at least one metadata bit includes using at least one of the first symbol error associated with the first set of decoded bits or the second symbol error associated with the second set of decoded bits.

[0074] In a third aspect, either alone or in combination with one or more of the first and second aspects, method 400 includes correcting one of the first symbol error associated with the first set of decoded bits or the second symbol error associated with the second set of decoded bits based on determining whether a first hypothesized value of at least one metadata bit or a second hypothesized value of at least one metadata bit is a value of at least one metadata bit.

[0075] In a fourth aspect, either alone or in combination with one or more of the first to third aspects, method 400 includes determining a position among a plurality of data bits associated with at least one of a first symbol error (e.g., i H0 ) associated with the first set of decoded bits or a second symbol error (e.g., i H1 ) associated with the second set of decoded bits.

[0076] In a fifth aspect, either alone or in combination with one or more of the first to fourth aspects, the value of the metadata bit is one of 0 or 1, wherein the first hypothesized value of the metadata bit is 0, and wherein the second hypothesized value of the metadata bit is 1.

[0077] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, encoding a codeword is performed using an encoder component associated with an error correction code engine of a memory device, wherein performing a first decoding procedure is performed using a first decoder component associated with the error correction code engine of the memory device, and wherein performing a second decoding procedure is performed using a second decoder component associated with the error correction code engine of the memory device.

[0078] Although Figure 4 illustrative blocks of method 400 are shown, in some embodiments, method 400 may include additional blocks, fewer blocks, different blocks, or a different arrangement of blocks compared to the blocks depicted in Figure 4 In addition or alternatively, two or more of the blocks of method 400 may be performed in parallel. Method 400 is an example of one method that may be performed by one or more of the devices described herein. The one or more devices may perform or may be configured to perform one or more other methods based on the operations described herein.

[0079] In some embodiments, a memory device includes one or more components configured to: receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure to determine a first syndrome, wherein the first decoding procedure is based on using a first assumed value of the metadata bits; performing a second decoding procedure to determine a second syndrome, wherein the second decoding procedure is based on using a second assumed value of the metadata bits; and using the first syndrome and the second syndrome to select one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

[0080] In some embodiments, a method includes: encoding a codeword that encodes a plurality of data bits associated with a portion of a memory, a plurality of parity bits associated with error correction of the plurality of data bits, and at least one metadata bit; using the codeword to perform a first decoding procedure to determine a first set of decoded bits, wherein the first decoding procedure is based on using a first assumed value of the at least one metadata bit; using the codeword to perform a second decoding procedure to determine a second set of decoded bits, wherein the second decoding procedure is based on using a second assumed value of the at least one metadata bit; and using the first set of decoded bits and the second set of decoded bits to determine whether the first assumed value of the at least one metadata bit or the second assumed value of the at least one metadata bit is the value of the at least one metadata bit.

[0081] In some embodiments, a memory device includes a plurality of error correction code (ECC) engines, each of the plurality of ECC engines including a plurality of decoders, and each ECC engine being configured to: receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure using a first decoder of the plurality of decoders to determine a first syndrome, wherein the first decoding procedure is based on using a first assumed value of the metadata bits; performing a second decoding procedure using a second decoder of the plurality of decoders to determine a second syndrome, wherein the second decoding procedure is based on using a second assumed value of the metadata bits; and selecting, based on the first syndrome, the second syndrome, and syndromes determined by one or more other ECC engines of the plurality of ECC engines, one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

[0082] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0083] Even though particular combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features may be combined in ways not expressly recited in the claims and / or not expressly disclosed in the specification. For example, the present disclosure includes each dependent claim in a group of claims in combination with each other individual claim in the group of claims and with each combination of multiple claims in the group of claims. As used herein, the phrase "at least one of" with respect to a list of items refers to any combination of the items, including a single member. As an example, "at least one of a, b, or c" is intended to cover a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination with multiple of the same element (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c or any other ordering of a, b, and c).

[0084] When a "component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, this language is intended to broadly cover a variety of architectures and environments. For example, unless otherwise explicitly claimed (e.g., by using "a first component" and "a second component" or other language that differentiates components in the claim), this language is intended to cover a single component performing or being configured to perform all operations, a group of components jointly performing or being configured to perform all operations, a first component performing or being configured to perform a first operation and a second component performing or being configured to perform a second operation, or any combination of components performing or being configured to perform the operations. For example, when a claim has the form "one or more components are configured to: perform X; perform Y; and perform Z", the claim should be interpreted to mean "one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (also possibly different) components are configured to perform Z".

[0085] No element, act, or instruction used herein should be construed as critical or essential unless explicitly so described. Also, as used herein, the article "a" is intended to include one or more items and may be used interchangeably with "one or more". Additionally, as used herein, the article "the" is intended to include one or more items referenced in conjunction with the article "the" and may be used interchangeably with "the one or more". When only one item is desired, the phrases "only one", "single", or similar language are used. Also, as used herein, the term "has" or the like is intended to be an open-ended term that does not limit the element it modifies (e.g., an element that "has" A may also have B). Additionally, unless otherwise explicitly stated, the phrase "based on" is intended to mean "at least partially based on". As used herein, the term "multiple" may be replaced with "a plurality of", and vice versa. Also, as used herein, unless otherwise explicitly stated (e.g., if used in combination with "either... of" or "only one of..."), the term "or" when used in a series is intended to be inclusive and may be used interchangeably with "and / or".

Claims

1. A memory device, comprising: One or more components configured to: Receive a codeword encoding a data vector, a parity vector associated with error correction of the data vector, and metadata bits; and Determine a value of the metadata bits by: Performing a first decoding procedure to determine a first syndrome, wherein the first decoding procedure is based on a first assumed value of the metadata bits; Performing a second decoding procedure to determine a second syndrome, wherein the second decoding procedure is based on a second assumed value of the metadata bits; And Using the first syndrome and the second syndrome to select one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

2. The memory device according to claim 1, wherein the parity vector is capable of providing error correction for up to a first number of bits, Wherein the data vector is associated with a second number of data bits and a third number of zero bits, and Wherein the second number is less than the first number.

3. The memory device according to claim 1, wherein the one or more components are further configured to: Determine at least one of a first symbol error associated with the first syndrome or a second symbol error associated with the second syndrome, Wherein, in order to select one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits, the one or more components are configured to use at least one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome.

4. The memory device according to claim 3, wherein the one or more components are further configured to correct one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome based on selecting one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

5. The memory device according to claim 3, wherein the one or more components are further configured to determine a position in the data vector associated with at least one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome.

6. The memory device according to claim 1, wherein the value of the metadata bits is one of 0 or 1, Wherein the first assumed value of the metadata bits is 0, and Wherein the second assumed value of the metadata bits is 1.

7. The memory device according to claim 1, wherein the one or more components are associated with an error correction code engine, and Wherein the error correction code engine includes a first decoder configured to perform the first decoding procedure and a second decoder configured to perform the second decoding procedure.

8. A method, comprising: Encode a codeword that encodes a plurality of data bits associated with a portion of a memory, a plurality of parity bits associated with error correction of the plurality of data bits, and at least one metadata bit; Perform a first decoding procedure using the codeword to determine a first set of decoded bits, wherein the first decoding procedure is based on a first assumed value of the at least one metadata bit; Perform a second decoding procedure using the codeword to determine a second set of decoded bits, wherein the second decoding procedure is based on a second assumed value of the at least one metadata bit; and Use the first set of decoded bits and the second set of decoded bits to determine whether the first assumed value of the at least one metadata bit or the second assumed value of the at least one metadata bit is the value of the at least one metadata bit.

9. The method according to claim 8, wherein the plurality of parity bits are capable of providing error correction for up to a first number of bits, wherein the plurality of data bits are associated with a data portion and a shortened portion, wherein the data portion is associated with a second number of bits, and wherein the second number of data bits is less than the first number of bits.

10. The method according to claim 8, further comprising: Determine at least one of a first symbol error associated with the first set of decoded bits or a second symbol error associated with the second set of decoded bits, wherein determining whether the first assumed value of the at least one metadata bit or the second assumed value of the at least one metadata bit is the value of the at least one metadata bit includes using at least one of the first symbol error associated with the first set of decoded bits or the second symbol error associated with the second set of decoded bits.

11. The method according to claim 10, further comprising correcting one of the first symbol error associated with the first set of decoded bits or the second symbol error associated with the second set of decoded bits based on determining whether the first assumed value of the at least one metadata bit or the second assumed value of the at least one metadata bit is the value of the at least one metadata bit.

12. The method according to claim 10, further comprising determining a position in the plurality of data bits associated with at least one of the first symbol error associated with the first set of decoded bits or the second symbol error associated with the second set of decoded bits.

13. The method according to claim 8, wherein the value of the metadata bit is one of 0 or 1, wherein the first assumed value of the metadata bit is 0, and wherein the second assumed value of the metadata bit is 1.

14. The method according to claim 8, wherein encoding the codeword is performed using an encoder component associated with an error correction code engine of a memory device, wherein performing the first decoding procedure is performed using a first decoder component associated with the error correction code engine of the memory device, and wherein performing the second decoding procedure is performed using a second decoder component associated with the error correction code engine of the memory device.

15. A memory device, comprising: a plurality of error correction code engines, wherein each error correction code engine of the plurality of error correction code engines includes a plurality of decoders, and wherein each error correction code engine is configured to: receive a codeword encoding a data vector, a parity check vector associated with error correction of the data vector, and metadata bits; and determine a value of the metadata bits by: performing a first decoding procedure using a first decoder of the plurality of decoders to determine a first syndrome, wherein the first decoding procedure is based on a first assumed value of the metadata bits; performing a second decoding procedure using a second decoder of the plurality of decoders to determine a second syndrome, wherein the second decoding procedure is based on a second assumed value of the metadata bits; and selecting, based on the first syndrome, the second syndrome, and syndromes determined by one or more other error correction code engines of the plurality of error correction code engines, one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

16. The memory device according to claim 15, wherein the parity check vector is capable of providing error correction for up to a first number of bits, wherein the data vector is associated with a second number of data bits and a third number of zero bits, and wherein the second number is less than the first number.

17. The memory device according to claim 15, wherein each error correction code engine is further configured to: determine at least one of a first symbol error associated with the first syndrome or a second symbol error associated with the second syndrome, wherein, in order to select one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits, each error correction code engine is configured to use at least one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome.

18. The memory device according to claim 17, wherein each error correction code engine is further configured to correct one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome based on selecting one of the first assumed value of the metadata bits or the second assumed value of the metadata bits as the value of the metadata bits.

19. The memory device according to claim 17, wherein each error correction code engine is further configured to determine a position in the data vector associated with at least one of the first symbol error associated with the first syndrome or the second symbol error associated with the second syndrome.

20. The memory device according to claim 15, wherein the value of the metadata bits is one of 0 or 1, wherein the first assumed value of the metadata bits is 0, and wherein the second assumed value of the metadata bits is 1.

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