Interconnection method and interconnection structure after chip screening
By filling and planarizing the openings of the dielectric layer, defining the through holes and metal filling, the problem of large-scale wiring resources occupied by AL layer is solved, and a high-yield chip interconnect structure is realized, which is suitable for a variety of packaging methods.
Patent Information
- Application Number
- CN202510518142.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-07-18
AI Technical Summary
The prior art requires a large demand for AL layer wiring resources after the chip screen, which affects chip planarization and stacking, and the test PAD area is relatively large, resulting in low packaging yield.
By filling and planarizing the openings of the dielectric layer, defining through holes and metal filling, metal interconnection is achieved, avoiding additional AL layer resources, and forming an interconnect structure on the metal interconnection layer using photolithography and etching processes.
Without increasing the AL layer wiring resources, we can meet wafer testing needs, improve packaging yield, and realize subsequent interconnection to reduce layout wiring pressure.
Smart Images
Figure CN120341177A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip interconnection, and particularly relates to an interconnection method and an interconnection structure after chip screening. Background Art
[0002] With the vigorous development of fields such as AI, cloud computing, and autonomous driving, higher requirements are put forward for chip performance such as bandwidth. Considering the slowdown of Moore's Law, heterogeneous integration of chips through 2.5D / 3D / 3.5D packaging to meet high-density integration and interconnection is the current mainstream method. However, the yield problem of advanced packaging has always been an issue that needs to be urgently solved.
[0003] Current high-performance computing (HPC) and other architectures usually adopt the CoW (chip on wafer) process, such as AMD MI300, etc. CoW refers to a packaging technology in which the cut bare die is bonded to the wafer. In order to improve the yield of CoW stacked packaging, before chip stacking, it is necessary to perform wafer probe testing (also known as CP testing, chip probing / circuit probing, testing the voltage, timing, function, etc. of each die on the wafer to ensure that each die meets the design specifications) on the chips. On the one hand, it is used to evaluate whether the die is qualified, and on the other hand, it is used to evaluate the device characteristics of the die itself. By means of performance matching, the packaging yield is further improved. However, the CP probe will cause surface damage to the test PAD, forming needle marks with a height of 1-2 um, which poses relatively great challenges to the bump process of the bottom wafer for subsequent interconnection with the substrate and the 3D interconnection between the die and the wafer. Summary of the Invention
[0004] In view of this, the present application provides an interconnection method and an interconnection structure after chip screening, aiming to reduce the demand for AL layer wiring resources.
[0005] The present application provides an interconnection method after chip screening in the first aspect, including:
[0006] Obtaining a 2D wafer with a dielectric layer opening formed, and performing wafer probe testing or wafer acceptance testing on the 2D wafer; wherein the dielectric layer opening is located in the dielectric layer, and the dielectric layer is located above the metal interconnection layer;
[0007] Performing dielectric layer filling and planarization processing on the dielectric layer opening by using a filling process;
[0008] Defining a via pattern in the dielectric layer by using a lithography process and an etching process, and stopping the via above the lower metal interconnection layer;
[0009] Metal-fill the through-holes, and use the metal-filled through-holes to form metal interconnections between the metal interconnect layer and the metal lines above the dielectric layer.
[0010] Preferably, before performing dielectric layer filling and planarization on the openings in the dielectric layer using a filling process, it further includes:
[0011] Remove the tip topography of the needle marks on the tested 2D wafer, remove the remaining metal at the openings in the dielectric layer, and stop the openings in the dielectric layer above the metal interconnect layer.
[0012] Preferably, before performing dielectric layer filling and planarization on the openings in the dielectric layer using a filling process, it further includes:
[0013] Use an etching process to remove the aluminum pads on the tested 2D wafer and the metal at the openings in the first dielectric layer, and remove the residual acid solution present in the first dielectric layer, where the first dielectric layer is located between the aluminum pads and the metal interconnect layer.
[0014] Preferably, the filling process includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
[0015] Preferably, the dielectric layer filling includes filling using a silicon nitride, silicon oxide, or silicon oxynitride process.
[0016] Preferably, the metal filling of the through-holes further includes:
[0017] Metal-fill the through-holes using physical vapor deposition or electrochemical plating process.
[0018] Preferably, the metal filling further includes: metal-filling using copper or tungsten.
[0019] Preferably, the metal lines above the dielectric layer are formed by a single damascene process after metal filling the through-holes.
[0020] Preferably, the metal lines are made of copper or aluminum.
[0021] In a second aspect of the present application, there is provided an interconnection structure for an interconnection method after chip screening based on the foregoing first aspect.
[0022] It can be seen that the interconnection method and interconnection structure after chip screening of the present application, without the need to additionally occupy AL layer wiring resources, meet the requirements of wafer testing such as CP through processing test needle marks and cross-layer interconnection structure design, increase the overall package (yield), and can also achieve subsequent interconnections. Description of the Drawings
[0023] To more clearly illustrate the technical solutions in the embodiments of the present application or in the art, the following will briefly introduce the drawings required for use in the description of the embodiments or the art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0024] Figure 1 The schematic diagram of a chip interconnection method according to the related art is shown.
[0025] Figure 2 The schematic diagram of another chip interconnection method according to the related art is shown.
[0026] Figure 3 The schematic diagram of yet another chip interconnection method according to the related art is shown.
[0027] Figure 4 The flowchart of the interconnection method after chip screening according to the first embodiment of the present application is shown.
[0028] Figure 5 The flowchart of the interconnection method after chip screening according to the second embodiment of the present application is shown.
[0029] Figure 6 The schematic diagram of the process implementation manner according to the second embodiment of the present application is shown.
[0030] Figure 7 The schematic diagram of a test PAD design according to the present application is shown.
[0031] Figure 8 The schematic diagram of a thick AL test PAD according to the related art is shown.
[0032] Figure 9 The flowchart of the interconnection method after chip screening according to the third embodiment of the present application is shown.
[0033] Figure 10 The schematic diagram of another test PAD design according to the present application is shown.
[0034] Figure 11 The schematic diagram of the process implementation manner according to the third embodiment of the present application is shown.
[0035] Figures 12 - 15 The schematic diagram of the chip interconnection manner under various packaging methods and stacking forms according to the present application is shown. Detailed implementation manners
[0036] To better understand the above technical solutions, the following will describe the above technical solutions in detail in combination with the drawings in the specification and specific implementation manners.
[0037] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. In order to more clearly illustrate the present application, numerous technical details are described in the following specific embodiments. Those skilled in the art should understand that the present application can still be implemented without some of these details. Additionally, in order to highlight the inventive concept of the present application, some methods, means, components, and their applications well-known to those skilled in the art are not described in detail, but this does not affect the implementation of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.
[0038] In the related art, in one solution, the pin marks are buried by depositing a corresponding dielectric layer, and the position of the aluminum pad (AL PAD) is designed in advance for the interconnection part to further achieve the interconnection. As Figure 1 shown, it still requires additional AL layer wiring resources, and the dielectric layer is relatively thick, which is not conducive to the planarization and stacking of the chip, and is also not beneficial to the heat dissipation of the chip itself. In another solution, by designing parallel ALPADs, which are divided into test PADs and interconnection PADs, the test PADs bury the pin marks after processing, and the interconnection PADs achieve further interconnection. As Figure 2 shown. With the parallel PAD design, the AL layer requires additional area. In yet another solution, by offsetting the test positions and reforming the bump openings on the second passivation layer, subsequent packaging processes such as bump are satisfied. As Figure 3 shown. The PAD areas for the test and subsequent bump processes are relatively large, resulting in additional requirements for the AL layer resources.
[0039] As described above, the related art has additional requirements for the wiring resources of the AL layer, resulting in a relatively large layout wiring pressure. To solve the above problems or other problems, the present application provides an interconnection method and an interconnection structure after chip screening, which realizes a new connection structure in a new process manner. By removing the AL metal layer from the test pin mark PADs, the interconnection with the lower metal layer is achieved, reducing the requirements for the AL layer wiring resources and being more friendly to the layout wiring.
[0040] Embodiment 1
[0041] On the one hand, the present application provides an interconnection method after chip screening. Refer to the flowchart of the interconnection method after chip screening shown in Figure 4 shown. The specific steps include:
[0042] S001, obtaining a 2D wafer with dielectric layer openings formed thereon, and performing wafer probe testing or wafer acceptance testing on the 2D wafer; wherein the dielectric layer openings are located in the dielectric layer, and the dielectric layer is located above the metal interconnection layer;
[0043] S002, perform dielectric layer filling and planarization processing on the openings in the dielectric layer by using a filling process;
[0044] S003, define a via pattern in the dielectric layer by using a photolithography process and an etching process, and stop the via above the underlying metal interconnect layer;
[0045] S004, perform metal filling on the via, and form a metal interconnect between the metal interconnect layer and the metal line above the dielectric layer by using the via after metal filling.
[0046] Embodiment 2
[0047] On the one hand, the present application provides an interconnection method after chip screening. Refer to Figure 5 the flowchart of the interconnection method after chip screening as shown, and the specific steps include:
[0048] S101, obtain a 2D wafer with openings formed in the dielectric layer, and perform a wafer probe test or a wafer acceptance test on the 2D wafer; wherein the openings in the dielectric layer are located in the dielectric layer, and the dielectric layer is located above the metal interconnect layer.
[0049] S102, remove the tip topography of the pin marks on the 2D wafer after the test, remove the remaining metal at the openings in the dielectric layer, and stop the openings in the dielectric layer above the metal interconnect layer, and then perform dielectric layer filling and planarization processing on the openings in the dielectric layer by using a filling process.
[0050] S103, define a via pattern in the dielectric layer by using a photolithography process and an etching process, and stop the via above the underlying metal interconnect layer.
[0051] S104, perform metal filling on the via, and form a metal interconnect between the metal interconnect layer and the metal line above the dielectric layer by using the via after metal filling.
[0052] The process implementation manner of this solution is as Figure 6 , and the specific process implementation manner is as follows:
[0053] Step 1: Design by using the test PADs of the 2D wafer standard, and obtain the 2D wafer after window opening of the SOC wafer (bottom wafer) and the Cache wafer (top wafer) prepared by the foundry;
[0054] Step 2: Perform a wafer probe test (CP) or a wafer acceptance test (WAT) on the 2D wafer, select a suitable wafer according to the test results, and mark (ink) the status of the Die for identifying the failed die after the WAT / CP test, which is convenient for discarding after later cutting;
[0055] Step 3: Remove the tip morphology of the pin marks on the wafer by using an etching process (such as F, Cl solutions, etc.) or other processes (laser annealing and melting, etc.);
[0056] Step 4: Redefine the opening window by using a photolithography process or the blank etch process method, remove the remaining metal AL at the opening position, and stop the opening of the second dielectric layer (passivation2 open) above the underlying metal interconnect layer (topmetal);
[0057] Step 5: Fill the dielectric layer (such as silicon nitride, silicon oxide, silicon oxynitride, etc.) through a suitable filling process (such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), etc.) and perform planarization;
[0058] Step 6: Redefine the via pattern by using a photolithography process and an etching process to form a trench, and stop the via on the top metal;
[0059] Step 7: Metal-fill the via through a suitable process (such as PVD, ECP (Electrochemical plating), etc.), and the filled metal is not limited to metal materials such as Cu / W, etc.;
[0060] Step 8: Use the single damascene process, etc. to form the metal interconnection between the metal wiring and the metal interconnect layer through the metal-filled via (not limited to metals such as Cu / AL, etc.).
[0061] It should be noted that the above process scheme requires that there should be no opening of the first dielectric layer (passivationl open) under the AL PAD opening, otherwise polymer residues are likely to exist at the AL position of the opening, affecting the reliability of the chip. The exemplary scheme of this application provides a schematic diagram of the PAD design, as Figure 7 shown.
[0062] Example 3
[0063] If the AL is relatively thick, a relatively serious side etching phenomenon will occur in the wet etching process, as Figure 8 shown. During the subsequent filling process of the dielectric layer, voids will occur, leading to reliability problems in the later stage of the chip. This application further provides a thick AL test PAD design scheme and a process implementation scheme.
[0064] On the other hand, the present application provides an interconnection method after chip screening. Refer to Figure 9 the flowchart of the interconnection method after chip screening as shown, and the specific steps include:
[0065] S201, obtain a 2D wafer with openings in the second dielectric layer formed, and perform wafer probe testing or wafer acceptance testing on the 2D wafer.
[0066] S202, use an etching process to remove the aluminum pads on the tested 2D wafer and the metal at the openings in the first dielectric layer, and use a filling process to perform dielectric layer filling and planarization on the openings in the second dielectric layer. The first dielectric layer is located between the aluminum pads and the metal interconnection layer.
[0067] S203, use a photolithography process and an etching process to define a via pattern in the second dielectric layer, and stop the via above the metal interconnection layer.
[0068] S204, perform metal filling on the via, and use the via after metal filling to form a metal interconnection between the metal interconnection layer and the metal line above the second dielectric layer.
[0069] The design solution of this embodiment is as Figure 10 shown. The AL PAD is not interconnected through the AL line, but is led out from the top metal. The opening in the second dielectric layer (passivation2 open) is greater than or equal to the size of the AL PAD. The opening in the first dielectric layer (passivation1 open) is placed close to the edge of the AL PAD to facilitate more deep Via layouts. The deep Via interconnection positions are pre-designed on the top metal.
[0070] The implementation solution of the thick AL process is as Figure 11 , and the specific process implementation solution is as follows:
[0071] Step 1: Obtain the 2D wafer after windowing of the SOC wafer (bottom wafer) and the Cache wafer (top wafer) prepared by the foundry;
[0072] Step 2: Perform CP testing or WAT testing on the 2D wafer, select a suitable wafer according to the test results, and the state of the inkDie;
[0073] Step 3: Use an etching process (such as solutions of F, Cl, etc.) to remove metals such as AL on the AL PAD and at the opening in the first dielectric layer (passivation1 open) on the wafer, at least ensure that the AL metal at the AL PAD position is completely removed, and in addition, remove the possible acid residue at the passivation1 open;
[0074] Step 4: Fill the dielectric layer (such as silicon nitride, silicon oxide, or silicon oxynitride, etc.) through a suitable process (such as PVD, CVD, or ALD, etc.) and perform planarization;
[0075] Step 5: Redefine the VIA pattern through photolithography and etching processes to form trenches and stop at the top metal;
[0076] Step 6: Fill the VIA with metal through a suitable process (such as PVD, ECP, etc.), and the metal is not limited to metal materials such as Cu / W, etc.;
[0077] Step 7: Form metal interconnections (not limited to metals such as Cu / AL, etc.) using the single damascene process, etc. for subsequent interconnections.
[0078] Example 4
[0079] Another aspect of the present application provides a chip interconnection structure formed by an interconnection method after chip screening based on Embodiments 1 to 3.
[0080] It can be seen that the interconnection method and interconnection structure after chip screening provided by the present application have the following advantages compared with the technology:
[0081] On the premise of not requiring additional occupation of AL layer wiring resources, by processing test pin marks and cross-layer interconnection structure design, the requirements of wafer testing such as CP are met, the overall packaging yield is increased, and subsequent interconnections can also be realized.
[0082] Those skilled in the art should also understand that the above solution is not limited to the CoW process and can be extended to packaging methods such as D2D (chip to chip, a packaging technology that bonds cut Dies to Dies), WoW (wafer on wafer, a packaging technology that bonds wafers to wafers), etc., face to face and face to back stacking forms, and subsequent interconnections are not limited to methods such as hybrid bonding, u-bump, Cu pillar, etc. As Figures 12 - 15 shown. The above solution is not limited to applications between Die interconnections and can also be applied to interconnections with interposer / package substrates. For example, after CP testing, an AL PAD opening is formed again for subsequent packaging bump processes. For overall advanced packaging, the same set of process treatment methods can be adopted, which can reduce the process development cost, as Figure 13 and Figure 15 shown.
[0083] The above text describes multiple embodiment solutions provided by the embodiments of the present application. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending multiple possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present application.
[0084] Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.
Claims
1. An interconnection method after chip screening, characterized in that, Including: Obtain a 2D wafer with an opening formed in the dielectric layer, and perform wafer probe testing or wafer acceptance testing on the 2D wafer; Wherein the opening in the dielectric layer is located in the dielectric layer, and the dielectric layer is located above the metal interconnect layer; Use a filling process to perform dielectric layer filling and planarization on the opening in the dielectric layer; Use photolithography and etching processes to define a via pattern in the dielectric layer, and stop the via above the underlying metal interconnect layer; Perform metal filling on the via, and form a metal interconnect between the metal interconnect layer and the metal line above the dielectric layer using the via after metal filling.
2. The interconnect method after chip screening according to claim 1, wherein Before using the filling process to perform dielectric layer filling and planarization on the opening in the dielectric layer, it further includes: Remove the tip topography of the pin marks on the 2D wafer after testing, remove the remaining metal at the opening in the dielectric layer, and stop the opening in the dielectric layer above the metal interconnect layer.
3. The interconnection method after chip screening according to claim 1, wherein Before using the filling process to perform dielectric layer filling and planarization on the opening in the dielectric layer, it further includes: Use an etching process to remove the aluminum pad on the 2D wafer after testing and the metal at the opening in the first dielectric layer, and remove the acid residue present in the first dielectric layer, where the first dielectric layer is located between the aluminum pad and the metal interconnect layer.
4. The interconnecting method after chip screening according to claim 2 or 3, characterized in that, The filling process includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.
5. The interconnection method after chip screening according to claim 2 or 3, characterized in that, The dielectric layer filling includes filling using a silicon nitride, silicon oxide, or silicon oxynitride process.
6. The interconnection method after chip screening according to claim 1, wherein, The performing metal filling on the via further includes: Perform metal filling on the via using physical vapor deposition or electrochemical plating process.
7. The interconnection method after chip screening according to claim 6, characterized in that Further including: Perform metal filling using copper or tungsten.
8. The interconnecting method after chip screening according to claim 1, characterized in that, The metal line above the dielectric layer is formed by a single damascene process after performing metal filling on the via.
9. The interconnection method after chip screening according to claim 8, characterized in that The metal line is made of copper or aluminum.
10. A chip interconnect structure based on the interconnect method for a chip after screening according to any one of claims 1-9.