Stacked hole and stacked disc chip packaging structure for transmitting high-speed signals

Abstract

The invention discloses a stacked hole and stacked disc chip packaging structure for transmitting high-speed signals, which comprises a ball grid array (BGA) solder ball, a bottom layer area and a top layer area, and is characterized in that each layer between Ln-4 and Ln / 2 is provided with a PTH expanded layer hole for stacked hole alignment; avoidance is arranged on each layer in the areas from Ln-4 to Ln-1 and the bottom layer. The micropores of every adjacent t layers from L1 to Ln / 2 are stacked; the micropores in each layer from Ln-3 to Ln are overlapped, and a micropore interlayer avoiding area is arranged in Ln-4 and is overlapped with the micropores in Ln-3; and BUMP salient points are also arranged in the overlapped micropores from Ln to Ln-3. According to the invention, a plurality of impedance discontinuous points on a transmission path are combined into three parts, the impedance of each part is controlled, and the impedance fluctuation is ensured to be reduced; in addition, through hole stacking and a shared avoiding area, space is saved, micro-ground via holes can be densely added, high-speed signal backflow and mutual isolation are carried out, and the transmission effect is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of switching chips, and particularly to a stacked via and stacked pad chip package structure for transmitting high-speed signals. Background Art

[0002] For high-speed differential signals above the rate of 10 Gbps, such as 10 Gbps, 12.5 Gpbs, 16 Gpbs, 25 Gpbs, 32 Gpbs, 56 Gbps and even higher-speed differential signals, in order to ensure low-loss transmission of signals, it is required that the physical transmission channel has small impedance fluctuations, so as to reduce signal reflection and maintain the integrity of the transmitted signal.

[0003] However, DIE Bumps and BGA Balls on the package substrate are densely arranged. BGA is the abbreviation of Ball Grid Array, that is, ball grid array package, DIE Bump is the chip bump, DIE is the chip or die; Bump is the bump or pad. In the design of high-speed signal packaging, on the one hand, it is necessary to overcome the difficulty of high-density wire-out at both ends of the Bump and BGA. On the other hand, it is necessary to ensure that the high-speed signal still has small impedance fluctuations after passing through various impedance discontinuous points such as BGA pads, via expansion hole pads, via expansion hole anti-pads, BUMP pads, micro-via anti-pads, and via expansion hole pads. How to achieve these two aspects simultaneously has become a key technical problem to be overcome in the package substrate. Summary of the Invention

[0004] In view of the above technical problems, the object of the present invention is to provide a stacked via and stacked pad chip package structure for transmitting high-speed signals. By combining multiple impedance discontinuous points on the high-speed signal transmission path into three parts and controlling the impedance of each part, the consistency of the overall impedance on the transmission path is ensured. In addition, by stacking vias and combining each avoidance and anti-pad, the space is effectively saved, so that micro-ground vias can be densely added for the return of high-speed signals and isolation between each other, ensuring the transmission effect of high-speed signals.

[0005] It is achieved through the following technical solutions: A stacked via and stacked die chip package structure for transmitting high-speed signals, at least including BGA solder balls and a package substrate with a total of n layers from L_1 to L_n, where n = 2k and k is an integer not less than 5; L_1 to L_n / 2 are the bottom layers, L_n-4 to L_n are the top layers, and PTH enlarged vias for stacked via alignment are provided on each layer between L_n-4 and L_n / 2; among them, on each layer from L_n-4 to L_n-1 and on each layer in the bottom layer region, an avoidance for ground copper foil is respectively provided, the region boundaries I of the avoidance on each layer in the bottom layer region are the same, the connection region of the BGA solder balls to L_1 is within the region boundary I of the avoidance in L_1, and the region boundaries II of the avoidance on each layer from L_n-4 to L_n-1 are the same; in L_1 to L_n / 2, the micro vias of every adjacent t layers starting from L_1 are stacked, where t is an integer not less than 3; the micro vias of each layer from L_n-3 to L_n are overlapped, a micro via isolation avoidance region is provided in L_n-4, and the micro via isolation avoidance region overlaps with the micro vias in L_n-3; BUMP bumps are also provided in the overlapped micro vias from L_n to L_n-3.

[0006] Preferably, in L_n-4 to L_n-1 in the top layer region, overlapping ground copper foil avoidance regions are provided, and the enlarged vias are located within the ground copper foil avoidance region in L_n-4. Since the dielectric of each layer is relatively thin during actual chip packaging, overlapping multi-layer ground copper foil avoidance regions are adopted to reduce the parasitic capacitance caused by the thin dielectric, which is convenient for ensuring the quality of high-speed signal transmission.

[0007] Preferably, the micro vias between L_n-4 and L_n-3 are located within the ground copper foil avoidance region in L_n-4. Since the micro vias are located within the corresponding ground copper foil avoidance region, the impedance change can be reduced, making the impedance fluctuation smaller.

[0008] Preferably, the anti-pad of the micro vias between L_n-4 and L_n-3 in L_n-4 is directly connected to the via pad of the enlarged vias in L_n-4. The anti-pad of the micro vias is directly connected to the via pad of the enlarged vias to form a low-impedance vertical channel, which can not only make the impedance fluctuation smaller but also improve the space utilization rate and save more space.

[0009] Preferably, a ground copper foil is reserved between the micro vias in L_n-4 and the micro via isolation avoidance region as a spacer. Reserving the spacer can suppress the possible crosstalk effect between the two.

[0010] Preferably, multiple micro ground vias or multiple high-speed differential signal vias are provided in each enlarged via and each micro via. Providing multiple high-speed differential signal vias can support the transmission of multiple high-speed differential signals, and multiple micro ground vias can reduce the ground bounce noise.

[0011] The beneficial effects of the present invention compared with the prior art are: In the technical solution of the present invention, multiple impedance discontinuity points on the high-speed signal transmission path are combined into three parts, the impedance of each part is controlled, and impedance fluctuations are reduced, thereby ensuring the consistency of the overall impedance on the transmission path; in addition, by stacking vias and combining each avoidance and anti-pad, space is effectively saved, so that micro-ground vias can be densely added for the return of high-speed signals and isolation between each other, ensuring the transmission effect of high-speed signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a stacked via and stacked pad chip package structure for transmitting high-speed signals; Figure 2 It is a comparative schematic diagram of high-speed differential signal vias and micro-ground vias. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] Next, the technical solutions in the embodiments of the present invention will be described in detail in conjunction with the drawings in the embodiments of the present invention Figure 1 and 2 of the present invention.

[0014] As Figure 1 shown, it is a schematic diagram of a stacked via and stacked pad chip package structure for transmitting high-speed signals, showing an encapsulation substrate with n layers, which are respectively connected to the BGA solder balls at the bottom and the BUMP bumps at the top. By performing corresponding stack-up combinations on multiple vias and multiple regions on the multi-layer encapsulation substrate, a stacked via and stacked pad package structure composed of BGA solder balls, a bottom layer region, PTH enlarged vias, a top layer region, and BUMP bumps is finally formed, effectively reducing impedance fluctuations and saving more unused space.

[0015] In this stacked via and stacked pad chip package structure, the n layers of the encapsulation substrate are respectively L_1, L_2, L_3,...., L_n, n = 2k, k is an integer not less than 5, and the same ground copper wire is laid on each layer, and then the ground copper wire of each layer is designed separately. L_1 to L_n / 2 is the bottom layer region, L_n - 4 to L_n is the top layer region, and PTH enlarged vias for stacked via alignment are provided on each layer between L_n - 4 and L_n / 2.

[0016] In this embodiment, in each layer of the top layer regions L_n-4 to L_n-1 and each layer of the bottom layer regions L_1 to L_n / 2, there is respectively provided an avoidance of the ground copper foil, that is, a vacant space, and the boundary of the avoidance is the region boundary. In the bottom layer regions L_1 to L_n / 2, the region boundaries I of the avoidance in each layer are the same, which is convenient for alignment for subsequent structural design. The micro-vias of every adjacent t layers starting from L_1 are stacked, where t is an integer not less than 3. For example, when t is 3, the micro-vias in L_1, L_2, and L_3 are stacked and share a micro-via channel A; then, the micro-vias in L_3, L_4, and L_5 are stacked and share another micro-via channel B; and so on until the layer L_n / 2. At the same time, there is also an avoidance region between every two adjacent micro-via channels on the junction layer. For example, there is a corresponding avoidance region between the micro-via channels A and B in the L_3 layer for suppressing crosstalk.

[0017] Further, if n / 2 cannot satisfy the stacking of micro-vias in every adjacent 3 layers. For example, when n = 12, the micro-via channel connected to L_6 is only the micro-via between L_6 and L_5.

[0018] In addition, for the parameter t during micro-via stacking, in order to increase the impedance coherence between different layers, the number of t is at least 3.

[0019] In this embodiment, the BGA solder balls are connected to L_1 and the connected region is within the region boundary I of the avoidance in L_1. The micro-vias between L_1 and L_3 are also within the range of the connection between the BGA solder balls and the region boundary I. Thus, each avoidance region from L_1 to the via expansion layer can be shared by the via expansion holes and each micro-via, thereby saving a large amount of space and making the connection of each part in the bottom layer region more orderly and having smaller impedance fluctuations.

[0020] In this embodiment, in L_n-4 to L_n-1 of the top layer region, the region boundaries II of the avoidance in each layer are the same. Here, the region boundary II and the region boundary I are independent of each other and do not need to be forced to align. The micro-vias of each layer from L_n-3 to L_n are overlapped to form a micro-via channel C, and the BUMP bumps are inserted into the micro-via channel C; in addition, a micro-via interlayer avoidance region is provided in L_n-4, and the position of the micro-via interlayer avoidance region overlaps with the micro-vias in L_n-3. Thus, the BUMP bumps and the micro-via channel C can share the anti-pad during actual package soldering. The anti-pad is the region where the ground copper foil is deliberately not set around each micro-via, that is, each avoidance region, for insulation.

[0021] In addition, among L_n-4 to L_n-1 in the top layer region, the via expansion holes are located within the ground copper pad avoidance region in L_n-4. Since the dielectric of each layer is relatively thin during actual chip packaging, for example, it may be less than 30 microns or between 30 and 60 microns, etc., overlapping multi-layer ground copper pad avoidance regions are adopted to reduce the parasitic capacitance that may be caused by the thin dielectric, facilitating the guarantee of the quality of high-speed signal transmission.

[0022] In this embodiment, the micro-vias between L_n-4 and L_n-3 are located within the ground copper pad avoidance region in L_n-4, and the anti-pads of the micro-vias between L_n-4 and L_n-3 in L_n-4 are directly connected to the via pads of the via expansion holes in L_n-4. Thus, the via expansion layer, the top layer region, and the BUMP bumps can share the corresponding avoidance regions between L_n-4 and L_n; at the same time, the anti-pads of the micro-vias are directly connected to the via pads of the via expansion holes to form a low-impedance vertical channel, which can not only reduce the impedance fluctuation but also improve the space utilization rate and save more space.

[0023] In this embodiment, a ground copper pad is reserved as a spacer between the micro-vias in L_n-4 and the via isolation and avoidance region. Reserving the spacer can suppress the possible crosstalk effect between the two.

[0024] In this embodiment, multiple micro-ground vias or multiple high-speed differential signal vias are provided in each via expansion hole and each micro-via. Providing multiple high-speed differential signal vias can support the transmission of multiple high-speed differential signals, and multiple micro-ground vias can reduce the ground bounce noise.

[0025] In summary, the present invention combines multiple impedance discontinuity points on the high-speed signal transmission path into three parts and controls the impedance of each part, thereby ensuring the consistency of the overall impedance on the transmission path and effectively reducing the impedance fluctuation; in addition, by overlapping vias and combining each avoidance and anti-pad, space is effectively saved, so that micro-ground vias can be densely added for the return of high-speed signals and mutual isolation, ensuring the transmission effect of high-speed signals, and having significant progressiveness.

[0026] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A stacked via and stacked die chip package structure for transmitting high-speed signals, characterized in that An encapsulation substrate including at least BGA solder balls and a total of n layers from L_1 to L_n, where n = 2k and k is an integer not less than 5; L_1 to L_n / 2 are the bottom regions, L_n - 4 to L_n are the top regions, and PTH extended holes for via alignment are provided in each layer between L_n - 4 and L_n / 2. Among them, avoidance areas for ground copper foils are respectively provided in each layer from L_n - 4 to L_n - 1 and each layer in the bottom region. The boundary I of the avoidance area in each layer of the bottom region is the same. The area where the BGA solder balls are connected to L_1 is within the boundary I of the avoidance area in L_1. The boundary II of the avoidance area in each layer from L_n - 4 to L_n - 1 is the same; in L_1 to L_n / 2, the microvias in every adjacent t layers starting from L_1 are stacked, where t is an integer not less than 3; the microvias in each layer from L_n - 3 to L_n are overlapped, and a microvia isolation avoidance area is provided in L_n - 4, and the microvia isolation avoidance area overlaps with the microvias in L_n - 3; BUMP bumps are also provided in the overlapped microvias from L_n to L_n - 3.

2. The stacked via and stacked die chip package structure for transmitting high-speed signals according to claim 1, wherein In L_n - 4 to L_n - 1 in the top region, overlapping ground copper foil avoidance areas are provided, and the extended holes are within the ground copper foil avoidance area in L_n - 4.

3. A stacked-via and stacked-die chip package structure for transmitting high-speed signals according to claim 2, wherein The microvias between L_n - 4 and L_n - 3 are within the ground copper foil avoidance area in L_n - 4.

4. A stacked-via and stacked-die chip package structure for transmitting high-speed signals according to claim 1, wherein, The anti-pad of the microvias between L_n - 4 and L_n - 3 in L_n - 4 is directly connected to the via pad of the extended holes in L_n - 4.

5. A stacked-via and stacked-die chip package structure for transmitting high-speed signals according to claim 1, characterized in that, Ground copper foil is reserved between the microvias in L_n - 4 and the microvia isolation avoidance area as a spacer.

6. The stacked via and stacked die chip package structure for transmitting high-speed signals according to claim 1, wherein Multiple micro-ground vias or multiple high-speed differential signal holes are provided in each extended hole and each microvia.

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