Electronic component and manufacturing method thereof

Abstract

The invention relates to an electronic component and a manufacturing method thereof. The electronic component includes: a first substrate; a first drain electrode of the first semiconductor chip is located on one side of the first semiconductor chip, a first gate electrode and a first source electrode of the first semiconductor chip are located on the other opposite side of the first semiconductor chip, and the first drain electrode is coupled to the first substrate; the second substrate is physically separated from the first substrate; a second drain electrode of the second semiconductor chip is located on one side of the second semiconductor chip, a second gate electrode and a second source electrode are located on the other opposite side of the second semiconductor chip, the second drain electrode is coupled with the second substrate, and the second gate electrode is coupled with the second source electrode. Wherein the first semiconductor chip and the second semiconductor chip are located between the first substrate and the second substrate; a first connection structure coupling the first source to the second substrate; and a second connection structure coupling the second source to the first substrate.

Description

Technical Field

[0001] The present invention relates to an electronic component and a method for manufacturing the same. More specifically, the present invention relates to an electronic component having a double-layer substrate and a heat dissipation structure. Background Art

[0002] An electronic component may include a plurality of chips or integrated circuits (ICs). Under the trend of miniaturization, the circuit wiring area on a printed circuit board (PCB) is reduced. At the same time, in order to meet higher current and power requirements, the total number of chips, the number of input / output (I / O) connection pins, and the interconnection paths in the electronic component will increase and become more complex. How to reduce resistance, disperse heat sources, and improve heat dissipation efficiency will become more important. Summary of the Invention

[0003] Embodiments of the present disclosure relate to an electronic component. The electronic component includes: a first substrate; a first semiconductor chip having a first gate, a first source, and a first drain, wherein the first drain is located on one side of the first semiconductor chip, and the first gate and the first source are located on the opposite side of the first semiconductor chip, and wherein the first drain is coupled to the first substrate; a second substrate physically separated from the first substrate; a second semiconductor chip having a second gate, a second source, and a second drain, wherein the second drain is located on one side of the second semiconductor chip, and the second gate and the second source are located on the opposite side of the second semiconductor chip, and wherein the second drain is coupled to the second substrate, and wherein the first semiconductor chip and the second semiconductor chip are located between the first substrate and the second substrate; a first connection structure that couples the first source to the second substrate; and a second connection structure that couples the second source to the first substrate.

[0004] Embodiments of the present disclosure relate to a method for manufacturing an electronic component. The method includes: providing a first substrate; disposing a first semiconductor chip on the first substrate; providing a second substrate; disposing a second semiconductor chip on the second substrate; coupling the second substrate to the first semiconductor chip via a first connection structure; and coupling the first substrate to the second semiconductor chip via a second connection structure. Brief Description of the Drawings

[0005] Aspects of certain embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0006] Figure 1AShown is a top view of an electronic component according to certain embodiments of the present case;

[0007] Figure 1B Shown is an equivalent circuit diagram of an electronic component according to certain embodiments of the present case;

[0008] Figure 2 Shown is a cross-sectional view of an electronic component according to certain embodiments of the present case;

[0009] Figure 3 Shown is a perspective view of a part of an electronic component according to certain embodiments of the present case;

[0010] Figure 4 Shown is a perspective view of a part of an electronic component according to certain embodiments of the present case;

[0011] Figure 5 Shown is an exploded view of an electronic component according to certain embodiments of the present case;

[0012] Figure 6 Shown is a perspective view of a part of an electronic component according to certain embodiments of the present case;

[0013] Figure 7 Shown is a perspective view of a part of an electronic component according to certain embodiments of the present case;

[0014] Figure 8 Shown is a schematic diagram of the current direction of an electronic component according to certain embodiments of the present case; and

[0015] Figure 9 Shown is a flowchart of a method for manufacturing an electronic component according to certain embodiments of the present case.

[0016] The same or similar components are labeled with the same reference numerals in the drawings and the detailed description. From the following detailed description in conjunction with the accompanying drawings, several embodiments of the present disclosure will be immediately understood. Detailed Description of Specific Embodiments

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be limiting. In the present disclosure, a reference to forming a first feature above or over a second feature can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0019] The present disclosure provides an electronic component and a method for manufacturing the same. The electronic component of the present disclosure separates chips on a double-layer substrate to disperse current and improves the heat dissipation efficiency of the chips through a heat dissipation structure. In addition, the electronic component of the present disclosure uses a metal layer instead of wires as a gate control layer for coupling the gates of the chips, which can reduce the circuit wiring area on the printed circuit board. Overall, the electronic component of the present disclosure can reduce resistance, disperse heat sources, improve heat dissipation efficiency, and meet higher current and power requirements while miniaturizing.

[0020] Referring to Figure 1A and Figure 1B , Figure 1A FIG. 13 shows a top view of an electronic component 1a according to some embodiments of the present case, Figure 1B FIG. 14 shows an equivalent circuit diagram of the electronic component 1a according to some embodiments of the present case. The electronic component 1a may include terminals for connecting to an external circuit, such as (but not limited to) a first lead VGH, a second lead VGL, an output terminal V out , a high-voltage terminal VH, and a low-voltage terminal VL.

[0021] The electronic component 1a may include semiconductor chips (referred to as chips or dies). The semiconductor chips may include circuit components such as transistors, resistors, capacitors, and interconnect structures to form an integrated circuit (IC). In some embodiments, the electronic component 1a may include metal-oxide-semiconductor field-effect transistors (MOSFETs), such as (but not limited to) NMOS, PMOS, CMOS, voltage feedback devices, and / or switches. In some embodiments, the electronic component 1a may include high-voltage transistors, which have a higher breakdown voltage (or withstand voltage) and can be applied to circuits with high input voltage and / or high output voltage.

[0022] The electronic component 1a may include an inverter circuit configured to convert an input DC voltage or DC current into an output AC voltage or AC current. However, the present disclosure is not limited thereto. Further, the electronic component 1a may include any type of integrated circuit, such as an amplifier circuit, an oscillator circuit, a rectifier circuit, a filter circuit, a timer circuit, a sensor circuit, a logic circuit, a power supply circuit, a voltage regulator circuit, or a communication circuit, etc.

[0023] In some embodiments, as Figure 1B shown, the equivalent circuit diagram of the electronic component 1a may include two NMOSs. The gate of the upper NMOS is coupled to the first lead VGH, the drain is coupled to the high-voltage terminal VH, and the source is coupled to the output terminal V out . The gate of the lower NMOS is coupled to the second lead VGL, the drain is coupled to the output terminal V out , and the source is coupled to the low-voltage terminal VL. In some embodiments, the two NMOSs are connected in a cascode configuration.

[0024] Referring to Figure 2 , Figure 2 shown is a cross-sectional view of the electronic component 1a according to certain embodiments of the present case. The electronic component 1a may include a first substrate 10, a second substrate 20, a first semiconductor chip 11, a second semiconductor chip 21, a first connection structure 12, a second connection structure 22, a first gate control layer 13, a second gate control layer 23, and a molding compound layer 14.

[0025] The first substrate 10 and the second substrate 20 may include a ceramic substrate and a circuit (or a heat dissipation structure) formed on one or both sides of the ceramic substrate. The circuit (or the heat dissipation structure) may be bonded to the ceramic substrate via an active metal brazing technique, a diffusion bonding technique, or other methods. Taking the active metal brazing technique as an example, the bonding layer between the ceramic substrate and the circuit (or the heat dissipation structure) may include a brazing material component and an active metal component. The brazing material component may include silver, copper, tin, etc. The active metal component may include titanium, zirconium, etc., and an active metal layer may be formed at the interface between the ceramic and the brazing material component. The substrate using the active metal brazing technique may be referred to as an active metal brazing (AMB) substrate. However, the present disclosure is not limited thereto. In some embodiments, the first substrate 10 and the second substrate 20 may use a diffusion bonding technique, such as a direct copper bonding (DCB) substrate. The first substrate 10 and the second substrate 20 may be separate substrates respectively. The first substrate 10 and the second substrate 20 may be physically separated, for example, they may be spaced apart by a distance from each other or not in contact with each other.

[0026] One or more chips may be respectively disposed on the first substrate 10 and the second substrate 20. In other words, one or more chips may be disposed between the first substrate 10 and the second substrate 20. For example, the first semiconductor chip 11 and the second semiconductor chip 21 may be disposed between the first substrate 10 and the second substrate 20. The drain of the first semiconductor chip 11 may be coupled to the first substrate 10, and the drain of the second semiconductor chip 21 may be coupled to the second substrate 20.

[0027] Referring to Figure 3 , Figure 3 FIG. shows a perspective view of the first semiconductor chip 11 and the first connection structure 12 according to certain embodiments of the present case.

[0028] The first semiconductor chip 11 may have one or more electrical terminals exposed from the surface of the first semiconductor chip 11. For example, the first gate 11G and the first source 11S of the first semiconductor chip 11 may be located on the same side of the first semiconductor chip 11, while the first drain 11D is located on the opposite side. The sizes (e.g., width, thickness, area, etc.) of the first gate 11G, the first source 11S, and the first drain 11D may be the same as or different from each other. For example, the size of the first drain 11D may be larger than that of the first source 11S, and the size of the first source 11S may be larger than that of the first gate 11G. The first semiconductor chip 11 may have a plurality of first sources 11S. In Figure 3 the first semiconductor chip 11 may have two first sources 11S, and in other embodiments, the first semiconductor chip 11 may have more than three first sources 11S.

[0029] The first drain 11D can be coupled Figure 2 to the first substrate 10. In some embodiments, the first drain 11D can be coupled to the first substrate 10 via a silver sintering process Figure 2 to the first substrate 10. For example, in Figure 2 , a silver sintering coating 11s can be disposed between the first drain 11D and the first substrate 10. In some embodiments, using the silver sintering process to replace the wire bonding process can reduce resistance and improve heat dissipation efficiency. Figure 2 To clearly show the position of the silver sintering coating 11s, the thickness of the silver sintering coating 11s is enlarged, however, the present disclosure is not limited thereto.

[0030] The first connection structure 12 can be disposed on the first source 11S. The first connection structure 12 can couple the first source 11S Figure 2 to the second substrate 20. In some embodiments, the first connection structure 12 can be coupled to the first source 11S via a silver sintering process. For example, a silver sintering coating 12s can be disposed between the first connection structure 12 and the first source 11S. In some embodiments, the first connection structure 12 can be coupled to the second substrate 20 via a silver sintering process Figure 2 to the second substrate 20. For example, a silver sintering coating (not shown) can be disposed between the first connection structure 12 and Figure 2 the second substrate 20.

[0031] The first connection structure 12 can have a first groove 12c that can span two first sources 11S. For example, the first connection structure 12 can have two end points separated by the first groove 12c, respectively coupled to the two first sources 11S. The first groove 12c can have dimensions, such as a width W and a height H. In some embodiments, the width W and the height H can be greater than (e.g., both greater than) Figure 2 at least three times the size (e.g., maximum width, maximum diameter, average width, average diameter, etc.) of the fillers in the molding compound layer 14 to facilitate filling of the molding compound layer 14 in subsequent processes Figure 2 in the molding compound layer 14. However, if the width W and the height H are too small, the resistance may be too high. For example, the width W and the height H can be between about 0.100 millimeters (mm) and about 0.300 mm, such as between about 0.200 mm and about 0.250 mm, such as about 0.225 mm.

[0032] The second semiconductor chip 21 and the second connection structure 22 can have a structure similar to or the same as that of the first semiconductor chip 11 and the first connection structure 12. For example, referring to Figure 3For the component symbols within the square brackets, the second semiconductor chip 21 may have one or more electrical terminals exposed from the surface of the second semiconductor chip 21. For example, the second gate 21G and the second source 21S of the second semiconductor chip 21 may be located on the same side of the second semiconductor chip 21 while the second drain 21D is located on the opposite side. The sizes (e.g., width, thickness, area, etc.) of the second gate 21G, the second source 21S, and the second drain 21D may be the same as or different from each other. For example, the size of the second drain 21D may be larger than that of the second source 21S, and the size of the second source 21S may be larger than that of the second gate 21G. The second semiconductor chip 21 may have a plurality of second sources 21S. In Figure 3 , the second semiconductor chip 21 may have two second sources 21S. In other embodiments, the second semiconductor chip 21 may have more than three second sources 21S.

[0033] The second drain 21D may be coupled to Figure 2 the second substrate 20. In some embodiments, the second drain 21D may be coupled to the second substrate 20 via a silver sintering process. For example, in Figure 2 a silver sintering coating 21s may be disposed between the second drain 21D and the second substrate 20. Figure 2 In

[0034] A second connection structure 22 may be disposed on the second source 21S. The second connection structure 22 may couple the second source 21S to Figure 2 the first substrate 10. In some embodiments, the second connection structure 22 may couple to the second source 21S via a silver sintering process. For example, a silver sintering coating 22s may be disposed between the second connection structure 22 and the second source 21S. In some embodiments, the second connection structure 22 may couple to Figure 2 the first substrate 10 via a silver sintering process. For example, a silver sintering coating (not shown) may be disposed between the second connection structure 22 and Figure 2 the first substrate 10.

[0035] The second connection structure 22 may have a second groove 22c that may span two second sources 21S. For example, the second connection structure 22 may have two endpoints separated by the second groove 22c, respectively coupling the two second sources 21S. The second groove 22c may have dimensions, such as a width W and a height H. In some embodiments, the width W and the height H may be greater than (e.g., both greater than) Figure 2 at least three times the size (e.g., maximum width, maximum diameter, average width, average diameter, etc.) of the filler in the molding compound layer 14 of Figure 2The molding compound layer 14. However, if the width W and the height H are too small, the resistance may be too high. For example, the width W and the height H can be between about 0.100 mm and about 0.300 mm, such as between about 0.200 mm and about 0.250 mm, such as about 0.225 mm.

[0036] Return reference Figure 2 , the drain of the first semiconductor chip 11 (such as Figure 3 the first drain 11D thereof) is coupled to the first substrate 10, and the drain of the second semiconductor chip 21 (such as Figure 3 the second drain 21D thereof) is coupled to the second substrate 20. In some embodiments, the drain of the first semiconductor chip 11 is coupled to the high-voltage terminal VH via the first substrate 10. The drain of the second semiconductor chip 21 is coupled to the low-voltage terminal (such as Figure 1A the low-voltage terminal VL thereof) via the second substrate 20. In this embodiment, the operating voltage or current of the first semiconductor chip 11 is higher than that of the second semiconductor chip 21. Separating the first semiconductor chip 11 (or the high-voltage chip) and the second semiconductor chip 21 (or the low-voltage chip) on different substrates can disperse the current, isolate the high-voltage and low-voltage circuits, and reduce the interference between the circuits. In some embodiments, separating them on different substrates can improve the heat dissipation ability and avoid the thermal interference of the high-voltage components on the low-voltage components.

[0037] The first connection structure 12 can be disposed between the first semiconductor chip 11 and the second substrate 20. The second connection structure 22 can be disposed between the second semiconductor chip 21 and the first substrate 10. In some embodiments, the first connection structure 12 can promote the heat dissipation of the first semiconductor chip 11 to the second substrate 20, and the second connection structure 22 can promote the heat dissipation of the second semiconductor chip 21 to the first substrate 10. In some embodiments, the first connection structure 12 and the second connection structure 22 can each have conductivity and serve as part of the circuit of the electronic component 1a. The first connection structure 12 and the second connection structure 22 can each include a conductive material such as a metal or a metal alloy. Examples of the conductive material can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more of them.

[0038] The first gate control layer 13 can be disposed between the first substrate 10 and the second substrate 20, such as between the first semiconductor chip 11 and the second substrate 20. The first gate control layer 13 can be coupled to the gate (such as Figure 7 the first gate 11G thereof) via a connecting member (such as Figure 3 the first gate terminal 13p thereof). The first gate control layer 13 can have Figure 7The opening 13h is configured to accommodate the first connection structure 12. For example, the first gate control layer 13 can surround the first connection structure 12 but does not contact the first connection structure 12. The first gate control layer 13 and the first connection structure 12 can be separated by the molding compound layer 14.

[0039] The second gate control layer 23 can be disposed between the first substrate 10 and the second substrate 20, such as between the first substrate 10 and the second semiconductor chip 21. The second gate control layer 23 can be coupled to the gate (such as Figure 6 the second gate terminal 23p of) via a connection member (such as Figure 3 the second gate 21G of). The second gate control layer 23 can have Figure 6 an opening 23h that is configured to accommodate the second connection structure 22. For example, the second gate control layer 23 can surround the second connection structure 22 but does not contact the second connection structure 22. The second gate control layer 23 and the second connection structure 22 can be separated by the molding compound layer 14.

[0040] As can be seen from Figure 2 the cross-sectional view, the first gate control layer 13 cuts through the first connection structure 12, and the second gate control layer 23 cuts through the second connection structure 22. However, as can be seen from Figure 4 the perspective view, the first connection structure 12 is located in the opening 13h of the first gate control layer 13 and does not contact the first gate control layer 13. The second connection structure 22 is located in the opening 23h of the second gate control layer 23 and does not contact the second gate control layer 23. Figure 4 Shown is a perspective view of a part of the electronic component 1a according to some embodiments of the present case. For the sake of simplicity, Figure 4 the molding compound layer 14 is not depicted.

[0041] The first gate control layer 13 and the second gate control layer 23 can be disposed at different heights from the first substrate 10. By using the first gate control layer 13 and the second gate control layer 23 as control layers for controlling the voltages of the first gate 11G and the second gate 21G, compared with wires, the circuit wiring area on the printed circuit board can be reduced. In addition, by using one first gate control layer 13, the first gates 11G of a plurality of first semiconductor chips 11 on the first substrate 10 can be controlled, which can simplify the circuit wiring and improve the circuit reliability.

[0042] The molding compound layer 14 can be disposed between the first substrate 10 and the second substrate 20, and cover the first semiconductor chip 11, the second semiconductor chip 21, the first connection structure 12, the second connection structure 22, the first gate control layer 13, and the second gate control layer 23. The molding compound layer 14 can include a molding compound (e.g., an epoxy molding compound) or other suitable materials, including (but not limited to) epoxy resins, phenolic resins, silicon-containing resins, etc. or combinations thereof.

[0043] Referring to Figure 5 , Figure 5 FIG. shows an exploded view of the electronic component 1a according to some embodiments of the present case. A plurality of chips can be disposed on the first substrate 10, such as the first semiconductor chip 11 and the third semiconductor chip 11'. The third semiconductor chip 11' can have one or more electrical terminals, such as the third gate 11'G, the third source 11'S, and the third drain (not shown). The first semiconductor chip 11 and the third semiconductor chip 11' can be adjacent to each other, and the distance D1 between the first gate 11G and the third gate 11'G can be less than the distance D2 between the first source 11S and the third source 11'S, so as to disperse the heat source and avoid heat accumulation from affecting the heat dissipation efficiency. Further, dispersing the heat source can reduce the junction temperature.

[0044] Referring to Figure 6 and Figure 7 , Figure 6 FIG. shows a perspective view of the electronic component 1a after removing the second substrate 20. Figure 7 FIG. shows a perspective view of the electronic component 1a after removing the first substrate 10. The first gate control layer 13 couples the gate of the first semiconductor chip 11 (such as the first gate 11G of Figure 3 ) to the first lead VGH. The high-voltage terminal VH is coupled to the first lead VGH via the first substrate 10, the first semiconductor chip 11, and the first gate control layer 13. The second gate control layer 23 couples the gate of the second semiconductor chip 21 (such as the second gate 21G of Figure 3 ) to the second lead VGL. The low-voltage terminal VL is coupled to the second lead VGL via the second substrate 20, the second semiconductor chip 21, and the second gate control layer 23.

[0045] Referring to Figure 6 and Figure 7 , and simultaneously referring to Figure 8 , Figure 8 FIG. shows a schematic diagram of the current direction of the electronic component 1a according to some embodiments of the present case.

[0046] In some embodiments, as in direction 1, current can flow from the high-voltage terminal VH into the first substrate 10. As in direction 2, the current can flow through the circuit of the first substrate 10 to the first semiconductor chip 11. As in direction 3, the first semiconductor chip 11 and the first connection structure 12 can transfer the current to the second substrate 20. The current can flow through the circuit of the second substrate 20 to the output terminal V out or transfer it to the second semiconductor chip 21 through the circuit of the second substrate 20. As in direction 4, the second semiconductor chip 21 and the second connection structure 22 can transfer the current to the first substrate 10. The circuit of the first substrate 10 can transfer the current to the third connection structure 24. As in direction 5, the third connection structure 24 can transfer the current to the second substrate 20. As in direction 6, the circuit of the second substrate 20 can transfer the current to the low-voltage terminal VL.

[0047] In some embodiments, the third connection structure 24 can be disposed between the first substrate 10 and the second substrate 20. The third connection structure 24 can be conductive and can be used to provide an electrical connection between the first substrate 10 and the second substrate 20. The third connection structure 24 can be disposed around or outside the second gate control layer 23, for example, not disposed in the opening 23h of the second gate control layer 23.

[0048] Referring to Figure 9 , Figure 9 is a flowchart of a method for manufacturing an electronic component according to certain embodiments of the present case. The manufacturing method includes steps 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100. The above steps or stages have been simplified for a better understanding of aspects of the present disclosure. The electronic component formed through the above steps can be the same as the Figure 2 shown electronic component 1a.

[0049] Step 90 is to provide a first substrate, such as Figure 2 the first substrate 10.

[0050] Step 91 is to dispose a first semiconductor chip on the first substrate, such as Figure 2 the first semiconductor chip 11. The first semiconductor chip 11 can have a first gate 11G, a first source 11S, and a first drain 11D. The first gate 11G and the first source 11S can be on the same side of the first semiconductor chip 11 while the first drain 11D is on the opposite side. In some embodiments, the first semiconductor chip 11 can be coupled to Figure 2 the first substrate 10 via a silver sintering process (or silver sintering bonding technology). For example, in Figure 2 , a silver sintering coating 11s can be disposed between the first drain 11D and the first substrate 10.

[0051] Step 92 is to provide a first gate control layer on the first gate, such as Figure 2 the first gate control layer 13. The first gate control layer 13 can be coupled to the first gate 11G via Figure 7 the first gate terminal 13p.

[0052] Step 93 provides a second substrate, such as Figure 2 the second substrate 20.

[0053] Step 94 is to provide a second semiconductor chip on the second substrate, such as Figure 2 the second semiconductor chip 21. The second semiconductor chip 21 may have a second gate 21G, a second source 21S, and a second drain 21D. The second gate 21G and the second source 21S may be located on the same side of the second semiconductor chip 21, while the second drain 21D is located on the opposite side. In some embodiments, the second semiconductor chip 21 can be coupled to Figure 2 the second substrate 20 via a silver sintering process or silver sintering bonding technology. For example, in Figure 2 a silver sintering coating 21s can be provided between the second drain 21D and the second substrate 20.

[0054] Step 95 is to provide a second gate control layer on the second gate, such as Figure 2 the second gate control layer 23. The second gate control layer 23 can be coupled to the second gate 21G via Figure 6 the second gate terminal 23p.

[0055] Step 96 is to provide a first connection structure on the first source, such as Figure 2 the first connection structure 12. For example, the first connection structure 12 is placed in Figure 7 the opening 13h.

[0056] Step 97 is to provide a second connection structure on the first substrate, such as Figure 2 the second connection structure 22.

[0057] In some embodiments, the first connection structure and the second connection structure in steps 96 and 97 can be provided in the same step. In some embodiments, the first connection structure and the second connection structure in steps 96 and 97 can be implemented before step 93.

[0058] Step 98 is to provide a first lead and a second lead on the first substrate, such as Figure 1Athe first lead VGH and the second lead VGL. In some embodiments, the first lead VGH and the second lead VGL can be bonded to the first substrate 10 via a silver sintering process or an ultrasonic bonding technology. In some embodiments, step 98 may further include connecting the endpoints of other external circuits, such as Figure 1A the output terminal V out , the high-voltage terminal VH, and the low-voltage terminal VL. In some embodiments, step 98 can be implemented before step 93. In some embodiments, step 98 can be implemented before step 91.

[0059] Step 99 is to couple the second source electrode to the second connection structure, such as Figure 2 the second connection structure 22 of . For example, in step 97, the second connection structure 22 is disposed on the first substrate 10. The second substrate 20 (and the second semiconductor chip 21 and the second gate control layer 23 thereon) obtained in steps 93, 94, and 95 can be turned over and bonded to the first substrate 10 (and the first semiconductor chip 11, the first gate control layer 13, the first connection structure 12, and the second connection structure 22 thereon) obtained in steps 90, 91, 92, 96, and 97. In this way, the second substrate 20 can be connected to the first semiconductor chip 11 via the first connection structure 12, and the first substrate 10 can be connected to the second semiconductor chip 21 via the second connection structure 22.

[0060] Step 100 is to form a molding compound layer, such as Figure 2 the molding compound layer 14 of . In some embodiments, the molding compound layer 14 is formed by molding techniques such as transfer molding or compression molding.

[0061] Spatial relative terms such as "beneath", "below", "lower", "above", "upper", "left", "right", etc. may be used herein for ease of description to describe the relationship of one component or feature to another or other components or features as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device when in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or there may be intermediate components.

[0062] As used herein, the terms "about," "substantially," "essentially," and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces positioned along the same plane that is within a few micrometers (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of being positioned along the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value that is within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0063] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments presented herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic component, characterized in that, Comprising: A first substrate; A first semiconductor chip having a first gate, a first source, and a first drain, wherein the first drain is located on one side of the first semiconductor chip, and the first gate and the first source are located on the opposite side of the first semiconductor chip, and wherein the first drain is coupled to the first substrate; A second substrate physically separated from the first substrate; A second semiconductor chip having a second gate, a second source, and a second drain, wherein the second drain is located on one side of the second semiconductor chip, and the second gate and the second source are located on the opposite side of the second semiconductor chip, and wherein the second drain is coupled to the second substrate, and wherein the first semiconductor chip and the second semiconductor chip are located between the first substrate and the second substrate; A first connection structure that couples the first source to the second substrate; And A second connection structure that couples the second source to the first substrate.

2. The electronic component according to claim 1, further comprising: A first gate control layer disposed between the first substrate and the second substrate and coupled to the first gate.

3. The electronic component according to claim 2, wherein the first gate control layer has an opening configured to accommodate the first connection structure.

4. The electronic component according to claim 2, wherein the first gate control layer couples the first gate to a first lead.

5. The electronic component according to claim 2, further comprising: A second gate control layer disposed between the first substrate and the second substrate and coupled to the second gate.

6. The electronic component according to claim 5, wherein the first gate control layer couples the first gate to a first lead and the second gate control layer couples the second gate to a second lead.

7. The electronic component according to claim 6, wherein the first substrate includes a high-voltage terminal of an inverter, which is coupled to the first lead via the first substrate and the first gate control layer.

8. The electronic component according to claim 6, wherein the second substrate includes a low-voltage terminal of an inverter, which is coupled to the second lead via the second substrate and the second gate control layer.

9. The electronic component according to claim 1, further comprising: A molding compound layer disposed between the first substrate and the second substrate, wherein the first connection structure has a groove, and the size of the groove is at least three times greater than the size of the filler in the molding compound layer.

10. The electronic component according to claim 1, further comprising: A silver sintered coating disposed between the first connection structure and the first source.

11. The electronic component according to claim 1, further comprising: A silver sintered coating disposed between the first drain and the first substrate.

12. The electronic component according to claim 1, wherein the first substrate and the second substrate include an Active Metal Brazing (AMB) substrate.

13. The electronic component according to claim 1, further comprising: A third semiconductor chip disposed on the first substrate and having a third gate and a third source, wherein the distance between the third gate and the first gate is less than the distance between the third source and the first source.

14. A manufacturing method of an electronic component, characterized in that, Comprising: Providing a first substrate; Disposing a first semiconductor chip on the first substrate; Providing a second substrate; Disposing a second semiconductor chip on the second substrate; Coupling the second substrate to the first semiconductor chip via a first connection structure; And Coupling the first substrate to the second semiconductor chip via a second connection structure.

15. The manufacturing method according to claim 14, wherein the first semiconductor chip has a first gate, a first source, and a first drain, wherein the first drain is located on one side of the first semiconductor chip, and the first gate and the first source are located on the opposite side of the first semiconductor chip, wherein the first drain is coupled to the first substrate, and the manufacturing method further comprises: Disposing a first connection structure on the first source.

16. The manufacturing method according to claim 14, wherein the second semiconductor chip has a second gate, a second source, and a second drain, wherein the second drain is located on one side of the second semiconductor chip, and the second gate and the second source are located on the opposite side of the second semiconductor chip, wherein the second drain is coupled to the second substrate, and the manufacturing method further comprises: Disposing a second connection structure on the first substrate.

17. The manufacturing method according to claim 14, further comprising: Disposing a first gate control layer on the first gate, which is coupled to the first gate.

18. The manufacturing method according to claim 17, further comprising: Disposing a second gate control layer on the second gate, which is coupled to the second gate.

19. The manufacturing method according to claim 14, further comprising: Disposing a first lead and a second lead on the first substrate.

20. The manufacturing method according to claim 14, wherein the first semiconductor chip is bonded to the first substrate via a silver sintering bonding technique.

21. The manufacturing method according to claim 14, wherein the first connection structure is bonded to the first source via a silver sintering bonding technique.

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