Spread spectrum clock generator and electronic device

Abstract

The invention provides a spread spectrum clock generator and an electronic device, and the spread spectrum clock generator is additionally provided with a second loop on the basis of a conventional clock generator loop (namely a first loop), and the second loop leads out a corresponding voltage from a loop filter in the conventional clock generator loop. The modulation frequency and the modulation depth of spread spectrum are carried out on the output of a ring oscillator in a traditional clock generator loop by generating a corresponding second voltage based on the voltage, the scheme is simple and easy to implement, the problem of electromagnetic interference (EMI) can be effectively solved, the use of a sigma-delta modulator can be avoided, the clock jitter output by the first loop is greatly reduced, and the performance of the clock generator is improved. The reliability is improved, and the application requirement of the spread spectrum phase-locked loop is met. Furthermore, the second loop is realized by adopting a pure analog circuit, the structure is simple, the area is small, and the cost is low. In addition, by trimming parameters in the second loop, the modulation frequency and the modulation depth of the spread spectrum do not change along with the process, the voltage and the temperature (PVT).

Description

Technical Field

[0001] The present invention relates to the technical field of clock generators, and particularly to a spread spectrum clock generator and an electronic device. Background Art

[0002] With the rapid development of CMOS (Complementary Metal Oxide Semiconductor) technology, the operating frequency of electronic systems has been continuously increasing, and the requirements for high-speed clocks have become more stringent. Nowadays, the data rates of wired communication systems such as DDR (Double Data Rate), PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard), or HDMI (High Definition Multimedia Interface) have increased rapidly, and the EMI (Electromagnetic Interference) problem caused by high-speed clocks has become more important. It can interfere with normal data transmission and even cause data errors.

[0003] A spread spectrum clock generator (SSCG) can, by means of frequency modulation, disperse the energy concentrated in a narrow frequency band range into a set wide frequency band range, thereby effectively reducing EMI.

[0004] Existing spread spectrum clock generators, although they can effectively reduce EMI, still have deficiencies such as low reliability, complex circuit structures, and high costs. Summary of the Invention

[0005] The purpose of the present invention is to provide a spread spectrum clock generator and an electronic device, which have a simple circuit structure, low cost, and high reliability.

[0006] To achieve the above purpose, the present invention provides a spread spectrum clock generator, which includes:

[0007] A first loop, which includes a loop filter and a ring oscillator, and is used to generate a first voltage for controlling the oscillation frequency output by the ring oscillator based on the voltage output from the first output terminal of the loop filter;

[0008] A second loop, coupled to the second output terminal of the loop filter, and is used to generate a second voltage for controlling the modulation frequency and modulation depth of the output of the ring oscillator to perform spread spectrum based on the voltage output from the second output terminal of the loop filter.

[0009] Optionally, the first loop further includes a phase frequency detector, a charge pump, a first gain amplifier, and a frequency divider. The phase frequency detector, the charge pump, the loop filter, and the first gain amplifier are sequentially coupled. A first input terminal of the phase frequency detector is coupled to an output terminal of the frequency divider, and a second input terminal of the phase frequency detector is coupled to an input clock signal. The first gain amplifier is configured to convert a voltage output from a first output terminal of the loop filter into the first voltage and provide it to a first control terminal of the ring oscillator. An output terminal of the ring oscillator is coupled to an input terminal of the frequency divider and an input terminal of the ring oscillator.

[0010] Optionally, the charge pump includes an operational amplifier, a first MOS transistor, a second MOS transistor, and a first adjustable resistor. A first input terminal of the operational amplifier is coupled to a bandgap reference voltage. A second input terminal of the operational amplifier is coupled to a first end of the first adjustable resistor and a drain of the first MOS transistor. An output terminal of the operational amplifier is coupled to a gate of the first MOS transistor and a gate of the second MOS transistor. A second end of the first adjustable resistor is grounded. A drain of the second MOS transistor is coupled to an input terminal of the loop filter to provide a charge and discharge current.

[0011] Optionally, the loop filter includes a filter resistor and a first filter capacitor. A first end of the filter resistor serves as the first output terminal of the loop filter, and a second end of the filter resistor serves as the second output terminal of the loop filter and is coupled to one end of the first filter capacitor and the second loop. The other end of the first filter capacitor is grounded.

[0012] Optionally, the loop filter is a multi - order filter of two - order or higher order, and it further includes at least a second filter capacitor. One end of the second filter capacitor is coupled to the first end of the filter resistor, and the other end of the second filter capacitor is grounded.

[0013] Optionally, the second loop includes a triangular wave generator and a second gain amplifier. A first input terminal of the triangular wave generator is coupled to the second output terminal of the loop filter, and a second input terminal of the triangular wave generator is coupled to a corresponding reference voltage. The triangular wave generator is configured to output the voltage output from the second output terminal of the loop filter as a triangular wave voltage. A period of the triangular wave voltage is used to control a modulation frequency for spreading the frequency of the output of the ring oscillator, and an amplitude of the triangular wave voltage is used to control a modulation depth for spreading the frequency of the output of the ring oscillator. An input terminal of the second gain amplifier is coupled to an output terminal of the triangular wave generator and is configured to convert the triangular wave voltage into the second voltage to provide it to a second control terminal of the ring oscillator.

[0014] Optionally, the triangular wave generator includes a transconductance amplifier and an integrating capacitor. The first input terminal of the transconductance amplifier is coupled to the second output terminal of the loop filter, and the second input terminal of the transconductance amplifier is coupled to the reference voltage. The transconductance amplifier is configured to convert the difference between the voltage at the second output terminal of the loop filter and the reference voltage into an error current. The integrating capacitor is coupled to the output terminal of the transconductance amplifier and the input terminal of the second gain amplifier, and is configured to integrate the error current to generate the triangular wave voltage.

[0015] Optionally, the error current △I = △V CTRL_R / R2, the amplitude of the triangular wave voltage △V = VBG / k, the period of the triangular wave voltage T = a*R2*C2, where △VCTRL_R is the difference between the voltage at the second output terminal of the loop filter and the reference voltage, 1 / R2 is the transconductance value of the transconductance amplifier, C2 is the capacitance value of the integrating capacitor, VBG is the bandgap reference voltage, a is a constant, and k is a coefficient.

[0016] Optionally, k = a*R2*C2 / (2*C1*R). By adjusting the ratio of R2 to R and the ratio of C2 to C1, the coefficient k is made independent of process, voltage, and temperature, and thus the modulation depth is made independent of process, voltage, and temperature, where R = VBG / ICP, ICP is the charge and discharge current of the loop filter, and C1 is the capacitance value of the first filter capacitor at the second output terminal of the loop filter.

[0017] Optionally, the transconductance amplifier includes:

[0018] A differential input circuit, coupled to the reference voltage and the second output terminal of the loop filter, and configured to convert the voltage at the second output terminal of the loop filter into a first current and the reference voltage into a second current;

[0019] A first current mirror, coupled to the differential input circuit, and configured to mirror-output the first current;

[0020] A second current mirror, coupled to the differential input circuit and the output terminal of the transconductance amplifier, and configured to mirror-output the second current;

[0021] A third current mirror, coupled to the first current mirror and the output terminal of the transconductance amplifier, and configured to mirror-output the current output by the first current mirror again, so that the output terminal of the transconductance amplifier outputs the error current.

[0022] Optionally, the differential input circuit includes a first input transistor, a second input transistor, and a second adjustable resistor. The gate of the first input transistor is coupled to the second output terminal of the loop filter. The gate of the second input transistor is coupled to the reference voltage. The source of the first input transistor is coupled to one end of the second adjustable resistor. The source of the second input transistor is coupled to the other end of the second adjustable resistor. The second adjustable resistor determines the transconductance value of the transconductance amplifier.

[0023] Optionally, the spread spectrum clock generator further includes at least one of the following (1) to (4):

[0024] (1) The first current mirror includes a first mirror transistor and a second mirror transistor. The gates of the first mirror transistor and the second mirror transistor are both coupled to the drain of the first input transistor. The drain of the second mirror transistor is coupled to the source of the first input transistor. The drain of the first mirror transistor serves as the output terminal of the first current mirror and is coupled to the input terminal of the third current mirror.

[0025] (2) The second current mirror includes a third mirror transistor and a fourth mirror transistor. The gates of the third mirror transistor and the fourth mirror transistor are both coupled to the drain of the second input transistor. The drain of the third mirror transistor is coupled to the source of the second input transistor. The drain of the fourth mirror transistor serves as the output terminal of the second current mirror and is coupled to the output terminal of the third current mirror and the output terminal of the transconductance amplifier.

[0026] (3) The third current mirror includes a fifth mirror transistor and a sixth mirror transistor. The gate of the fifth mirror transistor, the drain of the fifth mirror transistor, and the gate of the sixth mirror transistor are mutually coupled and serve as the input terminal of the third current mirror and are coupled to the output terminal of the first current mirror. The drain of the sixth mirror transistor serves as the output terminal of the third current mirror and is coupled to the output terminal of the second current mirror and the output terminal of the transconductance amplifier.

[0027] (4) The differential input circuit further includes a first current source, a second current source, a third current source, and a fourth current source. One end of the first current source is coupled to the drain of the first input transistor. One end of the second current source is coupled to the source of the first input transistor. One end of the third current source is coupled to the drain of the second input transistor. One end of the fourth current source is coupled to the source of the second input transistor.

[0028] Optionally, by adjusting the magnitude of the reference voltage, the spread spectrum mode of the spread spectrum clock generator can be changed, where:

[0029] When the adjusted reference voltage is equal to the set value, the spread spectrum clock generator achieves center spread spectrum.

[0030] When the reference voltage is adjusted to be lower than the set value, the spread spectrum clock generator realizes downward spread spectrum;

[0031] When the reference voltage is adjusted to be higher than the set value, the spread spectrum clock generator realizes upward spread spectrum.

[0032] Based on the same inventive concept, the present invention also provides an electronic device, which includes the spread spectrum clock generator as described in the present invention.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] 1. By adding a second loop on the basis of the traditional clock generator loop (i.e., the first loop), and the second loop extracts the corresponding voltage from the loop filter in the traditional clock generator loop, and generates a corresponding second voltage based on this voltage, which is used to control the modulation frequency and modulation depth of the output of the ring oscillator in the traditional clock generator loop for spread spectrum. The solution is simple and easy to implement, can effectively improve the electromagnetic interference (EMI) problem, and can avoid using a sigma-delta modulator, thereby greatly reducing the clock jitter of the output of the first loop, improving the reliability, and being very suitable for the application requirements of the spread spectrum phase-locked loop.

[0035] 2. The second loop includes a triangular wave generator and a gain amplifier, which is implemented by a pure analog circuit, and has a simple circuit structure, small area, low cost, and low power consumption.

[0036] 3. It is possible to change the modulation frequency of the output of the ring oscillator for spread spectrum by adjusting or trimming the resistance value of the transconductance amplifier and the capacitance value of the integration capacitor in the second loop, and making it independent of PVT (i.e., process, voltage, temperature) changes. At the same time, it is also possible to adjust the corresponding coefficient by adjusting or trimming the bias current of the transconductance amplifier, and then change the modulation depth of the output of the ring oscillator for spread spectrum, and making it also independent of PVT changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0038] Figure 1 is a schematic structural diagram of a spread spectrum clock generator according to an embodiment of the present invention,

[0039] Figure 2 is a schematic diagram of an example circuit of a charge pump in a spread spectrum clock generator according to an embodiment of the present invention.

[0040] Figure 3It is a schematic diagram of an example circuit of a loop filter in a spread-spectrum clock generator according to an embodiment of the present invention.

[0041] Figure 4 It is a schematic diagram of an example circuit of a ring oscillator in a spread-spectrum clock generator according to an embodiment of the present invention.

[0042] Figure 5 It is a schematic diagram of an example circuit of a triangular wave generator in a spread-spectrum clock generator according to an embodiment of the present invention.

[0043] Figure 6 It is a schematic diagram of an example circuit of a transconductance amplifier in a spread-spectrum clock generator according to an embodiment of the present invention.

[0044] Figure 7 It is a schematic diagram of an example of a triangular wave voltage of a triangular wave generator in a spread-spectrum clock generator according to an embodiment of the present invention.

[0045] Figure 8 It is a schematic diagram of some signal timing examples of a spread-spectrum clock generator according to an embodiment of the present invention.

[0046] Figure 9 It is a schematic diagram showing that the spread-spectrum mode changes when the reference voltage is changed in a spread-spectrum clock generator according to an embodiment of the present invention. Detailed implementation manners

[0047] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other instances, some well-known technical features are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to determine the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0048] The technical solution proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0049] Please refer to Figure 1 , an embodiment of the present invention provides a spread spectrum clock generator, which includes a first loop loop1 and a second loop loop2. The first loop loop1 is the main loop and controls the oscillation frequency (also known as the "clock frequency") output by the ring oscillator (ring OSC) 14 through a first voltage Vc1. The second loop loop2 is an auxiliary loop, which is drawn from the second output terminal (not marked in the figure) of the loop filter 12 in the first loop loop1, and controls the modulation frequency and modulation depth of the spread spectrum of the output of the ring oscillator 14 by generating a second voltage Vc2.

[0050] Among them, the first loop loop1 can adopt a traditional clock generator loop, which may include a frequency discriminator and phase detector 10, a charge pump 11, a loop filter 12, a first gain amplifier (AMP1) 13, a ring oscillator (ring OSC) 14, and a frequency divider (DIV) 15.

[0051] The first input terminal of the frequency discriminator and phase detector 10 is coupled to the output terminal of the frequency divider 15 to receive the feedback clock signal CLK_FB provided by the frequency divider 15. The second input terminal of the frequency discriminator and phase detector 10 receives the input clock signal CLK_IN. The frequency discriminator and phase detector 10 is used to compare the phases of the input clock signal CLK_IN and the feedback clock signal CLK_FB.

[0052] The input terminal of the charge pump 11 is coupled to the output terminal of the frequency discriminator and phase detector 10, and is used to perform charging or discharging according to the output result of the frequency discriminator and phase detector 10. Among them, when the phase of the input clock signal CLK_IN leads the feedback clock signal CLK_FB output by the frequency divider 15, it indicates that the current output frequency of the ring oscillator 14 (i.e., the oscillation frequency output by the ring oscillator 14, such as Figure 8 the fout in Figure 8In the case where the phase of the feedback clock signal CLK_FB lags behind the phase of the input clock signal CLK_IN, it indicates that the current output frequency fout of the ring oscillator 14 is lower than the target frequency. The frequency discriminator and phase detector 10 controls the charge pump 11 to output a relatively large charging current ICP to increase the output frequency fout of the ring oscillator 14. Conversely, when the phase of the feedback clock signal CLK_FB leads the phase of the input clock signal CLK_IN, it means that the current output frequency of the ring oscillator 14 is higher than the target frequency. The frequency discriminator and phase detector 10 controls the charge pump to output a relatively large discharging current ICP to decrease the output frequency of the ring oscillator 14. Eventually, the output frequency of the ring oscillator 14 changes periodically in a triangular wave shape according to the target frequency, and the working timing is as Figure 8 shown.

[0053] The input end of the loop filter 12 is coupled to the output end of the charge pump 11 and is used to filter the output of the charge pump 11. Its first output end is coupled to the output end of the first gain amplifier 12 to provide a voltage V CTRL to the first gain amplifier 12, and its second output end is coupled to the second loop loop2 to provide a voltage V CTRL_R . Among them, V CTRL is different from V CTRL_R .

[0054] The first input end (for example, the “+” input end) of the first gain amplifier 13 is coupled to the first output end of the loop filter 12. The output end of the first gain amplifier 13 is coupled to the second input end (for example, the “-” input end) of the first gain amplifier 13 and the first control end (not marked in the figure) of the ring oscillator 14. The first gain amplifier 13 is used to convert (for example, “amplify to”) the voltage V CTRL output from the first output end of the loop filter 12 into a first voltage Vc1 and provide it to the first control end of the ring oscillator 14 to control the oscillation frequency of the ring oscillator 14.

[0055] The ring oscillator 14 is used to oscillate and spread spectrum under the control of the first voltage Vc1 output by the first gain amplifier 13 and the second voltage Vc2 output by the second loop loop2, and then generate a signal with a corresponding output frequency. Among them, the first voltage Vc1 controls the oscillation frequency output by the ring oscillator 14, and the second voltage Vc2 controls the modulation frequency and modulation depth of the output of the ring oscillator 14 for spreading spectrum.

[0056] The input end of the frequency divider 15 is coupled to the output end of the ring oscillator 14, and the output end of the frequency divider 15 is coupled to the first input end of the frequency discriminator and phase detector 10. The frequency divider 15 is used to perform frequency division processing on the spread-spectrum output frequency of the ring oscillator 14 and output a feedback clock signal CLK_FB to the frequency discriminator and phase detector 10.

[0057] The second loop, loop2, includes a triangular wave generator 16 and a second gain amplifier (AMP2) 17. The first input terminal of the triangular wave generator 16 is coupled to the second output terminal of the loop filter 12 to access the voltage V CTRL_R , the second input terminal of the triangular wave generator 16 is coupled to the corresponding reference voltage VREF, and the output terminal of the triangular wave generator 16 is coupled to the first input terminal (e.g., its “+” input terminal) of the second gain amplifier 17. The triangular wave generator 16 is configured to output the voltage V CTRL_R output from the second output terminal of the loop filter 12 as a triangular wave voltage V CTRL_C with reference to the reference voltage VREF, and please refer to Figure 7 , the period T of the triangular wave voltage V CTRL_C is used to control the modulation frequency for frequency spreading of the output of the ring oscillator 14, and the amplitude ⊿V of the triangular wave voltage V CTRL_C is used to control the modulation depth for frequency spreading of the output of the ring oscillator 14.

[0058] The first input terminal (e.g., its “+” input terminal) of the second gain amplifier 17 is coupled to the output terminal of the triangular wave generator 16, and the second input terminal (e.g., its “−” input terminal) of the second gain amplifier 17 is coupled to the second control terminal (not shown) of the ring oscillator 14. The second gain amplifier 17 is configured to convert (e.g., “amplify to”) the triangular wave voltage V CTRL_C output by the triangular wave generator 16 into a second voltage Vc2 to be provided to the second control terminal of the ring oscillator 14.

[0059] It should be understood that the above frequency discriminator and phase detector 10, charge pump 11, loop filter 12, first gain amplifier 13, frequency divider 14, ring oscillator 15, triangular wave generator 16, and second gain amplifier 17 can all adopt any suitable circuit design.

[0060] In one example, please refer to Figure 2, the charge pump 11 includes an operational amplifier OP, a first MOS transistor P1, a second MOS transistor P2, and a first adjustable resistor R. The first input terminal (e.g., "-") of the operational amplifier OP is coupled to a bandgap reference voltage VBG. The second input terminal (e.g., "+") of the operational amplifier OP is coupled to the first end of the first adjustable resistor R and the drain of the first MOS transistor P1. The output terminal of the operational amplifier OP is coupled to the gates of the first MOS transistor P1 and the second MOS transistor P2. The second end of the first adjustable resistor R is grounded. The drain of the second MOS transistor P2 is coupled to the input terminal of the loop filter 13 to provide a charge and discharge current ICP. In this example, the sources of the first MOS transistor P1 and the second MOS transistor P2 are both connected to a power supply voltage (not shown). The first MOS transistor P1 and the second MOS transistor P2 are both PMOS transistors. However, in other examples of the present invention, one or both of the first MOS transistor P1 and the second MOS transistor P2 can be replaced with NMOS transistors.

[0061] In one example, please refer to Figure 3 , the loop filter 12 includes a filter resistor R1 and a first filter capacitor C1. The first end of the filter resistor R1 serves as the first output terminal of the loop filter 12 and is coupled to the input terminal (e.g., its "+" input terminal) of the first gain amplifier 13. The second end of the filter resistor R1 serves as the second output terminal of the loop filter 12 and is coupled to one end of the first filter capacitor C1 and the second loop loop2. The other end of the first filter capacitor C1 is grounded.

[0062] In other examples, the loop filter 12 can be a multi-stage filter of two or more stages. It can be formed by connecting multiple first-order RC filters in series, or by connecting a first-order RC filter and multiple filter capacitors in parallel, or by combining other arbitrarily suitable filters in series or parallel, etc. The present invention does not make specific limitations in this regard. The first output terminal and the second output terminal of the loop filter 12 formed by the multi-stage filter are the output terminals of two different stages of the multi-stage filter. For example, the first output terminal of the loop filter 12 is the output terminal of the last stage filter of the multi-stage filter, and its second output terminal is the output terminal of any stage filter in front of the last stage filter of the multi-stage filter.

[0063] For another example, please refer to Figure 3 , the loop filter 12 is a two-stage filter, which includes a filter resistor R1, a first filter capacitor C1, and a second filter capacitor C0. The filter resistor R1 and the first filter capacitor C1 are connected in series to form the first stage filter. On the other hand, the second filter capacitor C0 serves as the second stage filter. And the first end of the filter resistor R1 is coupled to one end of the second filter capacitor C0, and forms the output terminal of the two-stage filter (i.e., the first output terminal of the loop filter 12) and outputs a voltage V CTRL, the second end of the filtering resistor R1 is coupled to one end of the first filtering capacitor C1 and serves as the output end of the first-order filter therein, so as to form the second output end of the loop filter 12 and output the voltage V CTRL_R , the other end of the first filtering capacitor C1 is grounded. Figure 3 The loop filter 12 of

[0064]

[0065] wherein the filtering resistor R1, the first filtering capacitor C1 and the second filtering capacitor C0 jointly determine the zero point, pole position and frequency response characteristics of the second-order loop filter 12. By adjusting the filtering resistor R1, the first filtering capacitor C1 and the second filtering capacitor C0, the cut-off frequency, stability and noise suppression ability of the loop filter 12 can be optimized. The denominator of the transfer function H(s) of the loop filter 12 in the above formula has 2 poles (the denominator is a quadratic polynomial s 2 term, so there are two poles), so it is a second-order filter. Of course, the loop filter 12 can also be a multi-order filter with more than two orders. The number of poles in the denominator of the transfer function H(s) can achieve the number of orders of the filter.

[0066] In one example, please refer to Figure 4 , the ring oscillator 14 includes n cascaded inverters INV1 to INVn in sequence. INV1 is the first-stage inverter in the ring oscillator 14, and INVn is the last-stage inverter (or called the "nth-stage inverter") in the ring oscillator 14. One control end of each stage of inverter is coupled to the output end of the first gain amplifier 13 to access the first voltage Vc1; the other control end of each stage of inverter is coupled to the output end of the second gain amplifier 17 to access the second voltage Vc2. The input end of the first-stage inverter INV1 is the input end in of the ring oscillator 14, and the output end of the last-stage inverter INVn is the output end out of the ring oscillator 14.

[0067] In one example, please refer to Figure 5 , the triangular wave generator 16 includes a transconductance amplifier OTA and an integrating capacitor C2. The first input end (for example, the "-" input end) of the transconductance amplifier OTA is coupled to the second output end of the loop filter 12 to access the voltage V CTRL_R , the second input end (for example, the "+" input end) of the transconductance amplifier OTA is coupled to the reference voltage VREF. The transconductance amplifier OTA is used to amplify the voltage V CTRL_R at the second output end of the loop filter 12 and the difference △V CTRL_Ris converted into an error current ΔI. An integrating capacitor C2 is coupled to the output terminal of a transconductance amplifier OTA and the input terminal of a second gain amplifier 17, and is configured to integrate the error current ΔI output by the transconductance amplifier OTA to generate a triangular wave voltage V CTRL_C . Wherein, the error current ΔI is equal to the difference ΔV between VCTRL_R and a reference voltage VREF CTRL_R multiplied by the transconductance value 1 / R2 of the transconductance amplifier OTA. This error current ΔI forms a triangular wave voltage V CTRL_C on the integrating capacitor C2, and the result is equal to [ΔI(T / 2)] / C2. Substituting T = a*R2C2 and simplifying, we get ΔV CTRL_C = a*ΔV CTRL_R . Wherein, a is a constant.

[0068] The transconductance amplifier OTA can be specifically implemented by any suitable circuit design. For example, VREF and VBG are in a coefficient relationship, and the transconductance amplifier OTA can adopt the source degeneration technology to produce a current amplification factor that is strongly related to the reciprocal R2 of its transconductance value (1 / R2).

[0069] As an example, please refer to Figure 6 , the transconductance amplifier OTA includes a differential input circuit 161, a first current mirror 162, a second current mirror 163, and a third current mirror 164. Wherein, the differential input circuit 161 is coupled to the reference voltage VREF and the second output terminal of the loop filter 12, and is configured to convert the voltage V CTRL_R at the second output terminal of the loop filter 12 into a first current (not shown), and convert the reference voltage VREF into a second current (not shown). The first current mirror 162 is coupled to the differential input circuit 161 and is configured to mirror-output the first current (not shown). The second current mirror 163 is coupled to the differential input circuit 161 and the output terminal out of the transconductance amplifier OTA, and is configured to mirror-output the second current. The third current mirror 164 is coupled to the output terminal of the first current mirror 161 and the output terminal of the transconductance amplifier OTA, and is configured to mirror-output the current output by the first current mirror 161 again. Then, the difference between the mirror current output by the second current mirror 163 and the mirror current output by the third current mirror 164 is obtained at the output terminal of the transconductance amplifier OTA as the error current ΔI.

[0070] Optionally, the differential input circuit 161 includes a first input transistor N1, a second input transistor N2, and a second adjustable resistor R0. The gate of the first input transistor N1 is coupled to the second output terminal of the loop filter 12 to access the voltage V CTRL_R, the gate of the second input transistor N2 is coupled to the reference voltage VREF. The source of the first input transistor N1 is coupled to one end of the second adjustable resistor R0, and the source of the second input transistor N2 is coupled to the other end of the second adjustable resistor R0. Among them, the resistance value of the second adjustable resistor R0 can determine the transconductance value (1 / R2) of the transconductance amplifier OTA, and it can be selected as any appropriate value according to needs. The present invention does not make specific limitations on this. In one example, the resistance value of the second adjustable resistor R0 can be equal to 2*R2, where R2 is the reciprocal of the transconductance value (1 / R2) of the transconductance amplifier OTA. The first input transistor N1 and the second input transistor N2 have the same conduction type, for example, both are NMOS transistors, or both are PMOS transistors.

[0071] Further, the differential input circuit 161 further includes a first current source I1, a second current source I2, a third current source I3, and a fourth current source I4. One end of the first current source I1 is coupled to the drain of the first input transistor N1, one end of the second current source I2 is coupled to the source of the first input transistor N1, one end of the third current source I3 is coupled to the drain of the second input transistor N2, and one end of the fourth current source I4 is coupled to the source of the second input transistor N2. The other ends of the first current source I1 and the third current source I3 are both coupled to the power supply voltage (not shown), and the other ends of the second current source I2 and the fourth current source I4 are both grounded.

[0072] Optionally, the first current mirror 162 includes a first mirror transistor M1 and a second mirror transistor M2. The gates of the first mirror transistor M1 and the second mirror transistor M2 are both coupled to the drain of the first input transistor N1. The drain of the second mirror transistor M2 is coupled to the source of the first input transistor N1. The drain of the first mirror transistor M1 serves as the output end of the first current mirror 162 and is coupled to the input end of the third current mirror 164. Further, the first mirror transistor M1 and the second mirror transistor M2 have the same conduction type and are opposite to the conduction type of the first input transistor N1. For example, the first input transistor N1 is an NMOS transistor, and the first mirror transistor M1 and the second mirror transistor M2 are both PMOS transistors.

[0073] Optionally, the second current mirror 163 includes a third mirror transistor M3 and a fourth mirror transistor M4. The gates of the third mirror transistor M3 and the fourth mirror transistor M4 are both coupled to the drain of the second input transistor N2. The drain of the third mirror transistor M3 is coupled to the source of the second input transistor N2. The drain of the fourth mirror transistor M4 serves as the output end of the second current mirror 163 and is coupled to the output end of the third current mirror 164 and the output end out of the transconductance amplifier OTA. Further, the third mirror transistor M3 and the fourth mirror transistor M4 have the same conduction type and are opposite to the conduction type of the second input transistor N2. For example, the second input transistor N2 is an NMOS transistor, and the third mirror transistor M3 and the fourth mirror transistor M4 are both PMOS transistors.

[0074] Optionally, the third current mirror 164 includes a fifth mirror transistor N3 and a sixth mirror transistor N4. The gates of the fifth mirror transistor N3, the drain of the fifth mirror transistor N3, and the gate of the sixth mirror transistor N4 are coupled to each other, serving as the input terminal of the third current mirror 164, and are coupled to the output terminal of the first current mirror 162. The drain of the sixth mirror transistor N4 serves as the output terminal of the third current mirror 164, and is coupled to the output terminal of the second current mirror 163 and the output terminal out of the transconductance amplifier OTA.

[0075] It should be understood that Figure 6 in [the figure], N1 to N4 are NMOS transistors, and M1 to M4 are PMOS transistors. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, one or more of the above NMOS transistors can be replaced with PMOS transistors, BJT transistors, or triode transistors, etc., and one or more of the above PMOS transistors can be replaced with NMOS transistors, BJT transistors, or triode transistors, etc.

[0076] In addition, each circuit module in the above-mentioned first loop loop1 and second loop loop2 can be integrated together in the spread-spectrum clock generator chip, or at least one circuit module can be disposed outside the spread-spectrum clock generator chip. The present invention does not make specific limitations thereto.

[0077] Taking Figures 1 to 6 the spread-spectrum clock generator composed of the circuit shown as an example, the triangular wave voltage V CTRL_C of the spread-spectrum clock generator in this embodiment is as shown in Figure 8 . The period T of the triangular wave voltage V CTRL_C = a * R2 * C2. By adjusting or trimming the magnitudes of R2 and C2, the modulation frequency fout (whose corresponding fundamental frequency is fcenter) for spreading the spectrum of the output of the ring oscillator 14 can be changed.

[0078] The error current △I generated by the transconductance amplifier OTA = △V CTRL_R * 1 / R2. The triangular wave voltage V CTRL_C formed by this error current △I on the integrating capacitor C2 = [△I(T / 2)] / C2. Substituting T = a * R2C2 and simplifying, we get: △V CTRL_C = a * △V CTRL_R . When the voltage V CTRL_R at the second output terminal of the loop filter 12 generates a change amount △V CTRL_R , the charge pump 11 of the first loop loop1 will charge the loop filter 12 with a charging current ICP, and the result is equal to [(ICP)*(T / 2)] / C1, and ICP = VBG / R. Substituting this into the above formula, we get △V CTRL_R = [VBG / R * (a * R2 * C2 / 2)] / C1. It can be seen that △VCTRL_R The value is proportional to VBG, that is, the coefficient k = a*R2*C2 / (2*C1*R), where R is the resistance value of the first adjustable resistor in the charge pump 11, and R = VBG / ICP.

[0079] Obviously, by adjusting or trimming the ratio of R2 to R and the ratio of C2 to C1, the coefficient k can be made independent of PVT (i.e., process, voltage, temperature), thereby further enabling the modulation depth of the frequency spreading of the ring oscillator 14 to be independent of PVT.

[0080] That is to say, the amplitude △V of the triangular wave voltage V CTRL_C is △V = VBG / k. This coefficient k can be adjusted by trimming the bias current of the transconductance amplifier OTA, and thus a △V that is independent of PVT can be obtained, which is used to change the modulation depth of the output of the ring oscillator 14 for frequency spreading.

[0081] Therefore, before the product (chip or electronic device) leaves the factory, by trimming the three parameters of R2, C2, and the coefficient k, the modulation frequency and modulation depth required for frequency spreading of the output of the ring oscillator can be adjusted.

[0082] Furthermore, please refer to Figure 9 , by adjusting the magnitude of the reference voltage VREF, the frequency spreading mode of the frequency spreading clock generator in this embodiment can be changed. For example, when the reference voltage VREF is adjusted to be equal to a set value (not marked), the frequency spreading clock generator can achieve center frequency spreading; when the reference voltage VREF is adjusted to be lower than the set value, the frequency spreading clock generator can achieve downward frequency spreading; when the reference voltage VREF is adjusted to be higher than the set value, the frequency spreading clock generator can achieve upward frequency spreading.

[0083] In summary, the spread-spectrum clock generator disclosed in the present invention adds a second loop on the basis of a conventional clock generator loop (i.e., the first loop). The second loop adopts a pure analog circuit design and is led out from the second output terminal of the loop filter of the first loop, and can generate a second voltage that controls the output of the ring oscillator to perform spread spectrum for the modulation frequency and modulation depth. The solution is simple and easy to implement. The circuit structure is simple, with a small area, low cost, and low power consumption, and can effectively improve the electromagnetic interference (EMI) problem. Moreover, it can avoid using a sigma-delta modulator, thereby greatly reducing the clock jitter of the output of the first loop, improving reliability, and being very suitable for the application requirements of a spread-spectrum phase-locked loop. In addition, by adjusting or trimming the resistance value of the transconductance amplifier and the capacitance value of the integration capacitor in the second loop, the modulation frequency of the output of the ring oscillator for spread spectrum can be changed, and it does not change with PVT (process, voltage, temperature). At the same time, by adjusting or trimming the bias current of the transconductance amplifier, the corresponding coefficient can be adjusted, and then the modulation depth of the output of the ring oscillator for spread spectrum can be changed, and it also does not change with PVT.

[0084] Based on the same inventive concept, the present invention also provides an electronic device, which includes the spread-spectrum clock generator as described in the present invention. Among them, the specific process of the electronic device generating spread spectrum can refer to the corresponding content of the spread-spectrum clock generator in the above embodiments, and will not be elaborated here.

[0085] The electronic device can be a device, functional module or interface in any suitable application field (such as a high-speed interface adopting standards such as DDR, PCIe or HDMI, such as a register clock driver (RCD) or a data buffer (DB), etc.). These application fields are, for example, the field of system-on-chip (SOC), the field of storage (such as standards such as DDR4, DDR5, LPDDR4, LPDDR5, etc.), the field of communication equipment, the field of portable equipment, and so on. As long as it is a chip or electronic device that requires a high-speed clock, the spread-spectrum clock generator of the present invention can be used to improve the EMI of the high-speed clock signal.

[0086] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the technical solution of the present invention.

Claims

1. A spread-spectrum clock generator, characterized in that, Comprising: A first loop, which includes a loop filter and a ring oscillator, and is configured to generate a first voltage for controlling the oscillation frequency output by the ring oscillator based on the voltage output from the first output terminal of the loop filter; A second loop, coupled to the second output terminal of the loop filter, and configured to generate a second voltage for controlling the modulation frequency and modulation depth of the frequency spread of the output of the ring oscillator based on the voltage output from the second output terminal of the loop filter.

2. The spread spectrum clock generator according to claim 1, wherein The first loop further includes a frequency discriminator and phase detector, a charge pump, a first gain amplifier, and a frequency divider. The frequency discriminator, the charge pump, the loop filter, and the first gain amplifier are sequentially coupled. The first input terminal of the frequency discriminator is coupled to the output terminal of the frequency divider, the second input terminal of the frequency discriminator is coupled to an input clock signal. The first gain amplifier is configured to convert the voltage output from the first output terminal of the loop filter into the first voltage and provide it to the first control terminal of the ring oscillator. The output terminal of the ring oscillator is coupled to the input terminal of the frequency divider and the input terminal of the ring oscillator.

3. The spread spectrum clock generator according to claim 2, wherein The charge pump includes an operational amplifier, a first MOS transistor, a second MOS transistor, and a first adjustable resistor. The first input terminal of the operational amplifier is coupled to a bandgap reference voltage. The second input terminal of the operational amplifier is coupled to the first end of the first adjustable resistor and the drain of the first MOS transistor. The output terminal of the operational amplifier is coupled to the gate of the first MOS transistor and the gate of the second MOS transistor. The second end of the first adjustable resistor is grounded. The drain of the second MOS transistor is coupled to the input terminal of the loop filter to provide a charge and discharge current.

4. The spread spectrum clock generator according to claim 1, wherein, The loop filter includes a filter resistor and a first filter capacitor. The first end of the filter resistor serves as the first output terminal of the loop filter. The second end of the filter resistor serves as the second output terminal of the loop filter and is coupled to one end of the first filter capacitor and the second loop. The other end of the first filter capacitor is grounded.

5. The spread spectrum clock generator according to claim 4, wherein The loop filter is a multi-order filter of two orders or more, and at least further includes a second filter capacitor. One end of the second filter capacitor is coupled to the first end of the filter resistor, and the other end of the second filter capacitor is grounded.

6. The spread spectrum clock generator according to any one of claims 1-5, characterized in that, The second loop includes a triangular wave generator and a second gain amplifier. Among them, the first input terminal of the triangular wave generator is coupled to the second output terminal of the loop filter. The second input terminal of the triangular wave generator is coupled to a corresponding reference voltage. The triangular wave generator is configured to output the voltage output from the second output terminal of the loop filter as a triangular wave voltage. The period of the triangular wave voltage is used to control the modulation frequency of the frequency spread of the output of the ring oscillator, and the amplitude of the triangular wave voltage is used to control the modulation depth of the frequency spread of the output of the ring oscillator. The input terminal of the second gain amplifier is coupled to the output terminal of the triangular wave generator and is configured to convert the triangular wave voltage into the second voltage to provide it to the second control terminal of the ring oscillator.

7. The spread spectrum clock generator according to claim 6, wherein The triangular wave generator includes a transconductance amplifier and an integrating capacitor. The first input terminal of the transconductance amplifier is coupled to the second output terminal of the loop filter. The second input terminal of the transconductance amplifier is coupled to the reference voltage. The transconductance amplifier is configured to convert the difference between the voltage at the second output terminal of the loop filter and the reference voltage into an error current. The integrating capacitor is coupled to the output terminal of the transconductance amplifier and the input terminal of the second gain amplifier, and is configured to integrate the error current to generate the triangular wave voltage.

8. The spread spectrum clock generator according to claim 7, wherein, The error current ΔI = ΔV CTRL_R / R2, the amplitude of the triangular wave voltage ΔV = VBG / k, the period of the triangular wave voltage T = a*R2*C2, where ΔV CTRL_R is the difference between the voltage at the second output terminal of the loop filter and the reference voltage, 1 / R2 is the transconductance value of the transconductance amplifier, C2 is the capacitance value of the integration capacitor, VBG is the bandgap reference voltage, a is a constant, and k is a coefficient.

9. The spread spectrum clock generator according to claim 8, wherein k = a*R2*C2 / (2*C1*R). By adjusting the ratio of R2 to R and the ratio of C2 to C1, the coefficient k is made independent of process, voltage, and temperature, and thus the modulation depth is made independent of the process, voltage, and temperature. Here, R = VBG / ICP, where ICP is the charge and discharge current of the loop filter, and C1 is the capacitance value of the first filter capacitor at the second output terminal of the loop filter.

10. The spread spectrum clock generator according to any one of claims 7-9, characterized in that The transconductance amplifier includes: A differential input circuit, coupled to the reference voltage and the second output terminal of the loop filter, and configured to convert the voltage at the second output terminal of the loop filter into a first current and the reference voltage into a second current; A first current mirror, coupled to the differential input circuit, and configured to mirror-output the first current; A second current mirror, coupled to the differential input circuit and the output terminal of the transconductance amplifier, and configured to mirror-output the second current; A third current mirror, coupled to the first current mirror and the output terminal of the transconductance amplifier, and configured to mirror-output the current output by the first current mirror again, so that the output terminal of the transconductance amplifier outputs the error current.

11. The spread spectrum clock generator according to claim 10, wherein The differential input circuit includes a first input transistor, a second input transistor, and a second adjustable resistor. The gate of the first input transistor is coupled to the second output terminal of the loop filter. The gate of the second input transistor is coupled to the reference voltage. The source of the first input transistor is coupled to one end of the second adjustable resistor. The source of the second input transistor is coupled to the other end of the second adjustable resistor. Here, the second adjustable resistor determines the transconductance value of the transconductance amplifier.

12. The spread spectrum clock generator according to claim 11, wherein, It further includes at least one of the following (1) to (4): (1) The first current mirror includes a first mirror transistor and a second mirror transistor. The gates of the first mirror transistor and the second mirror transistor are both coupled to the drain of the first input transistor. The drain of the second mirror transistor is coupled to the source of the first input transistor. The drain of the first mirror transistor serves as the output terminal of the first current mirror and is coupled to the input terminal of the third current mirror; (2) The second current mirror includes a third mirror transistor and a fourth mirror transistor. The gates of the third mirror transistor and the fourth mirror transistor are both coupled to the drain of the second input transistor. The drain of the third mirror transistor is coupled to the source of the second input transistor. The drain of the fourth mirror transistor serves as the output terminal of the second current mirror and is coupled to the output terminal of the third current mirror and the output terminal of the transconductance amplifier; (3) The third current mirror includes a fifth mirror transistor and a sixth mirror transistor. The gates of the fifth mirror transistor, the drain of the fifth mirror transistor, and the gate of the sixth mirror transistor are mutually coupled as the input terminal of the third current mirror and are coupled to the output terminal of the first current mirror. The drain of the sixth mirror transistor serves as the output terminal of the third current mirror and is coupled to the output terminal of the second current mirror and the output terminal of the transconductance amplifier; (4) The differential input circuit further includes a first current source, a second current source, a third current source, and a fourth current source. One end of the first current source is coupled to the drain of the first input transistor, one end of the second current source is coupled to the source of the first input transistor, one end of the third current source is coupled to the drain of the second input transistor, and one end of the fourth current source is coupled to the source of the second input transistor.

13. The spread spectrum clock generator according to claim 6, wherein Adjusting the magnitude of the reference voltage can change the frequency spreading mode of the frequency spreading clock generator, where: When the adjusted reference voltage is equal to the set value, the frequency spreading clock generator achieves center frequency spreading; When the adjusted reference voltage is lower than the set value, the frequency spreading clock generator achieves downward frequency spreading; When the adjusted reference voltage is higher than the set value, the frequency spreading clock generator achieves upward frequency spreading.

14. An electronic device, characterized in that, It includes the frequency spreading clock generator according to any one of claims 1-13.

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