Hardware latch protection scheme for intelligent measurement terminal

Abstract

The invention discloses a hardware latch protection scheme for an intelligent measurement terminal, and the scheme comprises a hardware latch protection circuit taking an inverter as a main part, and the hardware latch protection circuit is used for carrying out the reverse output of an input signal, and forming a reset signal; a reset pulse signal DOGRST output by the hardware latch protection circuit is used for resetting the terminal, and the reset signal can control the core board to reset, so that the terminal is restarted; the anti-reset signal WDT output by the core board is used for anti-reset operation and protecting normal operation of the circuit. The problem that the intelligent measurement terminal cannot be restarted when system errors occur is solved, and resetting and restarting of the terminal are achieved through voltage changes of the phase inverter.

Description

Technical Field

[0001] The present invention relates to the technical field of distribution network automation, and particularly to a hardware latch protection solution for an intelligent measurement terminal. Background Art

[0002] With the development of the power system, intelligent measurement terminals have become an indispensable and important part of the power system. It can monitor parameters such as power quality, current and voltage in the power system in real time, providing important support for the safe operation of the power system. The single-chip microcomputer in the intelligent measurement terminal is the core component of the terminal, responsible for key tasks such as data acquisition, processing and transmission. However, due to the relatively harsh working environment of the intelligent measurement terminal, there are various forms of interference around it, and the single-chip microcomputer often suffers from interference from external electromagnetic fields, resulting in the program running wild and falling into an infinite loop. Once the normal operation of the program is interrupted, the system controlled by the single-chip microcomputer will not be able to continue working, resulting in the entire intelligent measurement terminal stopping operation and causing a large amount of property losses, and even causing serious consequences. For example, in the power system, the data acquisition and transmission of the intelligent measurement terminal are crucial for the safe operation of the power system. Once the terminal fails, it may lead to faults and accidents in the power system, having a serious impact on the stable operation of the power system. In order to ensure the stable operation of the intelligent terminal and reduce the risk brought by the program infinite loop, it is very necessary to carry out hardware latch protection for the intelligent measurement terminal. Summary of the Invention

[0003] Aiming at the deficiencies and defects existing in the prior art, the present invention provides a hardware latch protection solution for an intelligent measurement terminal, solves the problem that there is no hardware latch protection solution for the intelligent measurement terminal currently, and realizes the hardware protection for the intelligent measurement terminal.

[0004] The object of the present invention can be achieved by the following technical solutions:

[0005] A hardware latch protection solution for an intelligent measurement terminal includes a hardware latch protection circuit mainly composed of an inverter, a reset pulse signal DOG_RST output by the hardware latch protection circuit, and an anti-reset signal WDT output by the core board. The hardware latch protection circuit mainly composed of an inverter includes components such as an inverter, a resistor, a capacitor, and a triode.

[0006] A hardware latch protection solution for an intelligent measurement terminal includes the following steps:

[0007] Step 1: After the terminal is powered on, the output of the inverter in the hardware latch protection circuit remains high. At this time, DOG_RST charges the input terminal of the inverter. The capacitor C4 beside DOG_RST plays a role in filtering and voltage stabilization to ensure the stability of the input voltage. When the voltage at the input terminal of the inverter is greater than the set value, the inverter works, converting the high level at the input terminal to a low level at the output terminal. The inverter starts to output a low-level signal, causing the hardware latch protection scheme circuit to output a reset signal.

[0008] Step 2: To prevent reset situations, when the input voltage of the inverter reaches a certain value, the core board outputs an anti-reset signal WDT. When WDT is a high-level signal, the capacitor C1 in the circuit keeps the voltage from changing suddenly. The voltage on the right side rises, causing the triode in the hardware latch protection circuit to conduct. The voltage accumulated at the input terminal of the original inverter is released through the triode, resulting in a decrease in the voltage at the input terminal of the inverter, which cannot reach the requirement for high-level inversion output. At this time, the output terminal of the inverter still remains high, and the hardware latch protection circuit does not send a reset signal, ensuring the normal operation of the system. When WDT is a low-level signal, DOG_RST continues to provide voltage to the input terminal of the inverter, causing the voltage at the input terminal of the inverter to continuously rise. Before it reaches a high level, the WDT signal first changes to a high level, releasing the voltage accumulated at the input terminal of the inverter, forming an effective hardware latch protection cycle.

[0009] Step 3: Before the input terminal of the inverter in the hardware latch protection circuit mainly composed of the inverter is charged to a certain voltage, the output remains high. When the high level at the output terminal changes to a low level, there is a hysteresis interval in the middle. The output terminal will not change back to a high level until the input voltage drops to a certain value. By increasing the hysteresis interval, voltage mutations can be prevented, and at the same time, sufficient restart time is reserved.

[0010] Step 4: The reset pulse signal DOG_RST output by the hardware latch protection circuit. The DOG_RST terminal is usually in a high-level state, providing voltage to the input terminal of the inverter. Only when the inverter outputs a low level will it output a reset signal to the core board to restart the terminal. The anti-reset signal WDT output by the core board. The reset signal WDT is a square wave signal with a duty cycle of 50%. When the reset signal is at a high level, the triode conducts for a short time, pulling down the voltage at the input terminal of the inverter to prevent the inverter from outputting a low level. When the reset signal is at a low level, the triode closes, and a continuous voltage is input at DOG_RST, and the voltage at the input terminal of the inverter continuously accumulates and rises.

[0011] Advantageous technical effects of the present invention: Aiming at the problem of insufficient protection targeting of current intelligent measurement terminals, a hardware latch protection solution for intelligent measurement terminals is provided, which solves the problem that the intelligent measurement terminal is interfered by external electromagnetic fields, resulting in the program running wild and falling into an infinite loop, ensures the stability of the intelligent terminal, and reduces the risk brought by the program infinite loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is the overall circuit schematic diagram of the present invention. Figure 2 is the working principle diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not limit the present invention.

[0014] As Figure 1 shown, a hardware latch protection solution for an intelligent measurement terminal includes components such as an inverter, a resistor, a capacitor, and a triode inside. After the terminal is powered on, the output of the inverter in the hardware latch protection circuit remains high. At this time, DOG_RST charges the input terminal of the inverter, and the capacitor C4 beside DOG_RST plays a role in filtering and voltage stabilization to ensure the stability of the input voltage. When the voltage at the input terminal of the inverter is greater than the set value, the inverter works, converting the high level at the input terminal into a low level at the output terminal. The inverter starts to output a low-level signal, resulting in the hardware latch protection solution circuit outputting a reset signal.

[0015] To prevent the reset situation from occurring, when the input voltage of the inverter reaches a certain value, the core board outputs an anti-reset signal WDT. When WDT is a high-level signal, the capacitor C1 in the circuit keeps the voltage from changing suddenly, the voltage on the right side rises, and the triode in the hardware latch protection circuit conducts. The voltage accumulated at the input terminal of the original inverter is released through the triode, resulting in the voltage at the input terminal of the inverter decreasing and unable to meet the high-level inversion output requirement. At this time, the output terminal of the inverter still remains high, and the hardware latch protection circuit does not issue a reset signal, ensuring the normal operation of the system. When WDT is a low-level signal, DOG_RST continues to provide voltage to the input terminal of the inverter, causing the voltage at the input terminal of the inverter to continuously rise. Before it reaches the high level, the WDT signal first turns into a high level, releasing the voltage accumulated at the input terminal of the inverter, forming an effective hardware latch protection cycle.

[0016] Before the input end of the inverter in the hardware latch protection circuit mainly composed of inverters is charged to a certain voltage, the output is always high. When the high level at the output end becomes low, there is a hysteresis interval in the middle, and it is necessary for the input voltage to drop to a certain value before the output end will become high again. By increasing the hysteresis interval, voltage mutations can be prevented, and at the same time, sufficient restart time is retained.

[0017] The reset pulse signal DOG_RST output by the hardware latch protection circuit is usually in a high level state, providing voltage for the input end of the inverter. Only when the output of the inverter is low will it output a reset signal to the core board to restart the terminal. The anti-reset signal WDT output by the core board, the reset signal WDT is a square wave signal with a duty cycle of 50%. When the reset signal is high, the triode conducts for a short time, pulling down the voltage at the input end of the inverter to prevent the inverter from outputting a low level. When the reset signal is low, the triode closes, and a continuous voltage is input at DOG_RST, and the voltage at the input end of the inverter accumulates and rises continuously.

[0018] The present invention is more targeted at intelligent measurement terminals. At the same time, the software program is simpler, the requirements for hardware are low, the price is low, the cost is low, and it is easy to implement.

[0019] The above embodiments are illustrative of the specific implementation manners of the present invention, rather than limitations on the present invention. Those skilled in the relevant technical fields can make various transformations and changes without departing from the spirit and scope of the present invention to obtain corresponding equivalent technical solutions. Therefore, all equivalent technical solutions should be included in the patent protection scope of the present invention.

Claims

1. A hardware latch protection solution for an intelligent measurement terminal, characterized in that, It includes a hardware latch protection circuit mainly composed of an inverter, a reset pulse signal DOG_RST output by the hardware latch protection circuit, and an anti-reset signal WDT output by the core board.

2. The hardware latch protection scheme for an intelligent measurement terminal according to claim 1, wherein The hardware latch protection circuit mainly composed of an inverter. Inside the hardware latch protection circuit mainly composed of an inverter, there are an inverter, a resistor, and a capacitor. The output position of the inverter in the hardware latch protection circuit remains high after the terminal is powered on. At the same time, DOG_RST charges the input terminal. When the voltage at the input terminal is greater than the set value, the inverter works and outputs a low level, resulting in the hardware latch protection scheme circuit outputting a reset signal.

3. A hardware latch protection solution for an intelligent measurement terminal according to claim 1, characterized in that, To prevent reset situations, when the input voltage of the inverter reaches a certain value, the core board inputs an anti-reset signal. At this time, the triode in the hardware latch protection circuit conducts, resulting in the voltage at the input terminal of the inverter decreasing and unable to meet the requirements of inverting output. The output terminal remains high level, and the hardware latch protection circuit does not issue a reset signal to ensure the normal operation of the system; before the input terminal of the inverter is charged to a certain voltage, the output is always high level. When the high level at the output terminal changes to low level and then changes back to high level again, there is a hysteresis interval in the middle. The input terminal voltage needs to drop to a certain voltage before it will change back to high level again to prevent voltage mutations and at the same time retain sufficient restart time.

4. A hardware latch protection solution for an intelligent measurement terminal according to claim 1, characterized in that, The reset pulse signal DOG_RST output by the hardware latch protection circuit. The DOG_RST terminal is usually in a high level state, providing voltage for the input terminal of the inverter. Only when the inverter outputs a low level will it output a reset signal to the core board to restart the terminal.

5. A hardware latch protection scheme for an intelligent measurement terminal according to claim 1, characterized in that, The anti-reset signal output by the core board. The reset signal is a square wave signal with a duty cycle of 50%. When the reset signal is at a high level, the triode conducts for a short time, pulling down the voltage at the input terminal of the inverter to prevent the inverter from outputting a low level.

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