Complex switch control circuit based on domestic FPGA and control method thereof

Abstract

The invention discloses a domestic FPGA-based complex switch control circuit and method, and the circuit comprises an FPGA minimum system circuit and a peripheral serial-parallel conversion circuit, and the FPGA minimum system circuit is connected with the peripheral serial-parallel conversion circuit. Through complex combinational logic of the multi-channel switch, control can be conveniently carried out, use of devices is reduced, the design cost of the switch is saved, due to the fact that the multi-channel switch is a domestic device, the readability of a manual is high, the function implementation difficulty can be reduced, meanwhile, the multi-channel switch has the advantages of being convenient to operate and high in response speed, and the working efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA switch circuit control, and particularly to a complex switch control circuit based on domestic FPGA and its control method. Background Art

[0002] For traditional switch control of high and low levels, various NAND gates and combinations such as a 3 - 8 decoder are required to generate the 0 or 3.3V needed for the switch to achieve on - off control. For this type, there are also 1 - of - 3 switches, 1 - of - 4 switches, and N - of - 1 switches, which require more levels and thus more combinations. This is not only complex but also difficult to operate and design, increasing the design cost and time. In many cases, there will be conflicts in the switches. For example, different channels require the same switch to be enabled, which involves a priority issue.

[0003] In view of the above problems, the present invention provides a complex switch control circuit based on domestic FPGA with a simplified circuit design and its control method. Summary of the Invention

[0004] The object of the present invention is to provide a complex switch control circuit based on domestic FPGA with a simplified circuit design and its control method.

[0005] The present invention provides a complex switch control circuit based on domestic FPGA, including an FPGA minimum system circuit and a peripheral serial - parallel conversion circuit, and the FPGA minimum system circuit is connected to the peripheral serial - parallel conversion circuit.

[0006] Furthermore, the FPGA minimum system circuit includes a Flash configuration chip and an FPGA chip, and the configuration bank pins of the FPGA chip are connected to the communication pins of the Flash configuration chip.

[0007] Furthermore, the peripheral serial - parallel conversion circuit includes a buffer chip circuit and a dual - path NOT gate circuit, and the output of the buffer chip circuit is connected to the input of the dual - path NOT gate circuit.

[0008] The present invention also provides a complex switch control method based on domestic FPGA, which specifically includes the following steps:

[0009] Step 1: Prepare an FPGA control board. The FPGA makes each pin output a voltage of 3.3V for controlling the switch, and the usage modes include independent use and embedded use;

[0010] Step 2: Use software to map the corresponding input pins of the FPGA and the product. When used independently, a USB - to - serial chip is required, while it is not required for embedded use;

[0011] Step 3: Group all the switches in the product. Group the switches corresponding to each channel, number the groups in the program as the corresponding quantity, write down all input situations one by one, then perform permutations and combinations on the switches corresponding to each situation, write down the required switch combinations for each different input situation, ensure that when the input is different each time, the switches will change accordingly, then map the outputs of all switch chips in each group to the output pins of the FPGA for output, measure with a multimeter at the corresponding switch positions of the product to see if there is a transition between 3.3V and 0V to confirm whether the control is correct. When two channels use the same switch, the priority settings of the IO ports can be carried out.

[0012] The present invention has the following advantages: The streamlined circuit design of the present invention eliminates unnecessary logic conversion devices, reduces the workload and brings convenience to the layout. Supply 3.3V power to the FPGA. Only need to connect the controlled switch pins to the FPGA, add a protection resistor or a pull-down resistor, and combined with software, it can freely control any switch to output 0 or 3.3V for switch control without having to consider how to design the circuit combination by oneself, which is very convenient. It can also take into account the use of the priority of repeated switches, and at the same time, the response speed is very fast, which can reach the nanosecond level. Conventional ones have one or two hundred pins. This circuit also uses domestic FPGA, which is cheap and easy to operate. Brief Description of the Drawings

[0013] Figure 1 is the principle block diagram of the present invention;

[0014] Figure 2 is the circuit diagram of the minimum system of the FPGA of the present invention;

[0015] Figure 3 is the circuit diagram of the peripheral serial-parallel conversion of the present invention. Detailed Embodiment

[0016] The present invention provides a complex switch control circuit based on domestic FPGA, including an FPGA minimum system circuit and a peripheral serial-parallel conversion circuit, and the FPGA minimum system circuit is connected to the peripheral serial-parallel conversion circuit.

[0017] In this embodiment, the FPGA minimum system circuit includes a Flash configuration chip and an FPGA chip, and the configuration bank pins of the FPGA chip are connected to the communication pins of the Flash configuration chip.

[0018] In this embodiment, the peripheral serial-parallel conversion circuit includes a buffer chip circuit and a dual-channel NOT gate circuit, and the output of the buffer chip circuit is connected to the input of the dual-channel NOT gate circuit. The present invention also provides a complex switch control method based on domestic FPGA. The specific steps of the method are as follows:

[0019] Step 1: Prepare an FPGA control board. The FPGA makes each pin output a voltage of 3.3V to control the switch, and the usage methods include independent use and embedded use;

[0020] Step 2: Use software to map the input pins corresponding to the FPGA and the product. When used independently, a USB-to-serial chip is required, while it is not required for embedded use;

[0021] Step 3: Group all the switches in the product, group the switches corresponding to each channel, number the groups in the program as the corresponding quantity, write down all the input situations one by one, then perform permutations and combinations on the switches corresponding to each situation, write the required switch combinations for each different input situation, ensure that the switches change along with each different input, then output the output pins corresponding to the mapping of all the switch chips in each group to the FPGA, and use a multimeter to measure the corresponding switch positions of the product to see if there is a change between 3.3V and 0V to confirm whether the control is correct. When the same switch is used for two channels, the priority of the IO ports can be set.

[0022] Although the specific implementation modes of the present invention have been described in detail with reference to the accompanying drawings, it should not be construed as a limitation to the protection scope of the present invention. Within the scope described in the claims, various modifications and deformations that can be made by those skilled in the art without creative efforts still fall within the protection scope of this patent.

Claims

1. A complex switch control circuit based on domestic FPGA, including an FPGA minimum system circuit and a peripheral serial-parallel conversion circuit, characterized in that: The minimum system circuit of the FPGA is connected to the peripheral serial-parallel conversion circuit.

2. The complex switch control circuit based on domestic FPGA as described in claim 1, wherein: The minimum system circuit of the FPGA includes a Flash configuration chip and an FPGA chip, and the configuration bank pins of the FPGA chip are connected to the communication pins of the Flash configuration chip.

3. The complex switch control circuit based on domestic FPGA according to claim 1, characterized in that: The peripheral serial-parallel conversion circuit includes a buffer chip circuit and a dual-channel NOT gate circuit, and the output of the buffer chip circuit is connected to the input of the dual-channel NOT gate circuit.

4. A complex switch control method based on domestic FPGA, characterized in that: The specific steps of the method are as follows: Step 1: Prepare a control board of the FPGA. The FPGA makes each pin output a voltage of 3.3V to control the switch. Step 2: Use software to map the corresponding input pins of the FPGA and the product. When used independently, a USB-to-serial chip needs to be added, and it is not required when used embedded. Step 3: Group all the switches in the product, group the switches corresponding to each channel, number the groups as the corresponding quantity in the program, write down all the input situations one by one, then perform permutations and combinations on the switches corresponding to each situation, write the required switch combinations for each different input situation, ensure that the switches change together when each input is different, then map the outputs of all the switch chips in each group to the output pins of the FPGA for output, measure with a multimeter at the corresponding switch positions of the product to see if there is a change between 3.3V and 0V to confirm whether the control is correct. When two channels use the same switch, the priority of the IO ports can be set.

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