Multi-channel acquisition module, system and method based on trigger synchronization automatic calibration

Abstract

The invention relates to a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration, and belongs to the field of electronic measurement, the acquisition module comprises a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronous calibration circuit; the method has the advantages that the multi-channel synchronization precision is high, convenient channel expansion is supported, pairwise interconnection delay calibration can be carried out between modules in parallel, the system calibration time does not increase linearly along with the increase of the number of the channels, the interconnection relation is realized through annular connection, and a large fan-out cable is not needed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic measurement, and particularly relates to a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration. Background Art

[0002] In existing multi-channel acquisition systems, especially in ultra-high-channel parallel acquisition systems composed of multiple devices, there are inevitable delay differences in the transmission of trigger signals between modules, resulting in synchronization errors. Traditional calibration methods rely on external high-precision signal sources to form a star network through power dividers and other fan-out devices for trigger calibration, which is costly and has poor scalability, and has the following defects: 1. Limited synchronization accuracy: The trigger method used for sampling is usually digital trigger, which is limited by the data rate of ordinary FPGA IOs, and the accuracy is usually at the ns level; 2. Insufficient scalability: Increasing the acquisition channels requires adding calibration signal input connections, and it is difficult to dynamically adjust the delay parameters; it is difficult to implement in ultra-high-channel systems. For example, when 128-channel synchronous acquisition is performed, a tree-structured calibration signal connection is required when building the calibration network, and then the measured signal needs to be reconnected through cables after calibration, and the switching operation is complex; 3. Poor real-time performance: Multi-channel synchronization depends on the synchronization processing algorithm after the software obtains the acquisition data, and cannot meet the real-time acquisition requirements. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art, and provides a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration, which solves the deficiencies existing in the prior art.

[0004] The purpose of the present invention is achieved by the following technical solutions: A multi-channel acquisition module based on trigger synchronization automatic calibration, the acquisition module includes a channel conditioning and acquisition circuit, a trigger and input / output feedback circuit, a clock synchronization and calibration signal generation circuit, and an FPGA reception and synchronization calibration circuit; The channel conditioning and acquisition circuit: is configured to condition the measured signal through gain adjustment, AC / DC coupling control, and bandwidth limitation, so that the signal meets the ADC sampling requirements; The trigger and input / output feedback circuit: is configured to realize the input and trigger of the external trigger signal, as well as the transmission and feedback of the trigger signal, and realize the trigger delay measurement between multiple channels; The clock synchronization and calibration signal generation circuit: is configured to generate a sampling clock, input and output a reference clock when multiple acquisition modules are cascaded, and generate a synchronization calibration signal for a single acquisition module; The FPGA receiving and synchronization calibration circuit: is configured to receive the digital quantization signals sampled by each ADC, generate corresponding sampling data streams after protocol parsing, and perform edge synchronization reading and writing through phase adjustment and edge alignment FIFO processing in the calibration mode, so that the sampling data of each channel realizes end-to-end alignment of the delay from the input interface to the data processing end inside the FPGA.

[0005] The channel conditioning and acquisition circuit includes multiple acquisition channels. Each acquisition channel includes two input sources, namely an external signal under test input and an internally integrated calibration signal, which are selected by a first analog switch. When performing trigger synchronization calibration, the first analog switch selects the calibration signal as the input, and selects the signal under test as the input after the calibration trigger synchronization is completed; The selected signal is output to the ADC for acquisition after impedance adjustment, coupling, dynamic range adjustment, and offset adjustment. The data acquired by the ADC is input to the FPGA receiving and synchronization calibration circuit; When each acquisition channel ADC is working, the conversion delay from the analog signal to the digital signal is fixed, and the sampling clock references of all ADCs are consistent.

[0006] The trigger and input / output feedback circuit includes 5 signal input / output interfaces, namely trigger signal EXT input, main trigger input, main feedback output, slave trigger output, and slave feedback input; The trigger signal EXT of the upper-level acquisition module is selected by a second analog switch to control the synchronization trigger of this acquisition module; when performing the synchronization trigger of multiple acquisition modules, the third analog switch of this acquisition module is controlled to select the main trigger input as the trigger signal of this acquisition module for the synchronous acquisition of multiple acquisition modules; during trigger calibration, this acquisition module uses the main trigger input signal sent by the upper-level acquisition module for triggering, and after signal fan-out of this signal, it is sent back to the upper-level acquisition module through the main feedback output interface for trigger link delay measurement; This acquisition module outputs the trigger signal used through the slave trigger output interface to the next-level acquisition module as the main trigger input of the next-level acquisition module; during trigger calibration, this acquisition module receives the trigger signal fed back by the next-level acquisition module through the slave feedback input interface for trigger delay measurement from this acquisition module to the next-level acquisition module.

[0007] The clock synchronization and calibration signal generation circuit generates the clock reference signal required by the integrated phase-locked loop through a local crystal oscillator, and inputs it into the integrated phase-locked loop together with the externally provided clock reference signal, and the integrated phase-locked loop selects the reference clock; When multiple acquisition modules are interconnected for multi-channel parallel sampling, the multiple acquisition modules use a phase-coherent and same-frequency reference clock, and the reference clock is cascaded through the interfaces of the reference clock input and the reference clock output. The clock reference output of the previous-level acquisition module is connected to this acquisition module as the reference clock input of this acquisition module. After completing the common reference, the sampling clocks of the multiple acquisition modules reach the state of being same-frequency and phase-coherent, that is, high-precision multi-channel synchronous acquisition can be performed; an integrated phase-locked loop generates the required main acquisition clock, and through the integrated phase-locked loop, a divided calibration signal of 10 MHz and a reference clock signal of 10 MHz output to the next-level acquisition module are generated; The generated calibration signal is fan-out to multiple acquisition channels through a clock fan-out device, and at the same time, the interference of jitter on the phase of the calibration signal is reduced. The generated calibration signal is respectively connected to each analog channel and the external trigger channel in the acquisition module, and the consistency of the signal delay received by each channel is controlled by equal-length routing.

[0008] The FPGA receives the signal input by the trigger channel through the synchronization calibration circuit, and performs digital non-encoded sampling above Gsps through the SerDes interface, improving the sampling rate of the trigger signal, and further improving the time accuracy of the trigger signal to the ps level. The sampled data of the trigger signal also makes the trigger signal and the data of each acquisition channel achieve end-to-end alignment of the delay from the input interface end to the data processing end through the edge synchronization read and write method; After completing the precise delay calibration, the data of all acquisition channels and the trigger channel have achieved the delay alignment from the input interface to the data processing interface. Using any one of the signals as a trigger can achieve high-precision trigger synchronization of all parallel channels within a single acquisition module.

[0009] A multi-channel acquisition system based on trigger synchronization and automatic calibration, the system includes multiple acquisition modules; when the multiple acquisition modules are interconnected, the previous-level acquisition module outputs a clk_out signal to the next-level acquisition module, and after locking the clock phase reference in the next-level acquisition module, a clock reference signal is output to the next-next-level acquisition module for reference, thereby realizing the sampling time synchronization of the multiple acquisition modules.

[0010] A multi-channel acquisition method based on trigger synchronization and automatic calibration, the acquisition method includes: S1. Input the calibration signal into each analog channel and the trigger channel, respectively perform conditioning and digital quantization, and after being received by the FPGA receiving and synchronization calibration circuit, obtain the digital quantization signals of each path inside the FPGA; S2. Pass the same calibration signal through different acquisition links to obtain different delay quantization results. After clock domain conversion through an asynchronous FIFO, perform delay calibration at the edge moment, control the buffer reading and writing of each channel, correct the delay deviation of each channel, and obtain the data synchronously acquired by all channels; S3. Fan out the trigger signal of the upper-level acquisition module to the lower-level acquisition module, and then return it from the lower-level acquisition module to the upper-level acquisition module for line delay measurement, obtain the round-trip delay of the trigger signal transmission between the two acquisition modules, thereby calculate the absolute time delay between the trigger signal obtained by the lower-level acquisition module and the true trigger moment, and then correct the trigger moment calculation method of the lower-level acquisition module to achieve precise synchronization of the triggers of the two acquisition modules; S4. When any analog channel or trigger channel in any acquisition module in the entire system networking is selected as the system trigger channel, according to the trigger path transmission relationship, sequentially accumulate and issue the trigger delays of the subsequent acquisition modules, and then control the precise synchronization of the triggers of all channels of all acquisition modules to obtain the result of precise alignment of parallel acquisition of all channels. The specific content of S2 is as follows: S21. Each acquisition channel analyzes the quantization data according to the quantization protocol of the corresponding ADC, and writes the corresponding data and the associated clock into the write port of the internal asynchronous FIFO of the FPGA. At the read port of the FIFO, use the main clock inside the FPGA to generate a read signal to synchronize the acquisition data in different clock domains to the same data processing clock domain; S22. Process the generated quantization data in parallel to obtain parallel multi-channel data, split the parallel multi-channel data to obtain multiple groups of data, find the corresponding edge positions within each group, set a 16-bit register, and each bit represents whether the corresponding sequence meets the structure of the digital Schmitt comparator. When looking for the rising edge, set the upper and lower thresholds of the comparison level, and according to the relationship between the data and the upper and lower thresholds, output the corresponding results according to the set conditions. After obtaining the parallel multi-group comparison result registers of each channel, look for whether there is an edge judgment from 0 to 1 within each group according to the priority of the data points. If so, output the rising edge pos_edge_vld as 1, otherwise output 0, and output the corresponding bit index number pos_edge_idx; S23. Since the delays of different links are different, resulting in different beats at which the edges appear and the corresponding pos_edge_idx, therefore adjust the pos_edge_idx to be the same, use pos_edge_idx as the search condition, perform data shift adjustment according to different values, and after adjustment, adjust the data edges of each link to the first sampling point under the main clock; S24. After reset, according to the input pos_edge_vld signal, enable the write enable of each FIFO. After determining that each FIFO reaches a certain threshold, synchronously enable the read enable of each FIFO to obtain a signal with consistent edges after synchronization.

[0011] The specific content of S3 is as follows: S31. In each acquisition module, use the built-in calibration signal, and use the SerDes interface of the FPGA to quantize the calibration trigger signal. The quantized signal undergoes protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge bit sequence shift, and edge beat alignment to obtain the quantized data with aligned trigger delays in each acquisition module. S32. The upper-level acquisition module sends the calibration signal to the lower-level acquisition module as an input signal. The lower-level acquisition module copies the calibration signal through fan-out and feeds it back to the upper-level acquisition module. The two SerDes of the upper-level acquisition module respectively quantize the calibration signal and the feedback signal. After quantization by the two SerDes, the delay of the quantized edge is the round-trip delay of the trigger lines of the two acquisition modules. The transmission delay consists of the circuit delays of the two acquisition modules and the round-trip delay of the cable. Since the circuit delay is controlled by making the trigger output and feedback input have equal-length traces during circuit design, and the round-trip cable is a pair of equal-length wires, the delay is considered symmetric. Therefore, dividing the total delay value Cal_dly of the calibration signal by 2 can obtain the trigger signal transfer delay Trig_pdly between the two acquisition modules. S33. Record the obtained trigger signal transfer delay Trig_pdly through a register. After being read by the control software, it is sent to the lower-level acquisition module to correct the trigger position in the lower-level acquisition module. Since the trigger signal received by the lower-level acquisition module from the upper-level acquisition module has a delay of Trig_pdly, after the lower-level acquisition module completes triggering and waveform capture, advance the trigger point and correct the time value of Trig_pdly to obtain the real starting point. And the pre-trigger depth and post-trigger depth corresponding to the lower-level acquisition module are adjusted by Trig_pdly to adapt to the sampling delay caused by trigger transmission.

[0012] The acquisition method further includes: when channel expansion is required, select to add an acquisition module between any two acquisition modules in the entire system, and perform calibration on the delay between the new acquisition module and the upper and lower acquisition modules. After the new acquisition module and the upper and lower acquisition modules complete trigger delay calibration, update the system delay setting to enable the use of the expanded acquisition system. The acquisition method further includes system accuracy testing, and the system accuracy testing includes: using two signals with a synchronous phase relationship as the input signals of the entire multi-channel, inputting these two signal ends into any two channels of the calibrated multi-channel acquisition system, selecting one of the two channels as the trigger channel, observing the waveform display result of the acquired data, and judging whether synchronous trigger acquisition is performed between the two channels through the cursor measurement function.

[0013] The present invention has the following advantages: a multi-channel acquisition module, system and method based on trigger synchronization and automatic calibration, with high multi-channel synchronization accuracy, supporting convenient channel expansion, capable of parallel pairwise interconnection delay calibration between modules, the system calibration time does not increase linearly with the increase of the number of channels, and the interconnection relationship can use a ring connection without large fan-out cables. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic structural diagram of a single multi-channel acquisition module of the present invention; Figure 2 is a schematic diagram of a clock synchronization and calibration signal generation circuit; Figure 3 is a schematic diagram of a channel conditioning and acquisition circuit; Figure 4 is a schematic diagram of a trigger and input / output feedback circuit; Figure 5 is a schematic diagram of an FPGA reception and synchronization calibration circuit; Figure 6 is a schematic diagram of the connection composition of multiple multi-channel acquisition modules of the present invention; Figure 7 is a schematic diagram of edge bit sequence shifting; Figure 8 is a schematic diagram of master-slave acquisition module trigger delay correction. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below with reference to the accompanying drawings is not intended to limit the protection scope of the present application claimed, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the protection scope of the present application. The present invention will be further described below with reference to the accompanying drawings.

[0016] As shown Figure 1 In one embodiment of the present invention, a multi-channel acquisition module based on trigger synchronization automatic calibration is provided, which includes a channel conditioning and acquisition circuit, a trigger and input / output feedback circuit, a clock synchronization and calibration signal generation circuit, and an FPGA reception and synchronization calibration circuit.

[0017] Furthermore, as shown Figure 2 In the clock synchronization and calibration signal generation circuit, the generation of the sampling clock is realized, as well as the reference clock input / output function during multi-module cascading. By adding a signal fan-out circuit, the generation of the synchronization calibration signal for a single module is realized.

[0018] The local crystal oscillator generates the clock reference signal required by the integrated phase-locked loop. Together with the externally provided clock reference signal, they are input into the integrated phase-locked loop, and the integrated phase-locked loop selects the reference clock. The local crystal oscillator selects a temperature-controlled crystal oscillator with an initial accuracy of the reference temperature of ≤±0.3ppm.

[0019] When multiple acquisition modules are interconnected for multi-channel parallel sampling, multiple acquisition modules need to use a co-phased and same-frequency reference clock. At this time, the reference clock can be cascaded through the reference clock input / output interface. Connect the clock reference output of the upper-level module to this module as the reference clock input of this module. After completing the common reference, the sampling clocks of multiple acquisition modules reach the state of being the same frequency and co-phased, and high-precision multi-channel synchronous acquisition can be performed. Use the integrated phase-locked loop to generate the required system acquisition main clock, and use the phase-locked loop to generate the divided calibration signal of 10MHz and the reference clock signal of 10MHz output to the subsequent stage.

[0020] The generated calibration signal is fan-out to multiple acquisition channels through a clock fan-out device. A low-jitter fan-out device is used to reduce the interference of jitter on the phase of the calibration signal. Connect the generated calibration signal to the analog channels (CH1~CH4) and the external trigger channel (EXT) of a single acquisition module respectively. By making the traces of equal length, the signal delay consistency received by each channel is controlled. Using a low-jitter fan-out device to generate the multi-channel synchronous calibration signal can effectively ensure that the calibration source has excellent synchronization performance and improve the synchronization accuracy of the system.

[0021] Furthermore, as shown Figure 3 In the channel conditioning and acquisition circuit, the function realized is to condition the measured signal (external input or internal calibration signal) through circuits such as gain adjustment, AC / DC coupling control, and bandwidth limitation, so that the external signal meets the requirements of ADC sampling.

[0022] Each acquisition channel has two input sources, namely the external signal under test (such as CH1) and the internally integrated calibration signal (calibration signal fan-out 1). The selection is made through a 2:1 analog switch, and the analog switch used is implemented with a high-bandwidth signal relay to ensure that the signal bandwidth of the circuit is not affected by the inserted switch. When performing trigger synchronization calibration, the internal calibration signal is selected as the input; after the calibration trigger synchronization is completed, the signal under test is selected as the input.

[0023] The selected signal is output to the ADC for acquisition after passing through the corresponding conditioning circuits such as impedance adjustment, coupling, dynamic range adjustment, and offset adjustment of the acquisition system.

[0024] The ADC used for acquiring signals supports multiple interfaces and synchronization methods, such as common LVDS parallel output, JESD protocol output, serial output with synchronization frames, etc. In the invention solution, it is only necessary that when the ADC of each acquisition channel works, the conversion delay from the analog signal to the digital signal is fixed, and the sampling clock references of all ADCs are consistent. The data acquired by the ADC is sent to the FPGA for subsequent alignment operations and processing. The period of the calibration signal used is greater than the maximum transmission conversion period in all acquisition links, which can ensure that after the alignment processing of all acquisition links by the FPGA, the delay is compensated in reverse to be consistent.

[0025] Furthermore, as Figure 4 shown, the trigger and input / output feedback circuit realizes the input and trigger function of the external trigger signal, and realizes the transmission and feedback of the trigger signal, and realizes the trigger delay measurement between multiple channels. This circuit contains 5 signal input / output interfaces, among which the external trigger interface (EXT) is implemented with a conventional interface (such as BNC), and the remaining master trigger input, slave feedback output, slave trigger output, and slave feedback input are dedicated lines for multi-channel synchronization, and are interconnected using high-density integrated cables to reduce the space occupied by the connectors. Since the signals of this part of the circuit are all transmitted using analog signals, it has the characteristic of ultra-low jitter, which can make the trigger synchronization signal have a high precision at the ps level.

[0026] The trigger signal EXT of the upper-level master acquisition module is selected through an analog switch to control the synchronization trigger of this acquisition module; when performing the synchronization trigger of multiple acquisition modules, the switch of the slave acquisition module is controlled to select the master trigger input signal as the trigger signal of this acquisition module for synchronous acquisition. During trigger calibration, this acquisition module uses the master trigger input signal sent from the upper level for triggering. After this signal is fan-out, it is sent back to the upper level through the master feedback output interface for trigger link delay measurement.

[0027] This acquisition module outputs the trigger signal it uses to the next-level slave acquisition module as the main trigger input of the next-level slave acquisition module; during trigger calibration, this acquisition module receives the trigger signal fed back by the next-level slave acquisition module to measure the trigger delay from this acquisition module to the next-level slave acquisition module.

[0028] Further, as Figure 5 shown, the FPGA in the reception and synchronization calibration circuit receives the digital quantization signals sampled by each ADC through analog reception, and after protocol parsing, generates corresponding sampled data streams. Depending on the transmission protocol, there will be corresponding clock signals on the same path.

[0029] In the calibration mode, the asynchronous cache phase modulation module writes the received acquisition signals into an asynchronous FIFO (First In First Out queue). After phase adjustment and edge alignment FIFO processing, through the edge synchronization read and write method, the output data is accurately phase-aligned inside the FPGA, enabling end-to-end delay alignment of the sampled data of each channel from the input interface end to the data processing end inside the FPGA.

[0030] For the signals input to the trigger channel, digital non-encoded sampling above Gsps (Gigabit Samples per Second) is performed through the SerDes interface to increase the sampling rate of the trigger signal, thereby improving the time accuracy of the trigger signal to the ps level (the conventional solution uses ordinary IO ports for sampling with an accuracy of the ns level). The sampled data of the trigger signal also undergoes the edge synchronization read and write method, enabling end-to-end delay alignment of the trigger signal and the data of each acquisition channel from the input interface end to the data processing end.

[0031] After completing the above precise delay calibration, the data of all acquisition channels and the trigger channel achieve delay alignment from the input interface to the data processing interface. Using any one of the signals as a trigger can achieve high-precision trigger synchronization of all parallel channels within a single module.

[0032] The delay adjustment of trigger synchronization is automatically completed by the FPGA logic, and the software is not aware of the delay calibration data, which can be automatically completed by the FPGA logic controlling the hardware during the power-on initialization process of a single module.

[0033] As Figure 6 shown, another embodiment of the present invention relates to a multi-channel acquisition system based on automatic calibration of trigger synchronization, which is composed of multiple multi-channel acquisition modules in the previous embodiment. When interconnecting multiple acquisition modules, Figure 6 The dotted line in the figure represents the connection method of the reference clock between multiple modules. The ACQ1 module outputs the clk_out signal to the ACQ2 module. After locking the clock phase reference in the ACQ2 module, the ACQ2 module outputs the clock reference signal to the ACQ3 module for reference, and so on, enabling the sampling time synchronization of multiple modules.

[0034] Figure 6 The solid lines represent the input and output connections related to triggering. From the introduction of the signal interface of a single module, it is known that as the main acquisition module of the trigger channel, it is necessary to output the trigger signal to the slave acquisition module. Each cascaded module needs to have two signals connected to the upper-level module, namely, receiving the trigger synchronization signal sent by the upper-level module and returning the delayed trigger synchronization signal of the upper-level module, and maintaining the same signal transmission with the subsequent module.

[0035] For the last slave acquisition module ACQN, the main acquisition module ACQ1 is used as the slave acquisition module for signal connection. By this method, all modules are connected into a ring system connected end to end.

[0036] Another embodiment of the present invention relates to a multi-channel acquisition method based on trigger synchronization automatic calibration, which specifically includes the following content: S1. Acquisition of calibration data in each channel; The calibration signal is input into each analog channel and trigger channel, and is respectively conditioned and digitally quantified. After being received by the FPGA, the digitally quantified signals of each path are obtained inside the FPGA. Due to different conditioning methods, analog-to-digital quantization methods, digital signal transmission and parsing methods for each link, there will be different end-to-end delays from the input of the calibration signal at the same moment to the reception of the quantified signal by the FPGA. T_dly1 and T_dly2 are fixed values after initialization.

[0037] S2. Multi-channel trigger delay calibration and alignment in a single acquisition module; By passing the same calibration signal through different acquisition links, different delay quantization results are obtained. After clock domain conversion through an asynchronous FIFO, delay calibration is performed at the edge moment, and the cache read and write control of each channel is controlled, so that the delay deviation of each channel can be corrected, and synchronized acquisition data of all channels can be obtained at the FPGA end. At this time, any channel of a single module is used as the trigger signal, and accurate synchronous acquisition can be achieved for other passing triggers.

[0038] Further, S2 specifically includes the following content: S21. Cross-clock domain synchronization conversion; The data output after sampling and quantization by the ADC usually has a corresponding clock on the same path. Therefore, after the FPGA receives the data, clock synchronization processing needs to be performed to convert the data to the same clock domain. In this method, each acquisition channel parses the quantization data according to the quantization protocol of the corresponding ADC, and writes the corresponding data and the clock on the same path to the write port of the asynchronous FIFO inside the FPGA.

[0039] At the read port of the FIFO, the internal master clock of the FPGA is used to generate the read signal, synchronizing the acquired data in different clock domains to the same data processing clock domain.

[0040] During this process, due to the reset logic of each asynchronous FIFO and the cross-clock domain processing of data, there may be differences in the delay of each data initialization. This difference is processed by the subsequent delay synchronization processing algorithm.

[0041] S22, low congestion parallel edge judgment; The quantized sampling signal received in the FPGA is usually processed in parallel due to the internal master clock frequency limitation. For a 10Gsps signal, it is processed using 312.5MHz, and there are 32 sampling data under each master clock. The analog signal with a fixed input delay relationship, after passing through different analog-to-digital conversion links, the arrangement of the quantized data contains the delay information of the corresponding link. By setting the digital comparison method, the input phase synchronization point can be found in different quantized delay links.

[0042] In order to obtain the data delay information at 10Gsps, 20Gsps and higher sampling rates, it is necessary to process the multi-channel parallel data. Due to the timing requirements and logic level limitations in the FPGA, in the present invention, the parallel multi-channel data is segmented to reduce the number of parallel channels. The 32 data N0, N1... N31 under one clock are divided into two groups. The first group is N-1, N0... N15, and the second group is N15, N16... N31.

[0043] When processing the data quantized by the ADC, due to the existence of quantization noise and errors, the lower bits usually show random noise signals, and the Schmitt threshold comparison needs to be used during comparison. Search for the corresponding edge position within each group, set a 16-bit register, and each bit represents whether the corresponding order meets the structure of the digital Schmitt comparator. When searching for the rising edge, set the upper threshold com_h and the lower threshold com_l of the comparison level, and output the corresponding results according to the relationship between the data and the threshold according to the following conditions.

[0044] Condition 1: Nn>com_h, Condition 2: Nn>com_l, Condition 3: com_l≤Nn≤com_h; If Condition 1 is satisfied, the bit outputs 1; if Condition 2 is satisfied, the bit outputs 0; if Condition 3 is satisfied, the bit uses the result obtained from the previous bit comparison.

[0045] When processing the data quantized by high-speed SerDes usually used for triggering, since the quantization result is only 1 bit, the converted register can be directly obtained.

[0046] After obtaining multiple groups of comparison result registers in parallel for each channel, first search within each group for an edge determination of changing from 0 to 1 according to the priority of data points. If there is one, output the rising edge pos_edge_vld as 1, otherwise output 0, and output the corresponding bit index number pos_edge_idx.

[0047] In the case of sampling rate expansion, by splitting and combining parallel multiplexed data, a parallel trigger position search above 32 bits can be implemented inside the FPGA.

[0048] S23. Edge bit sequence shift; After performing edge determination on the data to obtain pos_edge_vld and pos_edge_idx, due to different delays in different links, the beats at which the edges appear and the corresponding pos_edge_idx are different.

[0049] First, adjust pos_edge_idx to be the same, use pos_edge_idx as the search condition, and perform data shift adjustment according to different values. As Figure 7 shown, taking 32-channel data per clock as an example, take the data of two consecutive clocks, N0, N1, N2…N31, N32, N33…N62, N63, and update the shift per clock. Select the corresponding data for output according to pos_edge_idx. When pos_edge_idx is 1, the data obtained per clock are N1~N32, N33~N64, N65~N96, and so on for other cases. After adjustment, the data edges of each link can be adjusted to the first sampling point under the main clock.

[0050] S24. Edge beat alignment operation; Due to different link delays, the edges of each channel of data after synchronization appear at different clocks and require different delay adjustments for synchronization. In this method, the read and write control of a synchronous FIFO is used for signal delay synchronization.

[0051] After reset, according to the input pos_edge_vld signal, enable the write enable of each channel FIFO. After determining that each channel FIFO reaches a certain threshold, synchronously enable the read enable of each channel FIFO, and a signal with consistent edges after synchronization can be obtained.

[0052] After processing through the above algorithm flow, the data of each acquisition link can be aligned for synchronous triggering in the FPGA, and the propagation delay and conversion quantization delay in the link are compensated through the adjustment algorithm.

[0053] S3. Precise calibration of the trigger delay between adjacent master and slave acquisition modules; On the premise of realizing the above-mentioned single-module multi-channel trigger synchronization, the trigger signal of the main acquisition module is fanned out to the slave acquisition module, and then returned to the main acquisition module from the slave acquisition module for line delay measurement. High-sampling-rate signal delay measurement can be achieved without using a high-speed ADC, but only with an FPGA, so as to obtain the round-trip delay of the trigger signal transmission between the two modules, thereby calculating the absolute time delay between the trigger signal obtained by the slave acquisition module and the true trigger moment, and then correcting the trigger moment calculation method of the slave acquisition module to achieve precise trigger synchronization between the master and slave acquisition modules. Since the round-trip measurement method is adopted, there are no strict requirements for the delay value of the inter-module interconnecting cable. The system is relied on for delay correction, reducing the hardware requirements in use.

[0054] Furthermore, the algorithm flow for delay calibration between adjacent acquisition modules is as follows: S31. Trigger acquisition synchronization calibration for each acquisition module; In each module, the self-provided calibration signal is used, and the calibration trigger signal is quantized using the high-speed SerDes interface of the FPGA. The quantized signal uses a method similar to that in the above section, and after protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge bit sequence shift, and edge beat alignment, the quantized data with trigger delay alignment in each module is obtained.

[0055] S32. Trigger delay measurement for the master and slave acquisition modules; The main acquisition module ACQ1 sends the calibration pulse signal to the slave acquisition module ACQ2 through the ACQ1 from trigger output interface. The slave acquisition module ACQ2 selects this signal as the input signal, and at the same time, after fanning out and copying this signal, it is sent back to the ACQ1 from feedback input through the ACQ2 main feedback output interface of ACQ2.

[0056] In ACQ1, two high-speed Serdes respectively quantify the calibration signal of ACQ1 and the signal fed back by ACQ2. After the calibration signal is output from the fan-out, it passes through the cable, the internal fan-out of ACQ2, and the feedback cable and then returns to ACQ1. After being quantified by the two-way Serdes, the delay of the quantized edge is the round-trip delay of the trigger lines of the two modules.

[0057] The transmission delay is composed of the circuit delay of the master and slave acquisition modules and the round-trip delay of the cable. Among them, for the circuit delay, during circuit design, the trigger output and feedback input are controlled to have equal-length traces, enabling high-precision delay control. Since the round-trip cable is a pair of equal-length wires, the cable round-trip delay can be considered symmetric. Therefore, only by dividing the total delay value Cal_dly of the calibration signal by 2 can the trigger signal transmission delay Trig_pdly between the master and slave acquisition modules be obtained.

[0058] S33. Trigger delay correction for master-slave acquisition modules; As Figure 8 shown, the obtained trigger signal propagation delay Trig_pdly is recorded through a register. After being read by the control software, it is sent to the slave acquisition module for correction of the trigger position. Since the trigger signal from the master acquisition module received by the slave acquisition module has a delay of Trig_pdly, after the slave acquisition module completes triggering and waveform capture, the trigger point is advanced, and the time value of Trig_pdly is corrected to obtain the true trigger point.

[0059] Since the slave acquisition module has performed trigger point forward shift correction, the corresponding pre-trigger depth and post-trigger depth of the slave acquisition module need to be adjusted by Trig_pdly accordingly to adapt to the sampling delay caused by trigger transmission.

[0060] S4. Trigger delay correction in a multi-acquisition-module multi-channel system; After completing the trigger synchronization of the above master-slave relationship, a one-dimensional array corresponding to the trigger delay correction value Trig_pdly of two adjacent acquisition modules in all interconnected modules can be obtained. When any analog or external trigger channel in any module in the entire system networking is selected as the system trigger channel, according to the trigger path transmission relationship, the trigger delays of subsequent modules are successively accumulated and sent down, so as to control the precise synchronization of triggering of all channels of all modules and obtain the result of precise alignment of parallel acquisition of all channels.

[0061] S5. Delay correction during system expansion; When channel expansion is required, a module can be added between any two modules in the entire ring system, and only the delay between the new module and the upstream and downstream modules needs to be calibrated, without the need to perform a full recalibration of the entire system. After the new module completes the trigger delay calibration with the upstream and downstream modules, the system delay setting is updated to use the expanded acquisition system.

[0062] At the same time, in the interface for trigger correction Trig_pdly, a software delay adjustment interface that can be adjusted by the user is reserved, and the correction can be further followed up according to the actual measurement results of the user.

[0063] S6. System accuracy test; Use two signals with a strictly synchronous phase relationship as the entire multi-channel input signal. For example, a pulse signal can be divided by a power splitter to obtain two input signals with fixed phases. These two signals are input into any two channels of the calibrated multi-channel acquisition system, and one of the two channels is selected as the trigger channel. Observe the waveform display result of the acquisition, and judge whether synchronous trigger acquisition is performed between the two channels through the function of the cursor measurement function.

[0064] When conducting the system accuracy test, the software automatically calculates the signal delay in the data collected by two channels. By implementing the edge judgment method through the software, the difference in the abscissa of the edges of the two channels is compared, and the results obtained each time are recorded in the statistical histogram. The overall synchronization accuracy index of the system after multiple tests can be measured through histogram statistics.

[0065] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and improvements, and can be changed within the scope of the concept described herein through the above teachings or the techniques or knowledge in related fields. And the changes and alterations made by those skilled in the art without departing from the spirit and scope of the present invention should all be within the protection scope of the appended claims of the present invention.

Claims

1. A multi-channel acquisition module based on trigger synchronization automatic calibration, characterized in that: The acquisition module includes a channel conditioning and acquisition circuit, a trigger and input / output feedback circuit, a clock synchronization and calibration signal generation circuit, and an FPGA reception and synchronization calibration circuit; The channel conditioning and acquisition circuit: is configured to condition the signal under test through gain adjustment, AC / DC coupling control, and bandwidth limitation, so that the signal meets the ADC sampling requirements; The trigger and input / output feedback circuit: is configured to implement the input and triggering of the external trigger signal, as well as the transmission and feedback of the trigger signal, and realize the trigger delay measurement between multiple channels; The clock synchronization and calibration signal generation circuit: is configured to generate the sampling clock, input and output the reference clock when multiple acquisition modules are cascaded, and generate the synchronization calibration signal for a single acquisition module; The FPGA reception and synchronization calibration circuit: is configured to receive the digital quantization signals sampled by each ADC, generate the corresponding sampling data stream after protocol parsing, and perform edge synchronization read and write after phase adjustment and edge alignment FIFO processing in the calibration mode, so that the sampling data of each channel is end-to-end aligned from the input interface to the data processing end inside the FPGA.

2. The multi-channel acquisition module based on trigger synchronization automatic calibration according to claim 1, wherein: The channel conditioning and acquisition circuit includes multiple acquisition channels. Each acquisition channel includes two input sources, namely the external signal under test input and the internally integrated calibration signal, which are selected by the first analog switch. When performing trigger synchronization calibration, the first analog switch selects the calibration signal as the input, and selects the signal under test as the input after the calibration trigger synchronization is completed; The selected signal is output to the ADC for acquisition after impedance adjustment, coupling, dynamic range adjustment, and offset adjustment. The data acquired by the ADC is input to the FPGA reception and synchronization calibration circuit; When each ADC in the acquisition channel is working, the conversion delay from the analog signal to the digital signal is fixed, and the sampling clock references of all ADCs are consistent.

3. A multi-channel acquisition module based on trigger synchronization automatic calibration according to claim 1, characterized in that: The trigger and input / output feedback circuit includes 5 signal input / output interfaces, namely the trigger signal EXT input, the main trigger input, the main feedback output, the slave trigger output, and the slave feedback input; The trigger signal EXT of the upper-level acquisition module is selected by the second analog switch to control the synchronization trigger of this acquisition module; when performing the synchronization trigger of multiple acquisition modules, the third analog switch of this acquisition module is controlled to select the main trigger input as the trigger signal of this acquisition module for the synchronous acquisition of multiple acquisition modules; during trigger calibration, this acquisition module uses the main trigger input signal sent by the upper-level acquisition module for triggering, and after fanning out the signal, it is sent back to the upper-level acquisition module through the main feedback output interface for trigger link delay measurement; This acquisition module outputs the used trigger signal to the lower-level acquisition module through the slave trigger output interface as the main trigger input of the lower-level acquisition module; during trigger calibration, this acquisition module receives the trigger signal fed back by the lower-level acquisition module through the slave feedback input interface for the trigger delay measurement from this acquisition module to the lower-level acquisition module.

4. A multi-channel acquisition module based on trigger synchronization automatic calibration according to claim 1, characterized in that: The clock synchronization and calibration signal generation circuit generates a clock reference signal required for the integrated phase-locked loop through a local crystal oscillator, and inputs it into the integrated phase-locked loop together with the externally provided clock reference signal. The integrated phase-locked loop selects the reference clock. When multiple acquisition modules are interconnected for multi-channel parallel sampling, multiple acquisition modules use a phase-coherent and same-frequency reference clock, and perform reference clock cascading through the interfaces of reference clock input and reference clock output. The clock reference output of the previous-level acquisition module is connected to this acquisition module as the reference clock input of this acquisition module. After common reference, the sampling clocks of multiple acquisition modules reach the state of same-frequency and phase coherence, that is, high-precision multi-channel synchronous acquisition can be performed. The integrated phase-locked loop generates the required acquisition master clock, and generates a divided calibration signal of 10 MHz and a reference clock signal of 10 MHz output to the next-level acquisition module through the integrated phase-locked loop. The generated calibration signal is fan-out to multiple acquisition channels through a clock fan-out device, and at the same time reduces the interference of jitter on the phase of the calibration signal. The generated calibration signal is respectively connected to each analog channel and external trigger channel in the acquisition module, and the consistency of the signal delay received by each channel is controlled by equal-length routing.

5. A multi-channel acquisition module based on trigger synchronization automatic calibration according to claim 1, characterized in that: The FPGA receives the signal input to the trigger channel by the synchronization and calibration circuit, and performs digital non-encoded sampling above Gsps through the SerDes interface, improves the sampling rate of the trigger signal, and further improves the time accuracy of the trigger signal to the ps level. The sampled data of the trigger signal also makes the trigger signal and the data of each acquisition channel achieve end-to-end alignment of the delay from the input interface end to the data processing end through the method of edge synchronous reading and writing. After precise delay calibration, the data of all acquisition channels and trigger channels have achieved delay alignment from the input interface to the data processing interface. Using any one of the signals as a trigger can achieve high-precision trigger synchronization of all parallel channels within a single acquisition module.

6. A multi-channel acquisition system based on trigger synchronization automatic calibration, characterized in that: The system includes multiple acquisition modules as described in any one of claims 1-5. When multiple acquisition modules are interconnected, the previous-level acquisition module outputs a clk_out signal to the next-level acquisition module, and after clock phase reference locking in the next-level acquisition module, outputs a clock reference signal to the next-next-level acquisition module for reference, thereby realizing the sampling time synchronization of multiple acquisition modules.

7. A multi-channel acquisition method based on trigger synchronization automatic calibration, characterized in that: The acquisition method includes: S1. Input the calibration signal into each analog channel and trigger channel, perform conditioning and digital quantization respectively, and after being received by the FPGA receiving and synchronization calibration circuit, obtain the digital quantization signals of each path inside the FPGA. S2. Pass the same calibration signal through different acquisition links to obtain different delay quantization results. After clock domain conversion through an asynchronous FIFO, perform delay calibration at the edge moment, control the cache reading and writing of each channel, correct the delay deviation of each channel, and obtain the data of synchronous acquisition of all channels. S3. By fanning out the trigger signal of the upper-level acquisition module to the lower-level acquisition module, and then returning it from the lower-level acquisition module to the upper-level acquisition module for line delay measurement, the round-trip delay of the trigger signal transmission between the two acquisition modules is obtained, so as to calculate the absolute time delay between the trigger signal obtained by the lower-level acquisition module and the real trigger moment, and then correct the trigger moment calculation method of the lower-level acquisition module to achieve precise synchronization of the triggers of the two acquisition modules; S4. When any analog channel or trigger channel in any acquisition module in the entire system networking is selected as the system trigger channel, according to the trigger path transmission relationship, the trigger delays of the subsequent acquisition modules are cumulatively issued in sequence, and then the precise synchronization of the triggers of all channels of all acquisition modules is controlled to obtain the result of precise alignment of parallel acquisitions of all channels.

8. A multi-channel acquisition method based on trigger synchronization automatic calibration according to claim 7, characterized in that: The specific content of S2 includes the following: S21. Each acquisition channel performs quantization data parsing according to the quantization protocol of the corresponding ADC, and writes the corresponding data and the associated clock into the write port of the internal asynchronous FIFO of the FPGA. At the read port of the FIFO, a read signal is generated using the main clock inside the FPGA to synchronize the acquisition data in different clock domains to the same data processing clock domain; S22. The generated quantization data is processed in parallel to obtain parallel multi-channel data. The parallel multi-channel data is segmented to obtain multiple groups of data. The corresponding edge positions are searched within each group, and a 16-bit register is set. Each bit represents whether the corresponding sequence meets the structure of the digital Schmitt comparator. When searching for the rising edge, the upper and lower threshold levels of the comparison level are set. According to the relationship between the data and the upper and lower thresholds, the corresponding results are output according to the set conditions. After obtaining the multi-group comparison result registers in parallel for each channel, within each group, search for the edge judgment of changing from 0 to 1 according to the priority of the data points. If there is one, output the rising edge pos_edge_vld as 1, otherwise output 0, and output the corresponding bit index number pos_edge_idx; S23. Since the delays of different links are different, resulting in different beats of the edge appearance and the corresponding pos_edge_idx, the pos_edge_idx is adjusted to be the same. Using pos_edge_idx as the search condition, data shift adjustment is performed according to different values. After adjustment, the data edges of each link are adjusted to the first sampling point under the main clock; S24. After reset, according to the input pos_edge_vld signal, the write enable of each FIFO is enabled. After determining that each FIFO reaches the threshold value, the read enable of each FIFO is synchronously enabled to obtain the signal with consistent edges after synchronization.

9. A multi-channel acquisition method based on trigger synchronization automatic calibration according to claim 7, characterized in that: The specific content of S3 includes the following: S31. In each acquisition module, use the built-in calibration signal, and use the SerDes interface of the FPGA to quantify the calibration trigger signal. The quantified signal undergoes protocol deserialization, cross-clock domain synchronization conversion, edge judgment, edge bit sequence shift, and edge beat alignment to obtain the quantified data with trigger delay alignment in each acquisition module. S32. The upper-level acquisition module sends the calibration signal to the lower-level acquisition module as an input signal. The lower-level acquisition module copies the calibration signal through fan-out and feeds it back to the upper-level acquisition module. The two SerDes of the upper-level acquisition module respectively quantify the calibration signal and the fed-back signal. After quantization by the two SerDes, the delay of the quantization edge is the round-trip delay of the trigger lines of the two acquisition modules. The transmission delay consists of the circuit delay of the two acquisition modules and the round-trip delay of the cable. Since the circuit delay is controlled by making the traces of the trigger output and the feedback input of equal length during circuit design, and the round-trip delay of the cable is considered symmetric because the round-trip cable is a pair of equal-length wires, dividing the total delay value Cal_dly of the calibration signal by 2 can obtain the trigger signal transfer delay Trig_pdly between the two acquisition modules. S33. Record the obtained trigger signal transfer delay Trig_pdly through a register. After being read by the control software, it is sent to the lower-level acquisition module to correct the trigger position in the lower-level acquisition module. Since the trigger signal received by the lower-level acquisition module from the upper-level acquisition module has a delay of Trig_pdly, after the lower-level acquisition module completes triggering and waveform capture, advance the trigger point and correct the time value of Trig_pdly to obtain the true starting point. Moreover, the pre-trigger depth and post-trigger depth corresponding to the lower-level acquisition module are adjusted by Trig_pdly to adapt to the sampling delay caused by trigger transmission.

10. A multi-channel acquisition method based on trigger synchronization automatic calibration according to any one of claims 7-9, characterized in that: The acquisition method further includes: when channel expansion is required, select to add an acquisition module between any two acquisition modules in the entire system, and perform calibration of the delay between the new acquisition module and the upper and lower acquisition modules. After the new acquisition module and the upper and lower acquisition modules complete the trigger delay calibration, update the system delay setting to enable the use of the expanded acquisition system. The acquisition method further includes system accuracy testing, and the system accuracy testing includes: using two signals with a synchronous phase relationship as the input signals for the entire multi-channel, inputting these two signal inputs into any two channels of the multi-channel acquisition system after calibration, selecting one of the two channels as the trigger channel, observing the waveform display result of the acquired signals, and determining whether synchronous trigger acquisition is performed between the two channels through the cursor measurement function.

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