Capacitive fully-differential two-stage digital-to-analog converter with progressive fault tolerance along with digits

Abstract

The invention discloses a capacitive fully-differential two-stage digital-to-analog converter capable of progressive fault tolerance along with digits. The capacitive fully-differential two-stage digital-to-analog converter comprises a signal input, a grounding capacitor, a low-order capacitor array with a progressive redundant capacitor, a bridging capacitor, a high-order capacitor array with a progressive redundant capacitor and a comparison logic, the low-order capacitor array with the progressive redundant capacitor is composed of a capacitor and a progressive redundant capacitor at the same-direction end and a capacitor and a progressive redundant capacitor at the reverse-direction end; the bridging capacitor is composed of two groups of bridging capacitors which are symmetrically distributed at the same-phase end and the opposite-phase end of the comparator; the high-order capacitor array with the progressive redundant capacitor is composed of a capacitor and a progressive redundant capacitor at the same-direction end and a capacitor and a progressive redundant capacitor at the reverse-direction end. A fault-tolerant mechanism formed by the redundant capacitors can actively correct misjudgment of the comparator, the problems that the fault-tolerant capacity of the comparator becomes poor along with increase of digits, the number of times of comparison is increased, power consumption is increased and the conversion speed is reduced due to the fact that the redundant capacitors are increased are solved, and the scheme has the advantages of high precision, small area and high robustness.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, relates to digital-to-analog converters, and particularly relates to a capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance along with the number of bits. Background Art

[0002] A capacitive digital-to-analog converter (CDAC) samples an input signal through an array of capacitors, and after making a decision bit by bit by a comparator, dynamically switches the connection state of the capacitors, and finally completes the approximation of the digital code. The circuit structure of the existing capacitive fully differential digital-to-analog converter is as Figure 1 shown, and it has the following two problems: 1) The fault tolerance ability deteriorates as the number of bits increases. The mis-switching caused by comparator noise or timing deviation will cause the accumulation of non-linear errors, and it cannot be corrected by the subsequent bit decision; 2) If a fault tolerance compensation circuit is added, the required number of comparisons will increase, resulting in increased power consumption and reduced conversion speed. Summary of the Invention

[0003] Objective of the Invention: To solve the problems that the fault tolerance ability of SARADC deteriorates as the number of bits increases, and the increase in the number of comparisons, power consumption, and conversion speed reduction caused by adding a fault tolerance compensation circuit, a capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance along with the number of bits is provided.

[0004] Technical Solution: To achieve the above objective, the present invention provides a capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance along with the number of bits, including: signal input, ground capacitors, a low-bit capacitor array with progressive redundant capacitors, bridging capacitors, a high-bit capacitor array with progressive redundant capacitors, and comparison logic;

[0005] The signal input is composed of introducing a fully differential input signal V ip and V in through a switching network, where V ip and V in are the in-phase terminal signal and the anti-phase terminal signal respectively;

[0006] The ground capacitors are composed of the ground capacitors C d1 , C d2 at the in-phase terminal, and the ground capacitors C d1 , C d2 at the anti-phase terminal;

[0007] The low-bit capacitor array with progressive redundant capacitors is composed of the capacitors C1 to C i / 2-1 , progressive redundant capacitor C 4C , …, C (i / 2-6)C , C (i / 2-2)C at the in-phase terminal, and the capacitors C1 to C i / 2-1 , progressive redundant capacitor C 4C , …, C(i / 2-6)C , C (i / 2-2)C which consists of, where i is an even number and i ≥ 10;

[0008] The bridging capacitor consists of two groups of bridging capacitors C symmetrically distributed at the non-inverting and inverting terminals of the comparator a which consists of;

[0009] The high-order capacitor array with progressive redundant capacitors consists of capacitors C at the non-inverting end i / 2 ~C i-1 , progressive redundant capacitor C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C and capacitors C at the inverting end i / 2 ~C i-1 , progressive redundant capacitor C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C which consists of;

[0010] The comparison logic consists of a high-speed dynamic comparator and digital logic;

[0011] The lower plates of the lower-order capacitors in the lower-order capacitor array and the lower plates of the high-order capacitors in the high-order capacitor array are both connected to the reference voltage V ref , common-mode voltage V cm , and ground GND (realized by a three-bit selector for dynamic configuration);

[0012] The bridging capacitor C a is used to dynamically balance voltage changes and ensure the linear weight transfer relationship of the segmented structure.

[0013] Furthermore, the number of redundant capacitors in the lower-order capacitor array is i / 7, taking the integer; the number of redundant capacitors in the high-order capacitor array is i / 5, taking the integer.

[0014] Furthermore, the output terminal of the fully differential input signal V ip is connected to the grounded capacitor C at the non-inverting end d2 , the lower-order capacitor array, and the upper plate of the bridging capacitor C a ; the fully differential input signal V in is connected to the grounded capacitor C at the inverting end d2 , the lower-order capacitor array, and the upper plate of the bridging capacitor C a .

[0015] Furthermore, the lower plates of the grounded capacitors C d1 , C d2 are fixedly grounded; the upper plate of the grounded capacitor C d1 is connected to the upper plates of all the capacitors in the high-order capacitor and the lower plate of the bridging capacitor C a ; the grounded capacitor Cd2 is connected to the output terminal of the signal input, all the upper capacitor plates of the low capacitors, and the upper capacitor plate of the bridging capacitor C a .

[0016] Furthermore, the low capacitor arrays of the progressive redundant capacitors all maintain a binary weight relationship. The progressive redundant capacitors C 4C , …, C (i / 2-6)C , C (i / 2-2)C are the same as the previous capacitor; the upper capacitor plates of the in-phase capacitors (C1~C i / 2-1 and the progressive redundant capacitors C 4C , …, C (i / 2-6)C , C (i / 2-2)C ) are connected to the output terminal of the signal V ip , the upper capacitor plate of the in-phase bridging capacitor C a ; the upper capacitor plates of the anti-phase capacitors (C1~C i / 2-1 and the progressive redundant capacitors C 4C , …, C (i / 2-6)C , C (i / 2-2)C ) are connected to the output terminal of the signal V in , the upper capacitor plate of the anti-phase bridging capacitor C a .

[0017] Furthermore, the high capacitor arrays of the progressive redundant capacitors all maintain a high-order binary weight relationship; the upper capacitor plates of the in-phase high capacitors (C i / 2 ~C i-1 , the progressive redundant capacitors C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C ) are connected to the upper capacitor plate of the in-phase grounding capacitor C d1 , the lower capacitor plate of the bridging capacitor C a ; the upper capacitor plates of the anti-phase high capacitors (C i / 2 ~C i-1 , the progressive redundant capacitors C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C ) are connected to the upper capacitor plate of the anti-phase grounding capacitor C d1 , the lower capacitor plate of the bridging capacitor C a .

[0018] Furthermore, the upper capacitor plate of the in-phase bridging capacitor C a is connected to the output terminal of the signal V ip , the upper capacitor plate of the in-phase grounding capacitor C d2 , the low capacitors (C1~C i / 2-1 and the progressive redundant capacitors C 4C , …, C (i / 2-6)C , C (i / 2-2)C) is connected to the upper plate, and the lower plate is grounded to the in-phase terminal capacitance C d1 The upper plate, the high-order capacitance (C i / 2 ~C i-1 , the progressive redundant capacitance C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C ) The upper plate is connected to the in-phase input terminal of the comparison logic; the anti-phase terminal is bridged with the capacitance C a The upper plate is connected to the output terminal of the signal V in , and the anti-phase terminal is grounded to the capacitance C d2 The upper plate, the low-order capacitance array (C1~C i / 2-1 and the progressive redundant capacitance C 4C , …, C (i / 2-6)C , C (i / 2-2)C ) The upper plate is connected, and the lower plate is grounded to the anti-phase terminal capacitance C d1 The upper plate, the high-order capacitance array (C i / 2 ~C i-1 , the progressive redundant capacitance C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C ) The upper plate is connected to the anti-phase input terminal of the comparison logic.

[0019] Furthermore, the operation method of the low-order capacitance array with progressive redundant capacitance includes: initially, the lower plates of all low-order capacitances are connected to the common-mode voltage V cm , the upper plates sample the input signal, wait for each bit of the comparator to complete the comparison before switching, start from the highest-order capacitance in sequence. If V ip >V in , then the lower plate of the maximum capacitance at the in-phase terminal is connected to GND, and the lower plate of the maximum capacitance at the anti-phase input terminal is connected to V ref , otherwise, the lower plate of the maximum capacitance at the in-phase terminal is connected to V ref , and the lower plate of the maximum capacitance at the anti-phase input terminal is connected to GND. This process repeats until the lower plates of the lowest-order capacitances are determined.

[0020] Furthermore, the operation method of the high-order capacitance array with progressive redundant capacitance includes: initially, the lower plates of all high-order capacitances are connected to the common-mode voltage V cm , the upper plates sample the input signal, wait for each bit of the comparator to complete the comparison before switching, start from the highest-order capacitance in sequence. If V ip >V in , then the lower plate of the maximum capacitance at the in-phase terminal is connected to GND, and the lower plate of the maximum capacitance at the anti-phase input terminal is connected to V ref , otherwise, the lower plate of the maximum capacitance at the in-phase terminal is connected to V ref, the lower plate of the maximum capacitance of the inverting input terminal is connected to GND, and this process is repeated until the lower plate of the lowest bit capacitance is determined.

[0021] The high-speed dynamic comparator is composed of a Strong-Arm dynamic comparator; the digital logic is composed of asynchronous SAR logic. The comparison logic integrates the comparator and the digital logic, and adjusts the connection of the lower plate of the capacitance to V ref 、V cm or GND in real time according to the judgment result to achieve low-power successive approximation. The input terminal of the comparator is connected to the lower plate of the bridging capacitor C a , the upper plate of the grounding capacitor C d1 , the high-order capacitance array: the capacitances C i / 2 ~C i-1 , the progressive redundant capacitance C (i / 2+2)C 、C (i / 2+4)C 、C (i / 2+4)C 、…、C (i-2)C are connected.

[0022] The calculation methods of the grounding capacitance and the bridging capacitance in the present invention include:

[0023] Step signals with an amplitude of V R are respectively input at two access points, and their changes to the output V o of the CDAC are respectively:

[0024]

[0025] where: C Mt is the total capacitance value of the high-order capacitances, C Lt is the total capacitance value of the low-order capacitances, and i is the number of bits of the ADC;

[0026] X = C Mt (C a + C Lt ) + C a C Lt

[0027] In order to maintain the correct weight and ensure the linearity of the ADC, it is necessary to have:

[0028] dV o1 = 2dV o2

[0029] Therefore So where C u is the unit capacitance.

[0030] In the present invention, the fault-tolerant mechanism composed of redundant capacitors can actively correct the misjudgment of the comparator, avoiding the problems that its fault-tolerant ability deteriorates as the number of bits increases, and the increase in the number of comparisons, power consumption, and conversion speed caused by adding redundant capacitors. The two-stage segmented architecture (the high-order and low-order capacitors are coupled by voltage division through a bridging capacitor) reduces the capacitance value of the highest-order capacitor to 1 / 2 of the existing solution N ; increasing V cm level enables the direct comparison without switch switching for the first time, reducing the energy consumption. This solution combines high precision, small area, and strong robustness, and is suitable for low-power and high-integration scenarios such as Internet of Things sensing and portable medical devices.

[0031] Advantages: Compared with the prior art, the present invention has the following advantages:

[0032] 1. In the present invention, redundant capacitors C 4C ,..., C (i / 2-2)C , C (i / 2+2)C , C (i / 2+4)C ,..., C (i-2)C are added, enabling the compensation of errors caused by miscomparisons of subsequent comparators and significantly improving the linearity;

[0033] 2. In the present invention, a bridging capacitor C a and V cm voltage are added, dividing the capacitor array into two segments: high-order and low-order, keeping the common-mode voltage unchanged, reducing the increase in the number of comparisons required due to the addition of redundant capacitors, improving the conversion speed, and reducing the power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a circuit diagram of an existing capacitive fully differential digital-to-analog converter;

[0035] Figure 2 is a circuit diagram of a capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance proposed by the present invention;

[0036] Figure 3 is a diagram for calculating the capacitance values of each capacitor in the present invention;

[0037] Figure 4 is a circuit simulation result diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] The present invention will be further clarified below in conjunction with the drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, various equivalent modifications made by those skilled in the art to the present invention fall within the scope defined by the appended claims of this application.

[0039] As Figure 2As shown, this embodiment provides a capacitive fully differential two-stage digital-to-analog converter with progressive bitwise fault tolerance, which consists of a signal input 10, a ground capacitance 20, a low-bit capacitance array 30 with progressive redundant capacitance, a bridging capacitance 40, a high-bit capacitance array 50 with progressive redundant capacitance, and a comparison logic 60.

[0040] Among them, the signal input 10 is composed of a fully differential input signal V introduced through a switching network ip (in-phase terminal) and V in (anti-phase terminal);

[0041] The ground capacitance 20 is composed of the ground capacitances C d1 , C d2 located at the non-inverting terminal of the comparator and the ground capacitances C d1 , C d2 located at the inverting terminal of the comparator;

[0042] The low-bit capacitance array 30 with progressive redundant capacitance is composed of the capacitances C1 to C5, the progressive redundant capacitance C 4C located at the non-inverting terminal of the comparator and the capacitances C1 to C5, the progressive redundant capacitance C 4C located at the inverting terminal of the comparator;

[0043] The bridging capacitance 40 is composed of two groups of bridging capacitances C a symmetrically distributed at the non-inverting and inverting terminals of the comparator;

[0044] The high-bit capacitance 50 with progressive redundant capacitance is composed of the capacitances C6 to C 11 , the progressive redundant capacitances C 8C , C 10C located at the non-inverting terminal of the comparator and the capacitances C6 to C 11 , the progressive redundant capacitances C 8C , C 10C located at the inverting terminal of the comparator;

[0045] The comparison logic (60) is composed of a high-speed dynamic comparator and digital logic.

[0046] In the signal input 10, the output terminal of the input signal V ip is connected to the upper plates of the ground capacitance C d2 at the non-inverting terminal, the low-bit capacitance C1, the low-bit capacitance C2, the low-bit capacitance C3, the low-bit capacitance C4, the redundant capacitance C 4C , the low-bit capacitance C5, and the bridging capacitance C a ; the output terminal of the input signal V in is connected to the upper plates of the ground capacitance C d2 at the inverting terminal, the low-bit capacitance C1, the low-bit capacitance C2, the low-bit capacitance C3, the low-bit capacitance C4, the redundant capacitance C 4C , the low-bit capacitance C5, and the bridging capacitance Ca is connected to the upper plate.

[0047] Among them, the input signal V ip and the input signal V in are a pair of fully differential signals. Compared with traditional single-ended signals, this input method reduces offset error and only causes gain error without affecting the linearity of the entire ADC.

[0048] In the ground capacitance 20, the ground capacitance C at the non-inverting terminal d1 is connected to the upper plates of the high-order capacitance C6, high-order capacitance C7, high-order capacitance C8, high-order capacitance C 8C , high-order capacitance C9, high-order capacitance C 10 , high-order capacitance C 10C , high-order capacitance C 11 and the upper plate of the bridging capacitance C a and the lower plate; the ground capacitance C at the inverting terminal d1 is connected to the upper plates of the high-order capacitance C6, high-order capacitance C7, high-order capacitance C8, high-order capacitance C 8C , high-order capacitance C9, high-order capacitance C 10 , high-order capacitance C 10C , high-order capacitance C 11 and the upper plate of the bridging capacitance C a . The ground capacitance C at the non-inverting terminal d2 is connected to the output terminal of the input signal V ip , the lower-order capacitance C1, lower-order capacitance C2, lower-order capacitance C3, lower-order capacitance C4, redundant capacitance C 4C , lower-order capacitance C5, and the upper plate of the bridging capacitance C a ; the ground capacitance C at the inverting terminal d2 is connected to the output terminal of the input signal V ip , the lower-order capacitance C1, lower-order capacitance C2, lower-order capacitance C3, lower-order capacitance C4, redundant capacitance C 4C , lower-order capacitance C5, and the upper plate of the bridging capacitance C a . In order to maintain the respective weights of the high-order capacitance and the lower-order capacitance in the segmented structure, the lower plate of the ground capacitance always remains grounded, and the upper plate is connected to the bridging capacitance and the high-order capacitance and the lower-order capacitance respectively. Among them, the capacitance value of the ground capacitance C d1 is the unit capacitance C u , and the capacitance value of the ground capacitance C d2 is 6C u .

[0049] In the lower-order capacitance array 30 with progressive redundant capacitance, the upper plate of the capacitance C1 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitance C2, the upper plate of the capacitance C3, the upper plate of the capacitance C4, redundant capacitance C 4CThe upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate. The upper plate of the capacitor C2 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C1, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate; the upper plate of the capacitor C3 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate; the upper plate of the capacitor C4 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C3, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate; the upper plate of the capacitor C4 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the upper plate of the capacitor C5, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate; the upper plate of the capacitor C5 at the non-inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate, and the bridging capacitor C at the non-inverting terminal a are connected to the upper plate; the upper plate of the capacitor C1 at the inverting terminal is connected to the output terminal of the input signal V ip , the upper plate of the capacitor C2, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the inverting terminal a are connected to the upper plate; the upper plate of the capacitor C2 at the inverting terminal is connected to the output terminal of the input signal V in , the upper plate of the capacitor C1, the upper plate of the capacitor C3, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the inverting terminal a are connected to the upper plate; the upper plate of the capacitor C3 at the inverting terminal is connected to the output terminal of the input signal V in , the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C4, the redundant capacitor C 4C The upper plate of the upper plate of the capacitor C5, and the bridging capacitor C at the inverting terminal a are connected to the upper plate; the upper plate of the capacitor C4 at the inverting terminal is connected to the output terminal of the input signal V inThe output terminal, the upper plate of capacitor C1, the upper plate of capacitor C2, the upper plate of capacitor C3, the redundant capacitor C 4C The upper plate, the bridging capacitor C of the inverting terminal a The upper plate is connected; the redundant capacitor C of the inverting terminal 4C The upper plate is connected to the input signal V in The output terminal, the upper plate of capacitor C1, the upper plate of capacitor C2, the upper plate of capacitor C3, the upper plate of capacitor C4, the upper plate of capacitor C5, the bridging capacitor C of the inverting terminal a The upper plate is connected; the upper plate of capacitor C5 of the inverting terminal is connected to the input signal V in The output terminal, the upper plate of capacitor C1, the upper plate of capacitor C2, the upper plate of capacitor C3, the upper plate of capacitor C4, the redundant capacitor C 4C The upper plate, the bridging capacitor C of the inverting terminal a The upper plates are connected; all the lower plates of the low-order capacitors are connected to the three-way selection connection line V ref , V cm , GND.

[0050] Among them, the capacitance value of C1 is the unit capacitance C u , the capacitance value of C2 is 2C u , the capacitance value of C3 is (i / 2 - 2) u , the capacitance value of C4 is 8C u , the redundant capacitor C 4C The capacitance value is 8C u , the capacitance value of C5 is 16C u , except for the redundant capacitor, it increases in binary. All the lower plates of the low-order capacitors are initially connected to the common-mode voltage V cm , the upper plates sample the input signal, wait for each bit of the comparator to complete the comparison and then switch, starting from the high-order capacitor C5 in sequence. If V ip > V in , then the lower plate of the largest capacitor at the non-inverting terminal is connected to GND, and the lower plate of the largest capacitor at the inverting input terminal is connected to V ref , otherwise, the lower plate of the largest capacitor at the non-inverting terminal is connected to V ref , the lower plate of the largest capacitor at the inverting input terminal is connected to GND, and this process is repeated until the lower plate of the lowest-order capacitor C1 is determined.

[0051] The bridging capacitor 40 includes: the bridging capacitor C of the non-inverting terminal a , the bridging capacitor C of the inverting terminal a . The upper plate of the bridging capacitor C of the non-inverting terminal a is connected to the output terminal of the input signal V ip , the upper plate of the grounded capacitor C d2 , the upper plate of the low-order capacitor C1, the upper plate of the low-order capacitor C2, the upper plate of the low-order capacitor C3, the upper plate of the low-order capacitor C4, the redundant capacitor C4C The upper plate is connected to the upper plate of the low - level capacitor C5; the lower plate is connected to the grounded capacitor C d1 The upper plate is connected to the upper plate of the high - level capacitor C6, the upper plate of the high - level capacitor C7, the upper plate of the high - level capacitor C8, the upper plate of the high - level capacitor C 8C The upper plate is connected to the upper plate of the high - level capacitor C9, the upper plate of the high - level capacitor C 10 The upper plate is connected to the upper plate of the high - level capacitor C 10C The upper plate is connected to the upper plate of the high - level capacitor C 11 The upper plate is connected to the non - inverting input terminal of the comparator; the bridging capacitor C of the inverting terminal a The upper plate is connected to the input signal V ip The output terminal of, the grounded capacitor C d2 The upper plate is connected to the upper plate of the low - level capacitor C1, the upper plate of the low - level capacitor C2, the upper plate of the low - level capacitor C3, the upper plate of the low - level capacitor C4, the upper plate of the redundant capacitor C 4C The upper plate is connected to the upper plate of the low - level capacitor C5; the lower plate is connected to the grounded capacitor C d1 The upper plate is connected to the upper plate of the high - level capacitor C6, the upper plate of the high - level capacitor C7, the upper plate of the high - level capacitor C8, the upper plate of the high - level capacitor C 8C The upper plate is connected to the upper plate of the high - level capacitor C9, the upper plate of the high - level capacitor C 10 The upper plate is connected to the upper plate of the high - level capacitor C 10C The upper plate is connected to the upper plate of the high - level capacitor C 11 The upper plate is connected to the inverting input terminal of the comparator.

[0052] Among them, to balance the weight relationship between the high - level capacitor and the low - level capacitor, the capacitance value of the bridging capacitor Ca is 3Cu. For the LSB bit, all capacitors except the bridging capacitor are in parallel, which is equivalent to adding the capacitance values, while the bridging capacitor is in series with the other capacitors in the LSB bit, thus reducing the total capacitance value of the LSB section. By reasonably setting the capacitance value of the bridging capacitor through the formula, the voltage change of the high - level capacitor can be made twice that of the low - level capacitor.

[0053] In the high - level capacitor array 50 with progressive redundant capacitors, the upper plate of the capacitor C6 at the non - inverting end is connected to the non - inverting input terminal of the comparator, the upper plate of the capacitor C7, the upper plate of the capacitor C8, the upper plate of the capacitor C 8C The upper plate, the upper plate of the capacitor C9, the upper plate of the capacitor C 10 The upper plate, the upper plate of the capacitor C 10C The upper plate, the upper plate of the capacitor C 11 The upper plate, the bridging capacitor C at the non - inverting end a The lower plate is connected; the upper plate of the capacitor C7 at the non - inverting end is connected to the non - inverting input terminal of the comparator, the upper plate of the capacitor C6, the upper plate of the capacitor C8, the upper plate of the capacitor C 8C The upper plate, the upper plate of the capacitor C9, the upper plate of the capacitor C 10 The upper plate, the upper plate of the capacitor C 10C The upper plate, the upper plate of the capacitor C 11 The upper plate, the bridging capacitor C at the non - inverting enda The upper plate of capacitor C8 at the same-polarity end is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C 8C the upper plate, capacitor C 10 the upper plate, capacitor C 10C the upper plate, capacitor C 11 the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C at the same-polarity end 8C is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C9, C 10 the upper plate, capacitor C 10C the upper plate, capacitor C 11 the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C9 at the same-polarity end is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C 8C the upper plate, capacitor C 10 the upper plate, capacitor C 10C the upper plate, capacitor C 11 the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C at the same-polarity end 10 is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C 8C the upper plate, capacitor C9, capacitor C 10C the upper plate, capacitor C 11 the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C at the same-polarity end 10C is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C 8C the upper plate, capacitor C9, capacitor C 10 the upper plate, capacitor C 11 the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C at the same-polarity end 11 is connected to the non-inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C 8C the upper plate, capacitor C9, capacitor C 10 the upper plate, capacitor C 10C the upper plate, the bridging capacitor C at the same-polarity end a the lower plate; the upper plate of capacitor C6 at the opposite-polarity end is connected to the inverting input terminal of the comparator, the upper plates of capacitors C7, C8, C 8CThe upper plate, the upper plate of capacitor C9, capacitor C 10 The upper plate, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C7 at the reverse terminal is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C8, capacitor C 8C The upper plate, the upper plate of capacitor C9, capacitor C 10 The upper plate, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C8 at the non-inverting terminal is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C7, capacitor C 8C The upper plate, the upper plate of capacitor C9, capacitor C 10 The upper plate, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C at the reverse terminal 8C is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C7, the upper plate of capacitor C8, the upper plate of capacitor C9, capacitor C 10 The upper plate, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C9 at the reverse terminal is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C7, the upper plate of capacitor C8, capacitor C 8C The upper plate, capacitor C 10 The upper plate, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C at the reverse terminal 10 is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C7, the upper plate of capacitor C8, capacitor C 8C The upper plate, the upper plate of capacitor C9, capacitor C 10C The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; the upper plate of capacitor C at the reverse terminal 10C is connected to the inverting input terminal of the comparator, the upper plate of capacitor C6, the upper plate of capacitor C7, the upper plate of capacitor C8, capacitor C 8C The upper plate, the upper plate of capacitor C9, capacitor C 10 The upper plate, capacitor C 11 The upper plate, the bridging capacitor C at the reverse terminala is connected to the lower plate; the capacitor C at the reverse terminal 11 The upper plate is connected to the inverting input terminal of the comparator, the upper plates of capacitors C6, C7, C8, C 8C upper plate, the upper plate of capacitor C9, C 10 upper plate, C 10C upper plate, the bridging capacitor C at the reverse terminal a is connected to the lower plate; among them, the lower plates of all high-order capacitors are connected to the three-way selection connection line V ref , V cm , GND.

[0054] Among them, the redundant error correction mechanism: for a certain input value, there are multiple digital codes code corresponding to it. For example, in a traditional ADC, the value 8 only corresponds to a group of codes 01000. If this bit comparison is incorrect, it cannot be compensated later. However, in the present invention, due to the addition of redundant capacitors, the weight of the redundant capacitor capacitance is equal to the capacitance value of the previous capacitor. Therefore, the value 8 corresponds to two groups of codes 001000 and 010000, which provides a certain fault tolerance space.

[0055] Among them, the capacitance value of C6 is the unit capacitance 2C u , the capacitance value of C7 is 4C u , the capacitance value of C8 is 8C u , the redundant capacitor C 8C has a capacitance value of 8C u , the capacitance value of C9 is 16C u , C 10 has a capacitance value of 32C u , the redundant capacitor C 10C has a capacitance value of 32C u , C 11 has a capacitance value of 64C u , except for the redundant capacitor, it increases in binary. The initial lower plates of all high-order capacitors are connected to the common-mode voltage V cm , the upper plates sample the input signal, wait for each bit comparison of the comparator to be completed and then switch, starting from the highest-order capacitor C 11 and proceeding in sequence. If V ip >V in , then the lower plate of the largest capacitor at the non-inverting terminal is connected to GND, and the lower plate of the largest capacitor at the inverting input terminal is connected to V ref , otherwise, the lower plate of the largest capacitor at the non-inverting terminal is connected to V ref , and the lower plate of the largest capacitor at the inverting input terminal is connected to GND. This process is repeated until the lower plate of the lowest-order capacitor C6 is determined.

[0056] According to Figure 3 shown, calculate the sizes of the grounding capacitor and the bridging capacitor: Input amplitudes of V are applied at points ① and ② respectivelyR step signal, the change in its output V of the CDAC is respectively: o The change amounts are:

[0057]

[0058] where: C Mt =(C6 + C7 + C8 + C 8C + C9 + C 10 + C 10C + C 11 ) + C d1 = 166C u + C d1

[0059] C Lt =(C1 + C2 + C3 + C4 + C 4C + C5) + C d2 = 39C u + C d2

[0060] X = C Mt (C a + C Lt ) + C a C Lt

[0061] To maintain the correct weights and ensure the ADC linearity, it must be that:

[0062] dV o1 = 2dV o2 Therefore 2(C a + C Lt ) = 32C a

[0063] So where C u is the unit capacitance with a capacitance value of 20 fF.

[0064] In the capacitor array, to satisfy the binary weight relationship, the voltage change value of the high - order capacitor is twice that of the previous capacitor. By taking the double - relationship with the same - amplitude step signal at points ① and ②, the sizes of the grounded capacitor and the bridging capacitor can be calculated.

[0065] The high - speed dynamic comparator is composed of a Strong - Arm dynamic comparator; the digital logic is composed of asynchronous SAR logic.

[0066] In the comparison logic 60, the non - inverting input terminal of the comparator is connected to the lower plate of the bridging capacitor C a , the upper plate of the grounded capacitor C d1 , the upper plate of the high - order capacitor C6, the upper plate of the high - order capacitor C7, the upper plate of the high - order capacitor C8, the upper plate of the high - order capacitor C8C The upper plate, the upper plate of the high - level capacitor C9, the high - level capacitor C 10 The upper plate, the high - level capacitor C 10C The upper plate, the high - level capacitor C 11 are connected; the inverting input terminal of the comparator is bridged with the capacitor C at the inverting end a The lower plate, the grounded capacitor C d1 The upper plate, the upper plate of the high - level capacitor C6, the upper plate of the high - level capacitor C7, the upper plate of the high - level capacitor C8, the upper plate of the high - level capacitor C 8C The upper plate, the upper plate of the high - level capacitor C9, the high - level capacitor C 10 The upper plate, the high - level capacitor C 10C The upper plate, the high - level capacitor C 11 are connected; the output V of the comparator out is connected to the digital logic; the digital logic feeds the result back to the three - way selection connection line V ref 、V cm 、GND.

[0067] In summary, adopting the capacitive fully - differential two - stage digital - to - analog converter circuit with progressive fault tolerance according to the number of bits can greatly reduce the number of capacitors, thus increasing the number of bits of the ADC. The redundant capacitors greatly improve the linearity of the ADC, and at the same time, the conversion speed also increases. Figure 4 This is a 256 - point FFT spectrum diagram of a 12 - bit SAR ADC for the simulation of this digital - to - analog converter circuit. It can be seen that at a sampling rate of 10 MHz, the effective number of bits SNR = 75.93 dB and ENOB = 11.90 dB.

Claims

1. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to the number of bits, characterized in that Including: Signal input, ground capacitance, low - order capacitance array with progressive redundant capacitance, bridging capacitance, high - order capacitance array with progressive redundant capacitance, and comparison logic; The signal input is composed of a fully differential input signal V introduced through a switching network ip and V in which are composed of V ip and V in respectively being the in-phase terminal signal and the anti-phase terminal signal; The grounding capacitance is composed of the grounding capacitances C d1 , C d2 at the non-inverting terminal and the grounding capacitances C d1 , C d2 at the inverting terminal; The low - order capacitor array with progressive redundant capacitors consists of capacitors C1 to C at the same - polarity end i / 2-1 , progressive redundant capacitor C 4C , …, C (i / 2-6)C , C (i / 2-2)C and capacitors C1 to C at the opposite - polarity end i / 2-1 , progressive redundant capacitor C 4C , …, C (i / 2-6)C , C (i / 2-2)C , where i is an even number and i ≥ 10; The bridging capacitor is composed of two groups of bridging capacitors C symmetrically distributed at the non-inverting terminal and inverting terminal of the comparator. a ; The high-order capacitor array with progressive redundant capacitors consists of capacitors C at the same-direction end i / 2 ~C i-1 , progressive redundant capacitors C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C and capacitors C at the opposite-direction end i / 2 ~C i-1 , progressive redundant capacitors C (i / 2+2)C , C (i / 2+4)C , C (i / 2+4)C , …, C (i-2)C ; The comparison logic is composed of a high - speed dynamic comparator and digital logic; The lower electrodes of the low capacitors in the low capacitor array and the lower electrodes of the high capacitors in the high capacitor array are both connected to the reference voltage V ref , the common-mode voltage V cm , and the ground GND; Bridging capacitor C a It is used to dynamically balance voltage changes and ensure the linear weight transfer relationship of the segmented structure.

2. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 1, characterized in that The number of redundant capacitances in the low - order capacitance array is i / 7, taking the integer; the number of redundant capacitances in the high - order capacitance array is i / 5, taking the integer.

3. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 1, wherein The output terminal of the fully differential input signal V ip is connected to the ground capacitance C d2 of the non-inverting terminal, the low capacitance array, and the upper plate of the bridging capacitance C a ; the fully differential input signal V in is connected to the ground capacitance C d2 of the inverting terminal, the low capacitance array, and the upper plate of the bridging capacitance C a .

4. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 3, characterized in that, Ground capacitance C d1 , C d2 The lower plate is fixedly grounded; the ground capacitance C d1 The upper plate is connected to all the upper plates of the high - level capacitors and the lower plate of the bridging capacitor C a The ground capacitance C d2 Is connected to the output end of the signal input, all the upper plates of the low - level capacitors, and the upper plate of the bridging capacitor C a Is connected.

5. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 4, characterized in that The low-order capacitance arrays of the progressive redundant capacitors all maintain a binary weight relationship. The progressive redundant capacitors C 4C ,..., C (i / 2-6)C , C (i / 2-2)C are the same as the previous capacitor; the upper plate of the in-phase terminal capacitor is connected to the signal V ip output terminal and the upper plate of the in-phase terminal bridging capacitor C a ; the upper plate of the anti-phase terminal capacitor is connected to the signal V in output terminal and the upper plate of the anti-phase terminal bridging capacitor C a .

6. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 5, wherein The high - order capacitor arrays of the progressive redundant capacitors all maintain the high - order binary weight relationship; the upper plates of the high - order capacitors at the in - phase terminal are connected to the upper plates of the in - phase terminal grounded capacitors C d1 and the lower plates of the bridging capacitors C a ; the upper plates of the high - order capacitors at the anti - phase terminal are connected to the upper plates of the anti - phase terminal grounded capacitors C d1 and the lower plates of the bridging capacitors C a .

7. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 6, characterized in that In-phase terminal bridging capacitor C a The upper plate is connected to the output terminal of signal V ip and the in-phase terminal grounding capacitor C d2 The upper plate is connected to the upper plates of the low-capacitance capacitor and the in-phase terminal grounding capacitor C d1 The upper plate is connected to the upper plates of the high-capacitance capacitor, the upper plate of the low-capacitance capacitor, and the non-inverting input terminal of the comparison logic; the anti-phase terminal bridging capacitor C a The upper plate is connected to the output terminal of signal V in and the anti-phase terminal grounding capacitor C d2 The upper plate is connected to the upper plates of the low-capacitance capacitor array and the anti-phase terminal grounding capacitor C d1 The upper plate is connected to the upper plates of the high-capacitance capacitor array, the upper plate of the low-capacitance capacitor array, and the inverting input terminal of the comparison logic.

8. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 7, characterized in that The operation method of the low - order capacitor array with progressive redundant capacitors includes: initially, the lower plates of all low - order capacitors are connected to the common - mode voltage V cm , the upper plates sample the input signal, wait for each bit of the comparator to complete the comparison before switching, starting from the highest - order capacitor in sequence. If V ip >V in , then the lower plate of the largest capacitor at the non - inverting terminal is connected to GND, and the lower plate of the largest capacitor at the inverting input terminal is connected to V ref , otherwise, the lower plate of the largest capacitor at the non - inverting terminal is connected to V ref , and the lower plate of the largest capacitor at the inverting input terminal is connected to GND. This process is repeated until the lower plates of the lowest - order capacitors are determined.

9. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 8, wherein The operation method of a high - order capacitor array with progressive redundant capacitors includes: initially, the lower plates of all high - order capacitors are connected to the common - mode voltage V cm , the upper plates sample the input signal, wait for each bit of the comparator to complete the comparison before switching, starting from the highest - order capacitor in sequence. If V ip >V in , then the lower plate of the largest capacitor at the non - inverting terminal is connected to GND, and the lower plate of the largest capacitor at the inverting input terminal is connected to V ref , otherwise, the lower plate of the largest capacitor at the non - inverting terminal is connected to V ref , and the lower plate of the largest capacitor at the inverting input terminal is connected to GND. This process is repeated until the lower plates of the lowest - order capacitors are determined.

10. A capacitive fully differential two-stage digital-to-analog converter with progressive fault tolerance according to claim 9, characterized in that, The calculation methods for the ground capacitance and the bridging capacitance include: Step signals with an amplitude of V are input at two access points, and the changes in the CDAC output V are respectively: R o ​​ Where: C Mt is the total capacitance value of the high capacitors, C Lt is the total capacitance value of the low capacitors, and i is the number of bits of the ADC; X = C Mt (C a + C Lt ) + C a C Lt To maintain the correct weights and ensure the linearity of the ADC, it is necessary to have: dV o1 = 2dV o2 Therefore Thus where C u is the unit capacitance.

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