Test system for realizing function test of Ethernet PHY chip

Abstract

The invention relates to a test system for realizing a function test of an Ethernet PHY (Physical Layer) chip, belongs to the technical field of Ethernet transceiver test, and solves the problem of lack of an Ethernet PHY chip test mode in the prior art. The test system comprises an ATE test board, an FPGA (Field Programmable Gate Array) and a to-be-tested PHY (Physical Layer) chip, the ATE test board stores test data and a test instruction of the function test of each Ethernet protocol of the PHY chip to be tested; the FPGA is used for converting test data into a first data frame based on a test instruction of an Ethernet protocol, and controlling the first data frame to communicate between the PHY chip to be tested and the PHY chip to be tested; analyzing a second data frame returned to the FPGA by the PHY chip to be tested and the PHY chip to be tested to obtain a test observation signal of a corresponding Ethernet protocol; and the ATE test board is also used for judging whether the function test of the corresponding Ethernet protocol is passed or not based on the test observation signal of the corresponding Ethernet protocol.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet transceiver testing, and in particular, to a test system for realizing the functional testing of Ethernet PHY chips. Background Art

[0002] In terms of the functional performance detection of Ethernet PHY chips, the performance detection of such devices abroad is carried out in the manufacturing plants. The manufacturing plants use forward testing methods for testing Ethernet PHY chips, that is, during the device design process, the test code has been generated, and each model of device has its corresponding test program, which can perform complete testing on its various performances. Domestic manufacturing plants also use forward testing methods to verify the functional performance of Ethernet PHY, but due to considerations regarding intellectual property protection, the forward test vectors are not made public. Due to the complexity of the Ethernet protocol and the high data transmission rate of the chips, domestic reliability institutions have always lacked the ability to test and screen Ethernet PHY chips, resulting in the Ethernet PHY chips always being in a state where they cannot be screened.

[0003] The reliability of data transmission is related to the stability of the entire system. Ethernet chips have been favored by various systems due to their characteristics such as high speed, high reliability, and long-distance transmission, and their usage in systems has gradually increased in recent years. However, due to problems such as the complex protocol and fast transceiver speed of Ethernet PHY chips, they have always been in a state where they cannot be screened and can only be directly installed in the machine and tested with the entire machine for system experiments, bringing uncertain factors to the system.

[0004] Considering that the quality grades of imported Ethernet PHY devices are all industrial grade or commercial grade, the procurement channels cannot be guaranteed, and at the same time, the quality of imported chips is uneven, the application consistency and reliability of domestic Ethernet PHY chips need to be further considered. Coupled with the complex communication protocol, diverse working modes of Ethernet PHY chips, as well as the increasing usage and the demand for domestic substitution year by year; researching the Ethernet chip protocol, building the Ethernet PHY chip testing ability based on user requirements, and comparing the differences between imported devices and domestic chips has become an urgent issue. Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a test system for realizing the functional testing of Ethernet PHY chips to solve the problem of the lack of Ethernet PHY chip testing methods in the prior art.

[0006] The present invention discloses a test system for realizing the functional testing of Ethernet PHY chips, and the test system includes: an ATE test bench, an FPGA, and a PHY chip for cross-testing; wherein,

[0007] The ATE test bench is used to store the test data and test instructions for the functional test of each Ethernet protocol of the PHY chip to be tested.

[0008] The FPGA is used to, when performing the functional test of each Ethernet protocol of the PHY chip to be tested, load the controller IP core of the corresponding Ethernet protocol based on the test instructions of the corresponding Ethernet protocol; and use the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, control the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip to be tested and the PHY chip for counter - testing; and also parse the second data frame returned by the PHY chip to be tested and the PHY chip for counter - testing to the FPGA to obtain the test observation signal of the corresponding Ethernet protocol.

[0009] The ATE test bench also determines whether the functional test of the corresponding Ethernet protocol passes based on the test observation signal of the corresponding Ethernet protocol.

[0010] On the basis of the above - mentioned solution, the present invention has also made the following improvements:

[0011] Further, the test system further includes a control decoder and a configuration memory corresponding to each Ethernet protocol; wherein,

[0012] The control decoder is used to receive the test instructions of the Ethernet protocol sent by the ATE test bench to generate the control instructions for the configuration memory corresponding to the corresponding Ethernet protocol.

[0013] The configuration memory, based on the control instructions, selects the controller IP core of the corresponding Ethernet protocol for the FPGA to load.

[0014] Further, the test system further includes a relay control module;

[0015] The controller IP core of the Ethernet protocol includes the control logic of the corresponding Ethernet protocol, and the control logic includes the pin connection mode between the FPGA and the PHY chip to be tested.

[0016] The relay control module is used to, when performing the functional test of each Ethernet protocol of the PHY chip to be tested, control the switching of the pin connection or disconnection between the PHY chip to be tested and the FPGA according to the controller IP core of the corresponding Ethernet protocol.

[0017] Further, the test system further includes a system clock;

[0018] The system clock is used to provide clock signals for the FPGA, the PHY chip to be tested, and the PHY chip for counter - testing.

[0019] Further, the test system further includes a test adapter; in the test system, the FPGA, the PHY chip for paired testing, the control decoder, the configuration memory corresponding to each Ethernet protocol, the relay control module, the system clock, and the test adapter are all arranged on the test board; among them,

[0020] The PHY chip for paired testing is directly soldered on the test board;

[0021] The PHY chip to be tested is fixed on the test board in a screwing manner through the test adapter;

[0022] The communication pins of the MAC layer of the PHY chip for paired testing are directly connected to the FPGA, and the communication ports of the PHY chip for paired testing and the PHY chip to be tested are butted after signal conditioning through a high-speed Ethernet transformer.

[0023] Further, in the FPGA, the first data frame of the Ethernet protocol is obtained by performing the following operations:

[0024] Based on the loaded controller IP core of the Ethernet protocol, the FPGA generates two identical MAC controllers corresponding to the Ethernet protocol; among them, one MAC controller is responsible for communicating with the PHY chip to be tested, and the other MAC controller is responsible for communicating with the PHY chip for paired testing;

[0025] The two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert them into the first data frame of the corresponding Ethernet protocol; and send the first data frame of the corresponding Ethernet protocol to the PHY chip to be tested or the PHY chip for paired testing connected by communication.

[0026] Further, the PHY chip to be tested and the PHY chip for paired testing obtain the second data frame by performing the following operations:

[0027] After the PHY chip to be tested and the PHY chip for paired testing respectively pass the verification of the received first data frame, they send the first data frame to the other party at a preset data transmission rate;

[0028] After both parties receive the first data frame and pass the verification, they convert the first data frame into a data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame.

[0029] Further, in the FPGA,

[0030] The receive FIFO is used to receive the test data of the corresponding Ethernet protocol from the ATE test bench;

[0031] The transmit FIFO is used to store the data obtained by parsing the second data frame as the test observation signal of the corresponding Ethernet protocol.

[0032] Further, the ATE test bench determines whether the functional test of the Ethernet protocol passes by performing the following operations:

[0033] The ATE test bench sends a read valid signal and a read clock to the FPGA, and reads the test observation signals in the transmit FIFO of the FPGA;

[0034] The ATE test bench compares the test data of the corresponding Ethernet protocol with the test observation signals. If they are consistent, the functional test of the corresponding Ethernet protocol passes; otherwise, the functional test of the corresponding Ethernet protocol fails.

[0035] Further, each functional test selects one Ethernet protocol from GMII\MII\RGMII\TBI\RTBI\SGMII and one data transmission rate from 10 / 100 / 1000BASE T to cooperate for data transmission.

[0036] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0037] The test system for realizing the functional test of the Ethernet PHY chip provided by the present invention enables the IP cores of different Ethernet protocols to be loaded into the FPGA time-sharing by using the ATE test bench to control the decoder, and increases the Ethernet data frame transmission during the test process in cooperation with the PHY chip under test. Finally, the full-process one-key test controlled by the ATE is realized. After receiving the data sent by the ATE, the FPGA can automatically generate an Ethernet data frame, calculate the cyclic redundancy check code automatically after modifying the data, and does not need to parse the Ethernet protocol, avoiding writing the complex protocol back to the test PATTERN by hand, which facilitates the debugging of the test development process.

[0038] In the present invention, the above technical solutions can also be combined with each other to realize more preferred combination schemes. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can be made obvious from the description, or understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained from the content specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings are only for the purpose of showing specific embodiments and are not considered as limiting the present invention. Throughout the drawings, the same reference signs denote the same components;

[0040] Figure 1 is a schematic structural diagram of a test system for realizing the functional test of an Ethernet PHY chip;

[0041] Figure 2 is a schematic structural diagram of the MAC layer communication path in the test system for the functional test of the Ethernet PHY chip;

[0042] Figure 3 Schematic diagram of the structure of the PHY communication path in the test system for the functional test of the Ethernet PHY chip;

[0043] Figure 4 Logic resource block diagram of the test board in the test system for the functional test of the Ethernet PHY chip;

[0044] Figure 5 Schematic diagram of the connection method of the GMII interfaces of the PHY chip under test and the countermeasure PHY chip to the communication pins of the MAC layer of the FPGA;

[0045] Figure 6 Internal logic schematic diagram of the core FPGA GMII IP core;

[0046] Figure 7 Schematic diagram of the connection method of the MII interfaces of the PHY chip under test and the countermeasure PHY chip to the communication pins of the MAC layer of the FPGA;

[0047] Figure 8 Internal logic schematic diagram of the core FPGA MII IP core;

[0048] Figure 9 Schematic diagram of the connection method of the RGMII interfaces of the PHY chip under test and the countermeasure PHY chip to the communication pins of the MAC layer of the FPGA;

[0049] Figure 10 Internal logic schematic diagram of the core FPGA RGMII IP core;

[0050] Figure 11 Schematic diagram of the connection method of the TBI interfaces of the PHY chip under test and the countermeasure PHY chip to the communication pins of the MAC layer of the FPGA;

[0051] Figure 12 Internal logic schematic diagram of the core FPGA TBI IP core;

[0052] Figure 13 Schematic diagram of the connection method of the RTBI interfaces of the PHY chip under test and the countermeasure PHY chip to the communication pins of the MAC layer of the FPGA;

[0053] Figure 14 Internal logic schematic diagram of the core FPGA RTBI IP core;

[0054] Figure 15 Schematic diagram of the connection method of the SGMII interfaces of the PHY chip under test and the countermeasure PHY chip to the MAC layer of the FPGA;

[0055] Figure 16 Internal logic schematic diagram of the core FPGA SGMII IP core;

[0056] Figure 17 Internal logic schematic diagram of the core FPGA GMII (TO FIBER) IP core. Specific implementation mode

[0057] The preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0058] First, the Ethernet communication protocol is introduced as follows. The Ethernet PHY chip supports Gigabit Media Independent Interface (GMII), Reduced GMII (RGMII), Serial Gigabit Media Independent Interface (SGMII), Ten-bit Interface (TBI), and Reduced TBI (RTBI) for direct connection to the MAC / switch interface. The Ethernet protocol frame between the MAC and the PHY is shown in Table 1 below, including seven parts: preamble, start frame delimiter, destination address, source address, length, data and payload, and CRC check.

[0059] Table 1 Thumbnail of Ethernet MAC layer protocol frame

[0060]

[0061] The preamble consists of 7 bytes of 10101010. The start frame delimiter indicates the start of a frame, and the symbol sequence is 10101011. The source address and the destination address are each 48 bits. The highest bit indicates whether it is a single address or a multi-address. 0 indicates a single address, and 1 indicates a multi-address. The highest bit of the source address is reserved and set to 0. The second highest bit indicates whether it is a local management address or a global management address. 0 indicates a global management address, and 1 indicates a local management address. If the broadcast mode is adopted, this bit is set to 1. The length indicates the number of bytes of MAC data or the type of MAC client protocol. The data field has a length of 46 - 1500 Byte. If it is less than 46 Byte, it is automatically padded with 0 to make up. The frame check uses a 32-bit cyclic redundancy check code to check all contents from the destination address to the data field.

[0062] During the testing process of the Ethernet PHY chip, since the data length and the specific content of the data will change, and each time it changes, it is necessary to recalculate the cyclic redundancy check code. The cyclic redundancy check code can be calculated by writing script software and written back to the test PATTERN of the test system according to the timing according to different protocol formats. Thus, the capacity of the entire Ethernet protocol is large, and the amount of calculation of the cyclic redundancy check code is very large, resulting in great difficulty in writing the test PATTERN. Even if 1 bit is incorrect, it will cause the communication between the MAC and the PHY chip to fail, and manually calculating using the algorithm causes great trouble for subsequent debugging.

[0063] In order to avoid repeatedly parsing complex communication protocols during the test development process, this embodiment provides the following test system for realizing the functional test of the Ethernet PHY chip to solve the above problems existing in the testing process of the Ethernet PHY chip.

[0064] In this embodiment, the structural schematic diagram of the test system for realizing the functional test of the Ethernet PHY chip is as Figure 1 shown. The test system includes: an ATE test bench, an FPGA, and a PHY chip under test. Among them, the ATE test bench is used to store the test data and test instructions for each functional test of the Ethernet protocol of the PHY chip under test; the FPGA is used to load the controller IP core of the corresponding Ethernet protocol based on the test instructions of the corresponding Ethernet protocol when performing each functional test of the Ethernet protocol of the PHY chip under test; and use the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and control the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip under test and the PHY chip for countermeasure; and also parse the second data frame returned by the PHY chip under test and the PHY chip for countermeasure to the FPGA to obtain the test observation signal of the corresponding Ethernet protocol.

[0065] The ATE test bench also judges whether the functional test of the corresponding Ethernet protocol passes based on the test observation signal of the corresponding Ethernet protocol.

[0066] Preferably, the test system further includes a control decoder and a configuration memory corresponding to each Ethernet protocol. Among them, the control decoder is used to receive the test instructions of the Ethernet protocol sent by the ATE test bench to generate control instructions for the configuration memory corresponding to the corresponding Ethernet protocol; the configuration memory, based on the control instructions, selects the controller IP core of the corresponding Ethernet protocol for the FPGA to load.

[0067] Preferably, the test system further includes a relay control module; the controller IP core of the Ethernet protocol includes the control logic of the corresponding Ethernet protocol, and the control logic includes the pin connection mode between the FPGA and the PHY chip under test; at this time, the relay control module is used to control the switching of the pins between the PHY chip under test and the FPGA in connection or disconnection according to the controller IP core of the corresponding Ethernet protocol when performing each function test of the Ethernet protocol of the PHY chip under test.

[0068] In addition, the test system further includes a system clock and a power conversion chip. Among them, the system clock is used to provide clock signals for the FPGA, the PHY chip under test, and the PHY chip for testing.

[0069] The power conversion chip is used to supply power to the test system.

[0070] In the test system of the Ethernet PHY chip provided in this embodiment, the FPGA, the PHY chip for testing, the control decoder, the configuration memory, the relay control module, the system clock, and the power conversion chip are all arranged on the test board.

[0071] Next, the overall technical concept of the test system for the Ethernet PHY chip provided in this embodiment will be described as follows: All devices on the test board are directly powered by the ATE test bench or powered by the ATE through a power conversion chip. For the normal data transmission of the PHY chip under test, a LINK relationship needs to be established with the PHY chip for paired testing. Therefore, in the test system provided in this embodiment, the content of paired testing with the PHY chip for paired testing is added. The FPGA is responsible for receiving the test data from the ATE test bench, converting the test data into data frames in the corresponding Ethernet protocol (i.e., the "first data frame" described above), and performing protocol transceiver between the MAC controller, the PHY chip under test, and the PHY chip for paired testing. The test process needs to cover multiple Ethernet protocol formats such as GMII\MII\RGMII\TBI\RTBI\SGMII. Each Ethernet protocol format requires a different controller IP core for scheduling and control. Therefore, in the test system provided in this embodiment, a control decoder is added. Different control instructions select different configuration memories for the FPGA to load the controller IP cores of different protocols. During the functional test of the Ethernet protocol, the communication pins of the PHY chip under test are connected to the IO pins of the FPGA and the PHY chip for paired testing through the relay control module, and the ATE test bench does not directly participate in the communication. In addition, the test system may further include a JTAG interface, which is used to load the controller IP cores of different Ethernet protocols into the FPGA during the debugging process. The relay control module is also used to control the switching of the connection or disconnection between the pins of the PHY chip under test and the digital channels of the ATE test bench. During the parameter test, the connection relationship between the FPGA and the PHY chip under test is released, and the PHY chip under test is directly connected to the ATE to implement input / output parameter testing. By switching the pin connection mode of the PHY chip under test through the relay control module, the parameter coverage testing of the PHY chip under test is realized. That is, the parameter test of the PHY chip under test is directly controlled by the ATE test bench: the ATE test bench directly sends the test data for the corresponding parameter test to the PHY chip under test and collects the test observation signals feedback by the PHY chip under test for the corresponding parameter test; the ATE test bench judges whether the corresponding parameter test passes based on the test observation signals of the corresponding parameter test. It should be emphasized that before the parameter test, the ATE test bench configures the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode. So as to collect the test observation signals feedback by the PHY chip under test.

[0072] In the test system provided in this embodiment, the receiving FIFO of the FPGA is used to receive test data of the corresponding Ethernet protocol from the ATE test bench. The FPGA generates two identical MAC controllers based on the loaded controller IP core of the Ethernet protocol. Among them, one MAC controller is responsible for communicating with the PHY chip under test, and the other MAC controller is responsible for communicating with the countermeasure PHY chip. The two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert it into the first data frame of the corresponding Ethernet protocol, and send the first data frame of the corresponding Ethernet protocol to the PHY chip under test or the countermeasure PHY chip connected by communication. After the PHY chip under test and the countermeasure PHY chip respectively verify the received first data frame, they send the first data frame to each other at the preset data transmission rate. After both parties receive the first data frame and verify it, they convert the first data frame into a data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame. The sending FIFO is used to store the data after parsing the second data frame as the test observation signal of the corresponding Ethernet protocol. The ATE test bench sends a read valid signal and a read clock to the FPGA to read the test observation signal in the sending FIFO of the FPGA. The ATE test bench compares the test data and the test observation signal of the corresponding Ethernet protocol. If they are consistent, the function test of the corresponding Ethernet protocol passes; otherwise, the function test of the corresponding Ethernet protocol fails. That is, after the FPGA receives the test data sent by the ATE, the two MAC controllers respectively automatically calculate the cyclic redundancy check code according to the current Ethernet protocol and generate a data frame of the corresponding Ethernet protocol (i.e., the "first data frame"), without the need to parse the Ethernet protocol, avoiding writing complex protocols back to the test PATTERN by hand and facilitating the debugging of the test development process. Using multiple configuration memories for multiple repeated loadings during the test process enables the realization of one-key testing for multiple different Ethernet protocol formats. During the test process, the low-speed data signal of the ATE is protocol-packed through the FPGA, and high-speed transceiver is performed between the PHY chip under test and the countermeasure PHY chip. After full-duplex communication, the FPGA retrieves the data frames ("second data frames") of the PHY chip under test and the countermeasure PHY chip and performs data unpacking. Finally, the data after parsing by the FPGA is returned to the ATE as a test observation signal for judgment and comparison, realizing the test of low-speed devices for high-speed chips. The entire test scheme has the advantages and characteristics of strong innovation, good practicability, high completeness, etc.

[0073] Specifically, the design scheme on the test board in the test system can also be disassembled into Figure 2 and Figure 3 shown in two parts. Among them, Figure 2 represents the structural schematic diagram of the MAC layer communication path in the test system of the Ethernet PHY chip, Figure 3Schematic diagram of the PHY communication path in the test system of the Ethernet PHY chip. The above two figures are actually integrated on a test board. Since the MAC layer and the PHY communication path are different, two figures are used for distinction. The PHY belongs to the physical layer; the MAC belongs to the data link layer and is mainly responsible for controlling and connecting the physical medium of the physical layer.

[0074] The logical resource block diagram of the test board in the test system of the Ethernet PHY chip is as Figure 4 shown. In order to complete the combined function test and DC parameter test of multiple Ethernet protocols for the PHY chip under test, the test board includes a test adapter (for carrying the PHY chip under test), a countermeasure PHY chip, an FPGA, a power conversion chip, a system clock, a relay control module, a configuration memory, a JTAG interface, an optical fiber interface, and a manual reset, etc. Next, the main devices in the test system are introduced as follows.

[0075] (1) Power supply part

[0076] All devices on the test board require working voltages of 1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, etc. to work properly. For the convenience of debugging and subsequent normalization management and use, in this embodiment, a power conversion chip is made, which can realize voltage conversion from 5V to all the above voltages. The 5V power supply input comes from the 5V DC source of the ATE test bench and the external port respectively: during the offline debugging process, the 5V power supply is connected by an external voltage regulator to supply power to all devices on the test board, and the test board can realize offline debugging and work away from the ATE test bench; during the debugging process of the ATE test bench, the physical connection between the PHY chip under test and the power conversion chip is manually disconnected, and the digital channels of the ATE test bench are used to supply power to the AVDD, CVDD, and DVDD of the PHY chip under test, which is convenient for measuring the power consumption of the PHY chip under test during the test process. The other devices on the test board are still powered by the power conversion chip.

[0077] (2) System clock

[0078] In this embodiment, the system clock is an Ethernet clock generator. Exemplarily, the Ethernet clock generator selects AD9571. In the specific implementation process, a 25M active crystal oscillator is selected as the clock reference for the clock input of AD9571, and the working reference clocks of the FPGA, the PHY chip under test, and the countermeasure PHY chip are all generated by AD9571.

[0079] Exemplarily, the 125M and 100M clock references generated by the AD9571 are output to the clock buffer (such as the LMK1D1024). The FPGA controls the 2-to-1 selection of the clock reference to use 100M or 125M, and finally outputs it as a clock synchronization signal to the GTX module of the FPGA, the PHY chip under test, and the SGMII interface of the countermeasure PHY chip.

[0080] (3) FPGA (including configuration memory and control part)

[0081] The FPGA is the core device for implementing the test function in this embodiment. The communication protocols of the PHY chip under test and the countermeasure PHY chip are both configured by the FPGA. The FPGA packs the test data sent by the ATE test bench into data frames corresponding to the Ethernet protocol through the built-in MAC controller, and sends the data frames of the Ethernet protocol (i.e., the "first data frames") to the PHY chip under test and the countermeasure PHY chip through the MAC layer. Subsequently, it receives the data frames (i.e., the "second data frames") sent by the full-duplex PHY chip under test and the countermeasure PHY chip, unpacks the data frames (i.e., the "second data frames"), and sends the parsed data (test observation signals) back to the ATE through the IO interface for comparison.

[0082] During the test process, multiple Ethernet protocol formats are involved, and the FPGA needs to load the controller IP cores of different Ethernet protocols multiple times in a time-sharing manner to implement MAC controllers of different protocols. Set the configuration pins M[2:0] of the FPGA to 001, and the configuration method is the main MASTER SPI. Exemplarily, in this embodiment, 8 configuration memories are set to store the controller IP cores of different Ethernet protocols respectively. The 8 configuration memories are selected by the control decoder. The ATE test bench controls the 3-way chip select signals A0, A1, and A2 of the control decoder to determine which configuration memory the FPGA starts from. After the FPGA is powered on, it automatically loads the corresponding Ethernet protocol controller IP core from the selected configuration memory. The IO ports of the FPGA are respectively connected to the PHY chip under test and the countermeasure PHY chip under test, mainly including all data ports for data transmission between the MAC layer and the PHY. In the specific implementation process, the control core preferably uses a high-performance FPGA with a GTX high-speed SEEDS interface, and the actual FPGA model selected is XC7K325T-FFG900I.

[0083] (4) PHY chip under test and countermeasure PHY chip (including relay control part)

[0084] The actual package sizes of the reference PHY chip and the PHY chip under test are the same. During the test, the reference PHY chip is directly soldered onto the test board. To enable the testing of different PHY chips under test, the PHY chip under test is fixed to the test board by screwing via a test adapter.

[0085] The communication pins of the MAC layer of the reference PHY chip are directly connected to the FPGA. The reference PHY chip is directly powered by a power conversion chip. The communication ports MDI[3:0] of the reference PHY chip and the PHY chip under test are connected after signal conditioning through a high-speed Ethernet transformer.

[0086] The communication pins of the MAC layer of the PHY chip under test are not directly connected to the FPGA, nor are the power pins directly connected to the digital channels of the ATE test bench or the power conversion chip; the pins of the PHY chip under test are controlled by a relay control module. According to the current test item (functional test or parameter test), the communication pins are selected to be connected to the FPGA or the digital channels of the ATE test bench. The power pins are connected manually and are powered by the power conversion chip during offline debugging. The ATE test bench also stores the test instructions for each parameter test of the PHY chip under test, and the test instructions for the parameter test are used to configure the connection method between the ATE test bench for each parameter test and the pins of the PHY chip under test; the relay control module is used to control the switching of the connection or disconnection of the pins between the PHY chip under test and the ATE test bench according to the test instructions for the parameter test when performing the parameter test of the PHY chip under test. Specifically, when the ATE test bench performs the parameter test, it is powered by the ATE test bench and the power consumption current is tested in real time. A relay control module is selected to switch the pins of the PHY chip under test to control the switching of the connection or disconnection between the PHY chip under test and the ATE test bench. On the one hand, it is convenient to test the pin connection of the PHY chip under test; on the other hand, for protocol parsing, the PHY chip under test can directly communicate with the ATE test bench to perform the input and output level tests.

[0087] (5) Hardware configuration part

[0088] The PHY chip under test and the reference PHY chip allow the working mode to be set through the Config[6:0] pins, including physical address, PHY operation mode, auto-negotiation, and MID crossover configuration. These can all be achieved through hardware configuration, thus avoiding direct access to internal registers. The registers for hardware configuration can be modified and overwritten through MDIO.

[0089] Table 2 LED corresponding hardware control codes

[0090] Pin Bit[2:0] VDDO 111 LED_LINK1D 110 LED_LINIK100 101 LED_LINK1000 100 LED_DUPLEX 011 LED_RX 010 LED_TX 001 VSS 000

[0091] Registers corresponding to the CONFIG signal in Table 3

[0092] Pin Bit[2] Bit[1] Bit[0] CONFIG0 <![CDATA[PHYADR[2] 1 > <![CDATA[PHYADR[1] 1 > <![CDATA[PHYADR[0] 1 > CONFIG1 ENA_PAUSE <![CDATA[PHYADR[4] 1 > <![CDATA[PHYADR[3] 1 > CONFIG2 ANEG[3] ANEG[2] ANEG[1] CONFIG3 ANEG[0] ENA_XC DIS_125 CONFIG4 HWCFG_MODE[2] HWCFG_MODE[1] HWCFG_MODE[0] CONFIG5 DIS_FC DIS_SLEEP HWCFG_MODE[3] CONFIG6 SEL_TWSI INT_POL 75 / 50 OHM

[0093] The PHY chip under test maps the common mode registers to Config[6:0] (Table 3), and at the same time assigns values to the LED hardware control codes (Table 2). Table 4 shows the register configuration information corresponding to different working modes. As can be seen from Table 3, the hardware configuration of the registers in Table 4 can be completed through CONFIG4 and CONFIG5. The test process in this embodiment mainly involves the HWCFG MODE[3:0] bits of the registers.

[0094] Register settings corresponding to different working modes in Table 4

[0095]

[0096] During the test process, CONFIG4 and CONFIG5 are respectively connected to the control decoder, and the three inputs of the controller decoder are controlled through the IO pins of the FPGA to ensure that CONFIG is connected to one of the LEDs, thus completing the assignment of the LED hardware control code in Table 2 to CONFIG, and thus realizing the assignment of the HWCFG MODE[3:0] of the register, and realizing the hardware setting of the working modes of the PHY chip under test and the PHY chip under test.

[0097] In addition to the above-discussed content, the test board also includes a fiber optic interface, which is mainly used for data transmission of fiber optic communication (FIBER itself is optical communication, and SGMII and FIBER share a high-speed differential interface, so time-division multiplexing needs to be performed through a relay control module); a JTAG interface, which is used for real-time configuration of the FPGA during the debugging process and for solidifying the configuration memory at the FPGA end. After the debugging is completed, this interface is not used during the actual test process. The test system can also include a manual reset port, which is used for resetting the FPGA during the debugging process. There are also other buffers, which are used for signal isolation and buffering, and will not be elaborated here.

[0098] For the entire data transmission process of the PHY chip under test, a complete communication link between the MAC and the PHY, as well as a complete LINK relationship between the PHY chip under test and the countermeasure PHY chip are required. A functional test will select one of SGMII / GMII / MII / RGMII / TBI / RTBI and one of 10 / 100 / 1000BASE T to cooperate for data transmission. During the actual test process, the COPPER side communicates at the highest test rate allowed by the protocol. The following 7 MAC layer IP cores (i.e., "controller IP cores") are required for test scheduling and transmission. The specific control port configurations are as shown in Table 5 below:

[0099] Table 5 Correspondence between Control Terminals and MAC Layer IP Cores

[0100] Serial number Control terminal (A[2:0]) MAC layer protocol 1 000 GMII TO COPPER(1000BASET) 2 001 MII TO COPPER(10BASET) 3 010 RGMII TO COPPER(1000BASET) 4 011 TBI TO COPPER(1000BASET) 5 100 RTBI TO COPPER(1000BASET) 6 101 SGMII TO COPPER(1000BASET) 7 110 FIBER TO COPPER(1000BASET)

[0101] 1. GMII TO COPPER Protocol Transmission

[0102] (1) Protocol Summary

[0103] GMII (Gigabit Media Independant Interface), a gigabit MII interface. GMII uses 8-bit interface data, with a working frequency of 125MHZ and a data transmission speed of up to 1000Mbps. It is also compatible with the 10 / 100Mbps working mode specified by MII. The GMII interface data structure conforms to the IEEE Ethernet standard. The schematic diagram of the connection method between the GMII interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 5 shown.

[0104] (2) Test Implementation

[0105] Install the test board on the ATE test bench, turn on the power-on button of the power conversion chip, and power on all other devices on the test board except the PHY chip under test through the power conversion chip. Start the test. The digital channel of the ATE test bench provides the voltage required for the normal operation of the PHY chip under test, and the PHY chip under test is powered on. Use the test vector to set the configuration pins A[2:0] of the control decoder to 000 according to Table 4, and the FPGA loads the GMII controller IP core from the 0th configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the countermeasure PHY chip through the IO pins. Set HWCFG MODE[3:0] to 1111, and then send a reset signal. The PHY chip under test and the countermeasure PHY chip start to reset and respectively collect their own hardware configuration information, and then perform handshake and auto-negotiation. It should be noted that the hardware configuration information of the PHY chip under test and the countermeasure PHY chip is kept consistent to ensure mutual communication.

[0106] From the start of the test until the handshake is successful, the ATE test bench keeps waiting through the test pattern. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that both the PHY chip under test and the countermeasure PHY chip can complete the handshake successfully. After the waiting ends, the ATE test bench sends test data to specific IO ports of the FPGA (ports written and agreed upon inside the FPGA for observing the FPGA output) through the test pattern. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in GMII format and sends this first data frame to both the PHY chip under test and the countermeasure PHY chip respectively. After receiving the first data frame in GMII format, and after verifying the integrity of the first data frame, the PHY chip under test and the countermeasure PHY chip send the first data frame to each other through the MDI[3:0] interface using the data transmission rate of 1000BASE T. After receiving the first data frame, both sides verify whether the first data frame is intact, and then convert the first data frame into a data frame in GMII format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in GMII format sent by the PHY chip under test and the countermeasure PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the GMII protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the parsed data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0107] (3) Programming idea of the controller IP core

[0108] The GMII controller IP core mainly includes five parts: a receive FIFO, a transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, and control logic (placed inside the controller IP core). Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the GMII-1000BASE T method, send a reset signal, and control the acquisition of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can recognize the write valid signal of the ATE test bench and read and store the test data in the receive FIFO driven by the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers pack the test data and finally form data frames in GMII format for the PHY chip under test and the countermeasure PHY chip. The data frames in GMII format are sent through the physical interfaces of the MAC and PHY. Figure 6Internal logic schematic diagram of the core FPGA GMII IP core.

[0109] The PHY chip under test and the paired PHY chip simultaneously receive data frames in GMII format from the MAC layer and perform full-duplex communication at a data transfer rate of 1000BASE-T; two MAC controllers respectively receive the data frames in GMII format from the PHY chip under test and the paired PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO of the FPGA. The transmit FIFO drives the data back to the ATE test bench for comparison under the ATE read signal; the actually received data should be exactly the same as the transmitted data. If the comparison is successful, it proves that the GMII-1000BASE-T link of the PHY chip under test and the paired PHY chip is intact and meets the requirements of the data manual.

[0110] 2. MII TO COPPER protocol transmission

[0111] (1) Protocol brief

[0112] MII, that is, Media Independent Interface, also called Medium Independent Interface. It is an Ethernet industry standard defined by IEEE-802.3. It includes a 4-bit data interface and a management interface between the MAC and the PHY. The data interface is used for two independent channels for the transmitter and the receiver respectively. Each channel has its own data, clock, and control signals. MII transmits data bidirectionally in 4-bit nibble mode, with a clock rate of 25MHZ, and its operating speed can reach 100Mb / s. When the clock rate is 2.5MHZ, the corresponding speed is 10Mb / s. Although the MII interface is flexible, due to the limitation of the transceiver rate, it has been gradually replaced by GMII. The schematic diagram of the connection method between the MII interfaces of the PHY chip under test and the paired PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 7 shown. Compared with GMII, the MII interface only reduces the data bits from 8 bits to 4 bits, and other control bits and working modes remain unchanged.

[0113] (2) Test implementation

[0114] Start the test. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to work properly, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 001 according to Table 4 using the test vector. The FPGA loads the MII controller IP core from the first configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Set HWCFG MODE[3:0] to 1111, i.e., the GMII-COPPER mode. Then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshaking and auto-negotiation. Assign the register with address 4 the value 0041 to configure the data transfer rate to 10M and convert the GMII protocol to the MII protocol; assign the register with address 0 the value 8000, and the PHY chip under test and the paired PHY chip start a soft reset and perform handshaking and auto-negotiation again.

[0115] From the start of the test until the handshake is successful, the ATE keeps waiting through the test PATTERN, and a fixed waiting time is obtained through multiple tests. This time needs to ensure that both the PHY chip under test and the paired PHY chip can succeed in handshaking. After the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in MII format and sends this first data frame to the PHY chip under test and the paired PHY chip respectively. After receiving the first data frame in MII format, and after verifying that the first data frame is intact, the PHY chip under test and the paired PHY chip send the first data frame to each other through the MDI[3:0] interface at the data transfer rate of 10BASE T. After both sides receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in MII format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in MII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the MII protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0116] (3) Programming idea of the controller IP core

[0117] The MII controller IP core mainly consists of six parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the paired PHY chip, control logic, and MDIO read / write. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the paired chip, inform the PHY chip under test and the paired PHY chip to communicate using the GMII-10BASE-T mode, send a reset signal, control the collection of hardware configuration information after the PHY chip under test and the paired PHY chip are reset, and ensure the effectiveness of the hardware configuration; configure the memories of the PHY chip under test and the paired PHY chip through the MDIO interface, modify the GMII format to the MII format, and at the same time initiate a soft reset and perform a PHY chip handshake again. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock; after the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers pack the test data and finally form the MII data frames of the PHY chip under test and the paired PHY chip. The MII data frames are sent through the physical interfaces of the MAC and PHY. Figure 8 It is the internal logic schematic diagram of the core FPGA MII IP core.

[0118] The PHY chip under test and the paired PHY chip simultaneously receive the MII format data frames at the MAC layer and perform full-duplex communication at the data transmission rate of 10BASE-T; the two MAC controllers respectively receive the MII format data frames of the PHY chip under test and the paired PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO of the FPGA. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal; the actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the MII-10BASE-T link of the PHY chip under test and the paired PHY chip is intact and meets the requirements of the data manual.

[0119] 3. RGMII TO COPPER Protocol Transmission

[0120] (1) Protocol Summary

[0121] RGMII (Reduced Gigabit Media Independant Interface), a reduced GMII interface. Compared with GMII, RGMII has the following characteristics: the transmit / receive data lines are changed from 8 to 4, TX_ER and TX_EN are multiplexed and transmitted through TX_CTL, RX_ER and RX_EN are multiplexed and transmitted through RX_CTL. Although the RGMII signal lines are halved, the TXC / RXC clock is still 125MHZ. To achieve a transmission rate of 1000Mbit, the TXD / RXD signal lines transmit / receive TXD[3:0] / RXD[3:0] in the GMII interface at the rising edge of the clock and transmit / receive TXD[7:4] / RXD[7:4] at the falling edge of the clock. The schematic diagram of the connection method between the RGMII interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 9 shown. Compared with GMII, RGMII simplifies both the control signal and the data bit width. To ensure the data transmission rate, the DDR method is used for data transmission to achieve the same data transmission rate as GMII.

[0122] (2) Test implementation

[0123] Start the test. The digital channel of the ATE test bench provides the voltage required for the normal operation of the PHY chip under test, and the PHY chip under test is powered on. Use the test vector to set the configuration pins A[2:0] of the control decoder to 010 according to Table 4, and the FPGA loads the RGMII controller IP core from the second configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the countermeasure PHY chip through the IO pins. Specifically: assign the control code 011 of the LED_DUPLEX signal to CONFIG4 of the PHY chip under test and the countermeasure PHY chip through the control decoder TMUX1308; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5 of the PHY chip under test and the countermeasure PHY chip; through the above hardware configuration, the register HWCFGMODE[3:0] is set to 1011, corresponding to the RGMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the countermeasure PHY chip start to reset and collect the hardware configuration information, and then perform handshaking and auto-negotiation.

[0124] From the start of the test until the handshake is successful, the ATE keeps waiting through the test pattern. After multiple tests, a fixed waiting time is obtained, and this time needs to ensure that both the PHY chip under test and the paired PHY chip can complete the handshake successfully. After the waiting ends, the ATE sends test data to specific IO ports of the FPGA through the test pattern. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in RGMII format and sends this first data frame to both the PHY chip under test and the paired PHY chip respectively. After receiving the first data frame in RGMII format, and after verifying that the first data frame is intact, the PHY chip under test and the paired PHY chip send the first data frame to each other through the MDI[3:0] interface at the data transfer rate of 1000BASE T. After both sides receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in RGMII format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in RGMII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the RGMII protocol in the transmit FIFO. It waits for the read valid signal and read clock of the ATE test bench, and finally sends the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0125] (3) Programming ideas for the controller IP core

[0126] The RGMII controller IP core mainly includes five parts: the receive FIFO, the transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the paired PHY chip, and the control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the paired PHY chip, inform the PHY chip under test and the paired PHY chip to communicate using the RGMII-1000BASE T method, send the reset signal, and control the collection of hardware configuration information after the PHY chip under test and the paired PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read the test data into and store it in the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers pack the test data and finally form the RGMII data frames of the PHY chip under test and the paired PHY chip, and the data frames are sent through the physical interfaces of the MAC and PHY. Figure 10 Schematic diagram of the internal logic of the core FPGA RGMII IP core.

[0127] The PHY chip under test and the countermeasure PHY chip simultaneously receive data frames in RGMII format from the MAC layer and perform full-duplex communication at a data transfer rate of 1000BASE-T. Two MAC controllers respectively receive the data frames in RGMII format from the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transmit the parsed data back to the transmit FIFO. The transmit FIFO drives the data back to the ATE test bench under the ATE read signal for comparison. The actually received data should be exactly the same as the transmitted data. If the comparison is successful, it proves that the RGMII-1000BASE-T links of the PHY chip under test and the countermeasure PHY chip are intact and meet the requirements of the data manual.

[0128] 4. Transmission of TBI TO COPPER Protocol

[0129] (1) Protocol Overview

[0130] TBI (Ten Bit Interface), the interface data bit width is increased from 8 bits of the GMII interface to 10 bits. In fact, the difference between the TBI interface and the GMII interface is not significant. The extra 2 bits of data are mainly because: under the TBI interface, the MAC chip performs an 8B - 10B transformation before sending the data to the PHY chip. Due to the increase in the data bit width, the data transfer rate increases from 1000Mbps of the GMII interface to 1.25Gbps. The TBI interfaces of most chips are compatible with the GMII interface. When used as the TBI interface, CRS and COL are generally not used. The schematic diagram of the connection method between the TBI interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 11 shown.

[0131] (2) Test Implementation

[0132] Start the test. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 011 according to Table 4 using the test vector. The FPGA loads the TBI controller IP core from the 3rd configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 101 of the LED_LINK100 signal to CONFIG4; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 1101, corresponding to the TBI TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshake and auto-negotiation.

[0133] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN, and a fixed waiting time is obtained through multiple tests. This time needs to ensure that both the PHY chip under test and the paired PHY chip can handshake successfully; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in TBI format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively; after the PHY chip under test and the paired PHY chip receive the first data frame in TBI format and verify that the first data frame is intact, they send the data frame to each other through the MDI[3:0] interface at the data transfer rate of 1000BASE T; after both sides receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in TBI format and send it to the FPGA as the second data frame; the FPGA receives the second data frames in TBI format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data; and stores the parsed data as the test observation signal of the TBI protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0134] (3) Programming idea of the controller IP core

[0135] The controller IP core of TBI mainly includes five parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the countermeasure PHY chip, and a control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate in the TBI-1000BASE T mode, send a reset signal, and control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the TBI data frames of the PHY chip under test and the countermeasure PHY chip. The TBI data frames are sent through the physical interfaces of the MAC and PHY. Figure 12 It is the internal logic schematic diagram of the core FPGA TBI IP core.

[0136] The PHY chip under test and the countermeasure PHY chip simultaneously receive the TBI format data frames at the MAC layer and perform full-duplex communication at the data transfer rate of 1000BASE-T. The two MAC controllers respectively receive the TBI format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the TBI-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0137] 5. RTBI TO COPPER Protocol Transmission

[0138] (1) Protocol Overview

[0139] RTBI (Reduced Ten Bit Interface), that is, a simplified TBI interface, with an interface data width of 5 bits and a clock frequency of 125 MHZ. Sampling is performed twice at the rising and falling edges of the clock. Finally, the data transfer rate is the same as that of TBI, but the interface is further simplified. The schematic diagram of the connection method between the RTBI interfaces of the PHY chip under test and the countermeasure PHY chip and the communication pins of the MAC layer of the FPGA is as Figure 13 shown.

[0140] (2) Test Implementation

[0141] Start the test. The digital channels of the ATE test bench provide the voltages required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 100 according to Table 4 using the test vector. The FPGA loads the controller IP core of RTBI from the 4th configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG4; through another TMUX1308, assign the control code 001 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 1001, corresponding to the RTBI TO COPPER communication protocol mode in Table 4. Then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshaking and auto-negotiation.

[0142] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that both the PHY chip under test and the paired PHY chip can succeed in handshaking. After the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in RTBI format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively. After the PHY chip under test and the paired PHY chip receive the first data frame in RTBI format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at the data transfer rate of 1000BASE T. After both parties receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in RTBI format and send it to the FPGA as the second data frame. The FPGA receives the second data frames in RTBI format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frames to obtain the parsed data, and stores the parsed data as the test observation signal of the RTBI protocol in the transmit FIFO. Wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0143] (3) Programming idea of the controller IP core

[0144] The controller IP core of RTBI mainly consists of five parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the countermeasure PHY chip, and control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the RTBI-1000BASE T method, send a reset signal, and control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration; the receive FIFO is used to receive test data from the ATE test bench. It can identify the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock; after the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the RTBI data frames of the PHY chip under test and the countermeasure PHY chip. The RTBI data frames are sent through the physical interfaces of the MAC and PHY. Figure 14 It is the internal logic schematic diagram of the core FPGA RTBI IP core.

[0145] The PHY chip under test and the countermeasure PHY chip simultaneously receive the RTBI format data frames at the MAC layer and perform full-duplex communication at the data transfer rate of 1000BASE-T; the two MAC controllers respectively receive the RTBI format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal; the actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the RTBI-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0146] 6. SGMII TO COPPER Protocol Transmission

[0147] (1) Protocol Overview

[0148] SGMII, namely Serial GMII, performs data transceiver through the high-speed serial interfaces of the FPGA and the PHY. There is a pair of differential signal lines for each of the transceiver, with a clock frequency of 625MHZ and sampling at both the rising and falling edges of the clock signal. The schematic diagram of the connection method between the SGMII interfaces of the PHY chip under test and the countermeasure PHY chip and the MAC layer of the FPGA is as Figure 15 shown. SGMII simplifies the communication hardware through a high-speed data rate.

[0149] (2) Test Implementation

[0150] Start the test. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to work properly, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 101 according to Table 4 using the test vector. The FPGA loads the SGMII controller IP core from the 5th configuration memory. The FPGA configures the PHY chip under test and the CONFIG of the paired PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 000 of the VSS signal to CONFIG4; through another TMUX1308, assign the control code 000 of the LED_TX signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 0000, corresponding to the SGMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the paired PHY chip start to reset and collect hardware configuration information, and then perform handshaking and auto-negotiation.

[0151] From the start of the test until the handshake is successful, the ATE has been waiting through the test PATTERN. A fixed waiting time is obtained through multiple tests, and this time needs to ensure that both the PHY chip under test and the paired PHY chip can succeed in handshaking; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in SGMII format and sends the first data frame to the PHY chip under test and the paired PHY chip respectively through the high-speed serial interface; after the PHY chip under test and the paired PHY chip receive the first data frame in SGMII format and verify that the first data frame is intact, they send the first data frame to the other party through the MDI[3:0] interface at the data transfer rate of 1000BASE T; after both parties receive the first data frame, they verify whether the first data frame is intact, and then convert the first data frame into a data frame in SGMII format and send it to the FPGA as the second data frame through the high-speed serial transceiver interface; the FPGA receives the data frames in SGMII format sent by the PHY chip under test and the paired PHY chip respectively, parses the second data frame to obtain the parsed data; and stores the parsed data as the test observation signal of the SGMII protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0152] (3) Programming idea of the controller IP core

[0153] The SGMII controller IP core mainly consists of five parts: a receive FIFO, a transmit FIFO, a MAC controller for the PHY chip under test, a MAC controller for the countermeasure PHY chip, and control logic. The control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the SGMII-1000BASE T mode, send a reset signal, and control the acquisition of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can recognize the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form SGMII format data frames for the PHY chip under test and the countermeasure PHY chip. The data frames are sent through the physical interfaces of the MAC and PHY. Figure 16 Internal logic schematic diagram of the core FPGA SGMII IP core.

[0154] The PHY chip under test and the countermeasure PHY chip simultaneously receive SGMII format data frames at the MAC layer and perform full-duplex communication at a data transfer rate of 1000BASE-T. The two MAC controllers respectively receive the SGMII format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and transfer the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the SGMII-1000BASE-T link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0155] 7. GMII TO FIBER protocol transmission

[0156] (1) Protocol brief introduction

[0157] For both GMII TO FIBER and GMII TO COPPER communication methods, the communication protocol between the FPGA and the PHY is GMII. The communication protocols between the two PHY chips are different. FIBER is fiber communication through a high-speed serial interface, and COPPER is twisted-pair communication. The FIBER transmission medium and ports are shared with the SGMII interface, namely three pairs of high-speed differential signals: SIN, SOUT, and CLK. When communicating using the SGMII protocol, the three pairs of differential signals are connected to the FPGA. When using GMII TO FIBER for data transmission, the three pairs of differential signals are used for data transmission between the two PHYs.

[0158] (2) Test implementation

[0159] Start the test. Switch the high-speed relay, and interconnect the three pairs of high-speed differential signals of the two PHY chips. The digital channels of the ATE test bench provide the voltage required for the PHY chip under test to operate normally, and the PHY chip under test is powered on. Set the configuration pins A[2:0] of the control decoder to 110 according to Table 4 using the test vector. The FPGA loads the GMII TO COPPER controller IP core from the 6th configuration memory. The FPGA configures the CONFIG of the PHY chip under test and the countermeasure PHY chip through the IO pins. Specifically: through the control decoder TMUX1308, assign the control code 111 of the VDDO signal to CONFIG4; through another TMUX1308, assign the control code 000 of the VSS signal to CONFIG5; through the above hardware configuration, the register HWCFG MODE[3:0] is set to 0111, corresponding to the GMII TO COPPER communication protocol mode in Table 4; then send a reset signal, and the PHY chip under test and the countermeasure PHY chip start to reset and collect the hardware configuration information, and then perform handshaking and auto-negotiation.

[0160] From the start of the test to the success of the handshake, the ATE has been waiting through the test PATTERN, and a fixed waiting time is obtained through multiple tests. This time needs to ensure that both the PHY chip under test and the countermeasure PHY chip can successfully handshake; after the waiting ends, the ATE sends test data to a specific IO port of the FPGA through the test PATTERN. After the test data enters the FPGA, the FPGA packs the test data into the first data frame in GMII format and sends the first data frame to the PHY chip under test and the countermeasure PHY chip respectively; after the PHY chip under test and the countermeasure PHY chip receive the first data frame in GMII format and verify that the first data frame is intact, they send the first data frame to the other party through the high-speed serial interface; after both parties receive the first data frame, verify whether the first data frame is intact, and then convert the first data frame into a data frame in GMII format and send it to the FPGA as the second data frame; the FPGA receives the second data frames in GMII format sent by the PHY chip under test and the countermeasure PHY chip respectively, parses the second data frames to obtain the parsed data; and stores the parsed data as the test observation signal of the GMII protocol in the transmit FIFO; wait for the read valid signal and read clock of the ATE test bench, and finally send the data back to the ATE test bench for comparison according to the synchronization signal of the ATE test bench.

[0161] (3) Programming idea of the controller IP core

[0162] The GMII controller IP core mainly consists of five parts: a receive FIFO, a transmit FIFO, the MAC controller of the PHY chip under test, the MAC controller of the countermeasure PHY chip, and control logic. Among them, the control logic is used to implement the hardware configuration of the PHY chip under test and the countermeasure PHY chip, inform the PHY chip under test and the countermeasure PHY chip to communicate using the GMII-1000BASE X (FIBER) mode, send a reset signal, and control the collection of hardware configuration information after the PHY chip under test and the countermeasure PHY chip are reset to ensure the effectiveness of the hardware configuration. The receive FIFO is used to receive test data from the ATE test bench. It can recognize the write valid signal of the ATE test bench and read and store the test data into the receive FIFO under the drive of the write clock. After the reception is completed, the test data in the receive FIFO is sent to the two MAC controllers respectively. The MAC controllers package the test data and finally form the GMII data frames of the PHY chip under test and the countermeasure PHY chip. The data frames are sent through the physical interfaces of the MAC and PHY. Figure 17 Internal logic schematic diagram of the core FPGA GMII (TO FIBER) IP core.

[0163] The PHY chip under test and the countermeasure PHY chip simultaneously receive the GMII format data frames at the MAC layer and perform full-duplex communication through the data transmission rate of the FIBER. The two MAC controllers respectively receive the GMII format data frames of the PHY chip under test and the countermeasure PHY chip, perform data parsing, and send the parsed data back to the transmit FIFO. The transmit FIFO sends the data back to the ATE test bench for comparison under the drive of the ATE read signal. The actually received data should be exactly the same as the sent data. If the comparison is successful, it proves that the GMII-1000BASE-X link of the PHY chip under test and the countermeasure PHY chip is intact and meets the requirements of the data manual.

[0164] 8. Testing of DC parameters

[0165] According to the chip data manual, the DC parameters mainly include the testing of power consumption current and input and output levels. During the parameter testing process, the AVDD, DVDD, and VDDO of the PHY chip under test are directly powered by the digital channels of the ATE test bench, and the power consumption current of the three power supply terminals of the PHY chip under test can be read during the data transmission process.

[0166] During the functional testing process, data communication is carried out between the FPGA and the PHY chip under test. The pins of the PHY chip under test do not establish a direct connection relationship with the digital channels of the ATE test bench, and the input and output levels of pins such as TX, RX, and MIDO cannot be tested. At the same time, the integrity of the chip pin connections cannot be tested.

[0167] During the parameter test, first use the ATE control relay control module to switch, and switch all the pins of the PHY chip under test to the ATE test bench. Test the integrity of the pin connections of the PHY chip under test. Use the ATE test bench to configure and read the registers of the PHY chip under test through the MDIO pin, configure the PHY chip under test into the GMII protocol format and the LOOKBACK self-loop mode, parse the GMII Ethernet data frame, send the GMII data frame to the PHY chip under test through the TX pin, use the ATE test bench to receive the GMII data frame sent by the RX reception, and compare it with the sent data frame. Through the above method, use the SEARCH test method of modifying the dynamic load multiple times to comprehensively evaluate the input level threshold and the load-bearing capacity of the output level of the PHY chip under test.

[0168] In this embodiment, in order to meet the requirements of technical indicators and cover as many protocol data transmission methods of the PHY chip under test as possible, the research group separately developed 7 functional controller IP cores, namely GMII TO COPPER, MII TO COPPER, RGMII TO COPPER, TBI TO COPPER, RTBI TO COPPER, SGMII TO COPPER, and GMII TO FIBER, to meet the test requirements of different protocols. During the test, use the ATE test bench to control the 3-8 decoder to load the IP cores of different Ethernet protocols time-sharing, and increase the transmission of Ethernet data frames during the test in cooperation with the PHY chip under test, and finally realize the one-key test of the entire ATE control process. Realize the coverage test of 7 protocols such as SGMII, GMII, MII, RGMII, TBI, and RTBI between MAC and PHY, and at the same time traverse protocol formats such as 10BASE T, 100BASE T, 1000BASE T, and 1000BASE X. Among them, the data transmission rate of the SGMII protocol communication method reaches the maximum data transmission rate of the chip, 1250MBPS, meeting the test requirements. During the functional test process, the FPGA is the test core. Develop multiple controller IP cores and use multiple configuration memories to achieve multiple repeated loadings during the test process, so that the tests of multiple protocol formats can be realized through one-key testing; the FPGA generates the MAC controller core. After the FPGA receives the data sent by the ATE, it can automatically generate Ethernet data frames, automatically calculate the cyclic redundancy check code after modifying the data, and does not need to parse the Ethernet protocol, avoiding writing the complex protocol back to the test PATTERN by hand, which facilitates the debugging of the test development process. In addition, switch the pin connection method of the PHY chip under test through the relay control module, and parse the complex Ethernet data frame to realize the coverage test of the DC parameters of the PHY chip under test.

[0169] Those skilled in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. Among them, the computer-readable storage medium is a disk, an optical disc, a read-only memory, or a random access memory, etc.

[0170] As described above, only the preferred specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A test system for implementing functional testing of an Ethernet PHY chip, characterized in that The test system includes: an ATE test bench, an FPGA, and a PHY chip for cross-testing; wherein, The ATE test bench is used to store the test data and test instructions for the functional test of each Ethernet protocol of the PHY chip to be tested. The FPGA is used to load the controller IP core of the corresponding Ethernet protocol based on the test instructions of the corresponding Ethernet protocol when performing the functional test of each Ethernet protocol of the PHY chip to be tested; and use the controller IP core of the corresponding Ethernet protocol to convert the test data of the corresponding Ethernet protocol into the first data frame of the corresponding Ethernet protocol, and control the communication of the first data frame of the corresponding Ethernet protocol between the PHY chip to be tested and the PHY chip for cross-testing; and also parse the second data frame returned by the PHY chip to be tested and the PHY chip for cross-testing to the FPGA to obtain the test observation signal of the corresponding Ethernet protocol. The ATE test bench also determines whether the functional test of the corresponding Ethernet protocol passes based on the test observation signal of the corresponding Ethernet protocol.

2. The test system for implementing the functional test of the Ethernet PHY chip according to claim 1, characterized in that, The test system also includes a control decoder and a configuration memory corresponding to each Ethernet protocol; wherein, The control decoder is used to receive the test instructions of the Ethernet protocol sent by the ATE test bench to generate the control instructions for the configuration memory corresponding to the corresponding Ethernet protocol. The configuration memory selects the controller IP core of the corresponding Ethernet protocol for the FPGA to load based on the control instructions.

3. The test system for implementing the functional test of the Ethernet PHY chip according to claim 2, wherein The test system also includes a relay control module; The controller IP core of the Ethernet protocol includes the control logic of the corresponding Ethernet protocol, and the control logic includes the pin connection mode between the FPGA and the PHY chip to be tested. The relay control module is used to control the switching of the pin connection or disconnection between the PHY chip to be tested and the FPGA according to the controller IP core of the corresponding Ethernet protocol when performing the functional test of each Ethernet protocol of the PHY chip to be tested.

4. The test system for implementing the functional test of the Ethernet PHY chip according to claim 3, characterized in that, The test system also includes a system clock; The system clock is used to provide clock signals for the FPGA, the PHY chip to be tested, and the PHY chip for cross-testing.

5. The test system for implementing the functional test of the Ethernet PHY chip according to claim 4, wherein, The test system also includes a test adapter; in the test system, the FPGA, the PHY chip for cross-testing, the control decoder, the configuration memory corresponding to each Ethernet protocol, the relay control module, the system clock, and the test adapter are all arranged on the test board; wherein, The PHY chip for cross-testing is directly soldered on the test board; The PHY chip to be tested is fixed on the test board by screwing through the test adapter; The communication pins of the MAC layer of the PHY chip for cross-testing are directly connected to the FPGA, and the communication ports of the PHY chip for cross-testing and the PHY chip to be tested are docked after signal conditioning through a high-speed Ethernet transformer.

6. The test system for implementing the functional test of the Ethernet PHY chip according to any one of claims 1-5, characterized in that, In the FPGA, the first data frame of the Ethernet protocol is obtained by performing the following operations: The FPGA generates two identical MAC controllers of the corresponding Ethernet protocol based on the loaded controller IP core of the Ethernet protocol; one MAC controller is responsible for communicating with the PHY chip to be tested, and the other MAC controller is responsible for communicating with the PHY chip for cross-testing. Two MAC controllers respectively process the test data of the corresponding Ethernet protocol, convert it into the first data frame of the corresponding Ethernet protocol, and send the first data frame of the corresponding Ethernet protocol to the PHY chip under test or the countermeasure PHY chip connected by communication.

7. The test system for implementing the functional test of the Ethernet PHY chip according to claim 6, characterized in that, The PHY chip under test and the countermeasure PHY chip obtain the second data frame by performing the following operations: After the PHY chip under test and the countermeasure PHY chip respectively pass the verification of the received first data frame, they send the first data frame to each other at the preset data transmission rate. After both parties receive the first data frame and pass the verification, they convert the first data frame into the data frame of the corresponding Ethernet protocol and send it to the FPGA as the second data frame.

8. The test system for implementing the functional test of the Ethernet PHY chip according to claim 7, characterized in that In the FPGA, The receive FIFO is used to receive the test data of the corresponding Ethernet protocol from the ATE test bench. The transmit FIFO is used to store the data obtained by parsing the second data frame as the test observation signal of the corresponding Ethernet protocol.

9. The test system for implementing the functional test of an Ethernet PHY chip according to claim 8, characterized in that, The ATE test bench determines whether the function test of the Ethernet protocol passes by performing the following operations: The ATE test bench sends a read valid signal and a read clock to the FPGA to read the test observation signal in the transmit FIFO of the FPGA. The ATE test bench compares the test data of the corresponding Ethernet protocol with the test observation signal. If they are consistent, the function test of the corresponding Ethernet protocol passes; otherwise, the function test of the corresponding Ethernet protocol fails.

10. The test system for implementing the functional test of the Ethernet PHY chip according to claim 1, wherein, Each function test selects one Ethernet protocol from GMII\MII\RGMII\TBI\RTBI\SGMII and one data transmission rate from 10 / 100 / 1000BASE T to cooperate for data transmission.

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