MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with gallium oxide super junction structure and manufacturing method

Abstract

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure with a gallium oxide super-junction structure and a manufacturing method, and mainly solves the problems of a compromise relationship between specific on-resistance and breakdown voltage and large static power consumption of a conventional gallium oxide MOSFET power device. The AlGaO / Ga2O3 heterojunction field effect transistor comprises a substrate, a Ga2O3 buffer layer and a barrier layer, wherein the barrier layer comprises two unintentionally doped AlGaO layers and a delta-doped AlGaO layer; a p-thin film layer and a p + thin film layer are sequentially arranged at the upper part of the barrier layer, and a super junction structure is formed among the three layers; the upper surface of the p + film layer is a base electrode, two ends of the buffer layer are a source electrode and a drain electrode, a gate electrode is arranged between the source electrode and the drain electrode, and an insulated gate dielectric layer is arranged below the gate electrode. By introducing the delta-doped AlGaO / Ga2O3 heterojunction and super junction structure, the carrier mobility can be improved, the specific on-resistance of the device can be reduced, the reverse withstand voltage of the device can be improved, the static power consumption and the dynamic power consumption can be reduced, and the device can be used as a power and high-voltage switching device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be used for power devices and switching devices. Background Art

[0002] Gallium oxide (Ga2O3) material is a semiconductor material with an ultra-wide bandgap. Due to its ultra-wide bandgap width of 4.2 - 4.9 eV and the advantage that the theoretical critical breakdown field strength can reach 8 MV / cm, it is considered a very promising high-voltage and high-power-density switching device. Research experimental results show that the Baliga figure of merit of β-Ga2O3 is 4 times that of GaN, 10 times that of SiC, and 3444 times that of Si. Under the same breakdown voltage as GaN and SiC devices, it has a lower on-resistance and smaller power consumption, which can greatly reduce the power loss during device operation. Compared with silicon and third-generation semiconductor devices, Ga2O3-based devices perform very well in breakdown voltage and on-state loss. However, the electron mobility of Ga2O3 material is relatively low, with a theoretical limit of only 300 cm 2 / V·s, and due to epitaxy and process reasons, the maximum electron mobility measured for Ga2O3 field-effect transistors reported currently at room temperature is only 180 cm 2 / V·s. Compared with field-effect transistors of other materials, its low electron mobility limits its applications in high-power and high-frequency fields. And currently, it is difficult to achieve a high-quality epitaxial growth of a monolithic P-type gallium oxide drift region for Ga2O3, so the realization of the breakdown voltage terminal of power devices and the reduction of specific on-resistance become very difficult. Therefore, it is crucial to realize a gallium oxide MOSFET device that simultaneously satisfies high breakdown voltage, low on-resistance, and high electron mobility.

[0003] The patent document with the application number 202210624808.1 discloses a horizontal enhancement-mode gallium oxide metal-oxide-semiconductor field-effect transistor and its manufacturing method, which includes: a substrate, a buffer layer, a channel layer, a P-type NiO thin film layer with different doping concentrations, and three electrodes, as Figure 1 shown. This device mainly solves the problems that the conventional gallium oxide depletion-mode MOSFET cannot be turned off when the gate is at zero bias and has a large static power consumption. Although it can realize an enhancement-mode gallium oxide MOSFET device, it does not improve the problem of low electron mobility.

[0004] The patent document with the application number 202311580701.2 discloses a preparation method of a high-electron-mobility gallium oxide field-effect transistor and the transistor, which includes: a substrate, a buffer layer, an unintentionally doped Ga2O3 channel layer, and an AlGaO barrier layer, as Figure 2As shown. By preparing an AlGaO / Ga2O3 heterojunction, a two-dimensional electron gas is formed, increasing the electron mobility of the field effect transistor. However, its breakdown voltage ability has not been improved, and the specific on-resistance is very high, resulting in a large static power consumption of the device. Summary of the Invention

[0005] The object of the present invention is to propose a MOSFET device with a gallium oxide superjunction structure and its manufacturing method in view of the deficiencies of the above-mentioned prior art, so as to improve the trade-off relationship between the breakdown voltage (BV) and the specific on-resistance (R on,sp ) in power devices, improve the reverse breakdown voltage ability of the device, reduce the on-resistance, and enhance the forward conduction performance of the device.

[0006] The technical key of the present invention is: by introducing a δ-doped AlGaO / Ga2O3 heterojunction and a superjunction structure, increasing the carrier concentration and mobility in the device channel, improving the conduction performance, increasing the breakdown voltage ability of the device, and reducing the specific on-resistance. Its implementation scheme includes the following:

[0007] 1. A MOSFET device with a gallium oxide superjunction structure, comprising: a substrate, a Ga2O3 buffer layer, a barrier layer, a P-type thin film layer, an insulating gate dielectric layer, a source electrode, a drain electrode, a gate electrode, and a base electrode, characterized in that: the barrier layer includes two unintentionally doped AlGaO layers and one δ-doped AlGaO layer, and the δ-doped AlGaO layer is located between the two unintentionally doped AlGaO layers; the Ga2O3 buffer layer is located below the barrier layer; the P-type thin film layer includes two p + thin film layers with different doping concentrations and p - thin film layer; the base electrode is electrically connected to the gate electrode.

[0008] Further, the substrate is located below the Ga2O3 buffer layer; the P-type thin film layer is located above the barrier layer; the base electrode is located on the upper surface of the P-type thin film layer; the source electrode and the drain electrode are respectively located at both ends of the Ga2O3 buffer layer; the gate electrode is located between the source electrode and the drain electrode, and an insulating gate dielectric layer is provided below the gate electrode.

[0009] Further, the substrate is made of a semi-insulating β-Ga2O3 material doped with Mg or Fe, with a thickness of 2 - 3 μm; the Ga2O3 buffer layer is made of β-Ga2O3 material, with a thickness of 400 nm - 1 μm; the P-type thin film layer is made of any one of NiO, MnO, Cu2O, CoO materials; the insulating gate dielectric layer is made of any one of Al2O3, SiO2, HfO2, SiN materials, with a thickness of 20 - 60 nm.

[0010] Further, the thicknesses of the unintentionally doped AlGaO layers are 2 - 5 nm and 25 - 30 nm respectively; the thickness of the δ-doped AlGaO layer is 1 - 3 nm, and its doping material is Si or Ge with a doping concentration of 3×10 18 ~2×10 19 cm -3 ; the upper p + thin film layer has a thickness of 5 - 10 nm and a doping concentration of 3×10 19 ~8×10 19 cm -3 ; the lower p - thin film layer has a thickness of 100 - 200 nm and a doping concentration of 10 17 ~10 18 cm -3 .

[0011] 2. A manufacturing method of a MOSFET device with a gallium oxide superjunction structure, characterized by comprising the following steps:

[0012] S1) After epitaxially growing a Ga2O3 buffer layer on a substrate layer by using the MOCVD process, perform organic cleaning and deionized water cleaning in sequence, and blow dry with high-purity N2;

[0013] S2) By using the MOCVD or MBE process, first deposit a first unintentionally doped AlGaO layer on the surface of the cleaned sample, then deposit a δ-doped AlGaO layer with a doping concentration of 3×10 18 ~2×10 19 cm -3 , and then deposit a second unintentionally doped AlGaO layer on the δ-doped AlGaO layer to form a barrier layer;

[0014] S3) By using the PECVD process, deposit a SiO2 layer on the surface of the sample deposited with the barrier layer as a regrowth mask, perform photolithography and etching on the regrowth mask layer until below the heterojunction interface, and remove the photoresist after the etching is completed;

[0015] S4) By using the MOCVD process, grow an n-type Ga2O3 layer with a doping concentration of 5×10 19 cm -3 in the etched area as the source and drain regions, and use wet etching to remove the regrowth mask;

[0016] S5) By using the EBM process, deposit 30 - 60 nm / 100 - 200 nm thick Ti / Au on the source and drain regions, and then perform annealing in an N2 atmosphere at 400 - 500 °C to form source electrodes and drain electrodes;

[0017] S6) Lithography is performed on the sample forming the source and drain electrodes to form the sputtering region of the P-type thin film layer, and a p-type thin film layer with a doping concentration of 10 17 ~10 18 cm -3 is first prepared on the sample surface by radio frequency magnetron sputtering technology, and then a p-type thin film layer with a doping concentration of 3×10 - ~8×10 19 ~8×10 19 cm -3 is prepared; +

[0018] S7) The base region is lithographed on the surface of the p-type thin film layer. Using the EBM process, after depositing Ni / Au with a thickness of 30 - 60 nm / 100 - 200 nm on the base region, annealing is then carried out in an N2 atmosphere at 400 - 500 °C to form the base; +

[0019] S8) Using the ALD process, Al2O3 with a thickness of 20 - 60 nm is deposited on the surface of the sample after the operation in step S7) to form the insulating gate dielectric layer;

[0020] S9) The gate region is lithographed on the insulating gate dielectric layer. Using the EBM process, Ni / Au with a thickness of 30 - 60 nm / 100 - 200 nm is deposited on the gate region. After metal lift-off, cleaning is carried out and dried with high-purity N2 to form the gate electrode;

[0021] S10) The source / drain / base region is lithographed on the insulating gate dielectric layer. The source / drain / base region is dry-etched using the RIE process to expose the ohmic contact metal of the source / drain / base region, and the device fabrication is completed.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] First, since the present invention is provided with a δ-doped AlGaO / Ga2O3 heterojunction, the two-dimensional electron gas (2DEG) formed has a high carrier concentration; at the same time, since the δ-doped layer in the heterojunction is extremely thin, there is less scattering of ionized impurities and the electron mobility is higher, enabling the electrons in the two-dimensional electron gas (2DEG) to have an extremely high maximum saturation velocity, effectively reducing the on-resistance and improving the on-capability of the device.

[0024] Second, since the present invention sets the P-type thin film layer to include two p-type thin film layers with different doping concentrations, namely the upper and lower layers, the p-type thin film layer can provide holes for the device and form a depletion region with the channel, reducing the on-resistance of the device and increasing the reverse breakdown voltage; through the p-type thin film layer + and the p-type thin film layer - the p-type thin film layer can provide holes for the device and form a depletion region with the channel, reducing the on-resistance of the device and increasing the reverse breakdown voltage; through the p-type thin film layer - the p-type thin film layer can provide holes for the device and form a depletion region with the channel, reducing the on-resistance of the device and increasing the reverse breakdown voltage; through the p-type thin film layer + ​​The thin film layer forms an ohmic contact with the base, which can better regulate the forward conduction characteristics of the device.

[0025] Thirdly, in the present invention, since the Ga2O3 buffer layer is disposed below the barrier layer, the reverse leakage of the device is reduced, and the breakdown voltage and reliability of the device are improved.

[0026] Fourthly, in the present invention, since the base is electrically connected to the gate electrode, the effective length of the gate electrode is increased, the gate control ability of the channel is enhanced, and the electric field concentration effect of the gate electrode is alleviated. Description of the Drawings

[0027] Figure 1 It is a schematic cross-sectional view of the device in Comparative Document 1;

[0028] Figure 2 It is a schematic cross-sectional view of the device in Comparative Document 2;

[0029] Figure 3 It is a schematic cross-sectional structure view of the device of the present invention;

[0030] Figure 4 It is a schematic process flow diagram of the preparation of the device of the present invention. Detailed Embodiments

[0031] The following describes the embodiments of the present invention in detail with reference to the accompanying drawings, but is not limited to the embodiments described herein.

[0032] Reference Figure 3 , the MOSFET device with a gallium oxide superjunction structure in this example includes: a substrate 1, a Ga2O3 buffer layer 2, a barrier layer 3, a P-type thin film layer 4, an insulating gate dielectric layer 5, a source electrode 6, a drain electrode 7, a gate electrode 8, and a base 9. Among them:

[0033] The substrate 1 is made of semi-insulating β-Ga2O3 material doped with Mg or Fe, and has a thickness of 2-3 μm;

[0034] The Ga2O3 buffer layer 2 is located above the substrate 1, and is made of β-Ga2O3 material, with a thickness of 400 nm-1 μm;

[0035] The barrier layer 3 is located above the Ga2O3 buffer layer 2, and includes: an unintentionally doped AlGaO layer 31 with a thickness of 2-5 nm, a doping concentration of 3×10 18 -2×10 19 cm -3 , a 1-3 nm thick δ-doped AlGaO layer 32, and a 25-30 nm unintentionally doped AlGaO layer 33;

[0036] The source electrode 6 and the drain electrode 7 are located at both ends of the Ga2O3 buffer layer 2, and both are made of 30-60nm / 100-200nm Ti / Au metal materials;

[0037] The P-type thin film layer 4 is located on the upper part of the barrier layer 3 and includes two layers: the doping concentration is 3×10 19 ~8×10 19 cm -3 , 5~10nm thick p + The thin film layer 41 and the doping concentration are 10 17 ~10 18 cm -3 , 100~200nm thick p - Thin film layer 42;

[0038] The base 9 is located at p + The upper surface of the thin film layer 41 is made of 30-60nm / 100-200nm Ni / Au metal material;

[0039] The insulating gate dielectric layer 5 is made of Al2O3 material and has a thickness of 20 to 60 nm;

[0040] The gate electrode 8 is located on the upper surface of the insulating gate dielectric layer 5 , is made of 30-60nm / 100-200nm Ni / Au metal material, and is electrically connected to the base 9 .

[0041] Reference Figure 4 The present invention provides the following three embodiments of the method for manufacturing a gallium oxide super junction MOSFET device:

[0042] Example 1: On a Fe-doped Ga2O3 semi-insulating substrate, a first unintentionally doped AlGaO layer with a thickness of 4.5 nm, a second unintentionally doped AlGaO layer with a thickness of 24.5 nm, a δ-Si-doped AlGaO layer with a thickness of 3 nm and a doping concentration of 3×10 18 cm -3 , p + The NiO film layer thickness is 10nm and the doping concentration is 5×10 19 cm -3 , p - The NiO film layer thickness is 150nm and the doping concentration is 5×10 17 cm -3 Gallium oxide superjunction MOSFET device.

[0043] Step 1: epitaxially grow a Ga2O3 buffer layer on a Fe-doped Ga2O3 substrate layer using a MOCVD process. Figure 4 (a).

[0044] 1.1) Place a semi-insulating Ga2O3 substrate doped with Fe and with a thickness of 2 μm in acetone, anhydrous ethanol solution, and deionized water in sequence, ultrasonically clean for 5 min, and dry with high-purity N2.

[0045] 1.2) Set TEGa and O2 as the gallium source and oxygen source, use N2 as the carrier gas, and under the process conditions that the flow rates of TEGa and O2 are 60 sccm and 2500 sccm respectively, the reaction chamber temperature is 600 °C, and the growth pressure is 25 Torr, epitaxially grow a Ga2O3 buffer layer with a thickness of 500 nm on the Fe-doped Ga2O3 semi-insulating substrate layer.

[0046] Step 2, use the MOCVD process to grow a barrier layer on the Ga2O3 buffer layer, as Figure 4 (b).

[0047] Set TEGa, TMAl, and O2 as the gallium source, aluminum source, and oxygen source, use TEOS as the Si doping source, and N2 as the carrier gas. Under the process conditions that the flow rates of TEGa, TMAl, and O2 are 60 sccm, 25 sccm, and 2500 sccm respectively, the reaction chamber temperature is 600 °C, and the growth pressure is 25 Torr, epitaxially grow a 4.5-nm-thick first unintentionally doped AlGaO layer, a δ-Si-doped AlGaO layer with a thickness of 3 nm, and a 24.5-nm-thick second unintentionally doped AlGaO layer on the Ga2O3 buffer layer in sequence to form a three-layer structure barrier layer. 18 cm -3 -3, and form a three-layer structure barrier layer.

[0048] Step 3, deposit a regrowth mask on the surface of the second unintentionally doped AlGaO layer, as Figure 4 (c).

[0049] Use plasma-enhanced chemical vapor deposition (PECVD) method, use SiH4 and O2 as the silicon source and oxygen source, and under the process conditions that the flow rates of SiH4 and O2 are 30 sccm and 150 sccm respectively, the reaction chamber temperature is 300 °C, the growth pressure is 800 mTorr, and the radio frequency power is 100 W, deposit 200 nm of SiO2 on the sample surface as the regrowth mask.

[0050] Step 4, etch the regrowth mask to etch out the growth region, as Figure 4 (d).

[0051] First, perform photolithography on the regrown mask to expose the source and drain regions. Then, using the reactive ion etching (RIE) method, etch the regrown mask to a depth of 240 nm under the process conditions of a chamber pressure of 5.0 Pa, a plasma power of 150 W, and flow rates of BCl3 and Ar of 30 sccm and 20 sccm respectively. After that, remove the photoresist.

[0052] Step 5: In the etched growth region, grow the source and drain regions and remove the mask, as shown in Figure 4 (e).

[0053] 5.1) Using the metalorganic chemical vapor deposition (MOCVD) method, with TEGa and O2 as the gallium source and oxygen source respectively, and N2 as the carrier gas, grow a heavily doped n-type Ga2O3 layer with a doping concentration of 5×10 19 cm -3 and a thickness of 40 nm on the etched area under the process conditions of flow rates of TEGa and O2 of 60 sccm and 2500 sccm respectively, a reaction chamber temperature of 600 °C, and a growth pressure of 25 Torr.

[0054] 5.2) Use wet etching to remove the remaining regrown mask at room temperature. The etching solution is: HF solution (HF:H2O = 1:10), for a time of 1 min. After etching, wash the sample with a large amount of deionized water.

[0055] Step 6: Fabricate the source and drain ohmic electrodes, as shown in Figure 4 (f).

[0056] 6.1) Photolithograph the source and drain preset regions on the cleaned sample, and sequentially deposit 30 nm of Ti and 100 nm of Au in this region through the electron beam evaporation (EBM) process. After the metal deposition is completed, place the sample in an acetone solution for lift-off and soak it in an NMP solution for 1 min to remove the photoresist.

[0057] 6.2) Ultrasonically clean the sample after lift-off in acetone, absolute ethanol solution, and deionized water for 5 min respectively, dry it with high-purity N2, and perform thermal annealing at a temperature of 450 °C and a nitrogen flow rate of 3 L / min for 1 min to form a good ohmic contact.

[0058] Step 7: Fabricate a double-layer P-type NiO thin film, as shown in Figure 4 (g).

[0059] 7.1) Lithographically pattern the NiO sputtering region on the sample that will form the source and drain electrodes. Select 99.99% high-purity NiO ceramic as the target material. Under the process conditions of a magnetron sputtering power of 150 W and a growth environment of a mixed gas of 0.6 Pa Ar and O2, control the Ar flow rate at 40 sccm and the O2 flow rate at 2 sccm. Sputter in the sputtering region to obtain a p-type NiO thin film layer with a thickness of 150 nm and a doping concentration of 5×10 17 cm -3 -type - NiO thin film layer;

[0060] 7.2) Select 99.99% high-purity NiO ceramic as the target material. Under the process conditions of a magnetron sputtering power of 150 W and a growth environment of a mixed gas of 0.6 Pa Ar and O2, control the Ar flow rate at 40 sccm and the O2 flow rate at 20 sccm. Sputter on the p - -type NiO thin film layer to obtain a p-type NiO thin film layer with a thickness of 10 nm and a doping concentration of 5×10 19 cm -3 -type + NiO thin film layer;

[0061] 7.3) Remove the photoresist on the sputtered sample and anneal it in an oxygen atmosphere at a temperature of 400 °C for 30 minutes to improve the crystallinity and stability of the thin film.

[0062] Step 8, fabricate the base electrode, as shown in Figure 4 (h).

[0063] 8.1) Lithographically pattern the base electrode preset region on the surface of the p + -type NiO thin film. Sequentially deposit 30 nm of Ni and 100 nm of Au in this region through the EBM process. After the metal deposition is completed, place the sample in an acetone solution for lift-off and soak it in an NMP solution for 1 min to remove the photoresist;

[0064] 8.2) Ultrasonically clean the sample after lift-off in acetone, absolute ethanol solution, and deionized water for 5 min respectively, and then dry it with high-purity N2 to form the base electrode. Then, perform thermal annealing at a temperature of 450 °C and a nitrogen flow rate of 3 L / min for 1 min to form a good ohmic contact.

[0065] Step 9, fabricate the insulating gate dielectric layer using the ALD process, as shown in Figure 4 (i).

[0066] Using TMA and H2O as the aluminum source and oxygen source respectively, deposit Al2O3 with a thickness of 20 nm on the surface of the sample by atomic layer deposition (ALD) at a reaction chamber temperature of 400 °C and a growth rate of 0.1 nm / cycle to form the insulating gate dielectric layer.

[0067] Step 10, fabricate the gate electrode, as shown in Figure 4 (j).

[0068] 10.1) Photolithographically define the gate preset area on the surface of the insulating gate dielectric layer, and sequentially deposit Ni with a thickness of 30 nm and Au with a thickness of 100 nm in this area by the EBM process. After the metal deposition is completed, place the sample in an acetone solution for metal lift-off, and soak it in an NMP solution for 1 min to remove the photoresist;

[0069] 10.2) Ultrasonically clean the sample after metal lift-off in acetone, absolute ethanol solution, and deionized water for 5 min respectively, and then dry it with high-purity N2 to form the gate electrode.

[0070] Step 11, open holes, as shown in Figure 4 (k)

[0071] 11.1) Photolithographically define the source / drain / base regions on the insulating gate dielectric layer;

[0072] 11.2) Use the reactive ion etching (RIE) method to dry-etch the source / drain / base regions under the process conditions of a chamber pressure of 5.0 Pa, a plasma power of 150 W, and the flow rates of BCl3 and Ar being 30 sccm and 20 sccm respectively, to expose the ohmic contact metal of the source / drain / base regions and complete the device fabrication.

[0073] Example 2, on a Mg-doped Ga2O3 semi-insulating substrate, fabricate a gallium oxide superjunction MOSFET device with a first unintentionally doped AlGaO layer having a thickness of 3 nm, a second unintentionally doped AlGaO layer having a thickness of 27 nm, a δ-Si-doped AlGaO layer having a thickness of 2 nm and a doping concentration of 5×10 18 cm -3 , p + MnO thin film layer having a thickness of 5 nm and a doping concentration of 8×10 19 cm -3 , p - MnO thin film layer having a thickness of 100 nm and a doping concentration of 1×10 18 cm -3 .

[0074] Step 1, epitaxially grow a Ga2O3 buffer layer on the Mg-doped Ga2O3 substrate layer, as shown in Figure 4 (a).

[0075] A Mg-doped Ga2O3 semi-insulating substrate with a thickness of 2.5 μm was successively placed in acetone, anhydrous ethanol solution and deionized water for ultrasonic cleaning for 5 min, and then dried with high-purity N2. Using TEGa and O2 as gallium source and oxygen source respectively, and N2 as carrier gas, with the flow rates of TEGa and O2 being 60 sccm and 2500 sccm respectively, the reaction chamber temperature being 600 °C, and the growth pressure being 25 Torr, a Ga2O3 buffer layer with a thickness of 800 nm was epitaxially grown on the Mg-doped Ga2O3 semi-insulating substrate layer by MOCVD process.

[0076] Step two, grow a barrier layer on the Ga2O3 buffer layer, as Figure 4 (b).

[0077] Set TEGa, TMAl and O2 as gallium source, aluminum source and oxygen source respectively, TEOS as Si doping source, N2 as carrier gas, with the flow rates of TEGa, TMAl and O2 being 60 sccm, 25 sccm and 2500 sccm respectively, the reaction chamber temperature being 600 °C, and the growth pressure being 25 Torr. By MOCVD process, grow a barrier layer on the Ga2O3 buffer layer, that is, first deposit a 3-nm-thick first unintentionally doped AlGaO layer, then deposit a δ-Si-doped AlGaO layer with a doping concentration of 5×10 18 cm -3 and a thickness of 2 nm, and then deposit a 27-nm-thick second unintentionally doped AlGaO layer on the δ-Si-doped AlGaO layer.

[0078] Step three, deposit a regrowth mask on the surface of the second unintentionally doped AlGaO layer, as Figure 4 (c).

[0079] Set SiH4 and O2 as silicon source and oxygen source respectively, with their flow rates being 40 sccm and 200 sccm respectively, the reaction chamber temperature being 300 °C, the growth pressure being 800 mTorr, and the RF power being 150 W. Using PECVD method, deposit 400 nm of SiO2 on the sample surface as the regrowth mask.

[0080] Step four, etch the regrowth mask to etch out the growth region, as Figure 4 (d).

[0081] Perform photolithography on the regrowth mask to expose the source-drain region. Set the chamber pressure to 5.0 Pa, the plasma power to 150 W, and the flow rates of BCl3 and Ar to 30 sccm and 20 sccm respectively. Using RIE method, etch the regrowth mask to a depth of 450 nm, and finally remove the photoresist.

[0082] Step Five: In the etched growth region, grow the source and drain regions and remove the mask, as shown in Figure 4 (e).

[0083] Set TEGa and O2 as the gallium source and oxygen source, with the flow rates of 60 sccm and 2500 sccm respectively, N2 as the carrier gas, the reaction chamber temperature of 600 °C, and the growth pressure of 25 Torr. Using the metalorganic chemical vapor deposition (MOCVD) method, grow a heavily doped n-type Ga2O3 layer with a doping concentration of 5×10 19 cm -3 and a thickness of 50 nm; then, through wet etching, use an HF solution (HF:H2O = 1:10) to etch the remaining regrowth mask at room temperature for 2 min. After etching, wash the sample with a large amount of deionized water.

[0084] Step Six: Fabricate the source-drain ohmic electrodes, as shown in Figure 4 (f).

[0085] Lithograph the sample after removing the mask to obtain the source-drain preset region. Sequentially deposit 50 nm of Ti and 150 nm of Au in this region through the electron beam evaporation (EBM) process. After completion, put the sample into an acetone solution for lift-off and soak it in an NMP solution for 1 min to remove the photoresist; then ultrasonically clean it in acetone, absolute ethanol solution, and deionized water for 5 min respectively and dry it with high-purity N2; and perform thermal annealing at a temperature of 450 °C and a nitrogen flow rate of 3 L / min for 1 min to form a good ohmic contact.

[0086] Step Seven: Fabricate the double-layer p-type MnO thin film, as shown in Figure 4 (g).

[0087] Lithograph the sample with the source-drain electrodes to obtain the MnO sputtering region. Select 99.99% high-purity MnO as the target material, set the magnetron sputtering power to 150 W, and the growth environment to a mixed gas of 0.6 Pa Ar and O2. Control the Ar flow rate to be 50 sccm and the O2 flow rate to be 1 sccm. Sputter in the sputtering region to obtain a p 18 cm -3 MnO thin film layer with a thickness of 100 nm and a doping concentration of 1×10 - ; then control the Ar flow rate to be 50 sccm and the O2 flow rate to be 5 sccm, and sputter on the p - MnO thin film layer to obtain a p 19 cm -3 MnO thin film layer with a thickness of 5 nm and a doping concentration of 8×10 +MnO thin film layer; after the thin film growth is completed, the photoresist on the sample is removed, and the sample is annealed for 30 minutes in an oxygen atmosphere at a temperature of 400 °C to improve the crystallinity and stability of the thin film.

[0088] Step eight, prepare the base electrode, as Figure 4 (h).

[0089] Photolithograph the base electrode area on the surface of the p + MnO thin film, and sequentially deposit 50 nm of Ni and 150 nm of Au in this area through the EBM process. After the metal deposition is completed, the sample is soaked in acetone solution and NMP solution in sequence to complete the metal lift-off and remove the photoresist; then the sample is ultrasonically cleaned in acetone, absolute ethanol solution and deionized water for 5 min respectively and then dried with high-purity N2 to form the base electrode; and at a temperature of 450 °C and a nitrogen gas flow rate of 3 L / min, thermal annealing is carried out for 1 min to form a good ohmic contact.

[0090] Step nine, fabricate the insulating gate dielectric layer, as Figure 4 (i).

[0091] Set TMA and H2O as the aluminum source and oxygen source, with the reaction chamber temperature of 400 °C and the growth rate of 0.1 nm / cycle. Using the atomic layer deposition (ALD) process, deposit Al2O3 with a thickness of 40 nm on the surface of the sample to form the insulating gate dielectric layer.

[0092] Step ten, prepare the gate electrode, as Figure 4 (j).

[0093] Photolithograph the preset gate electrode area on the surface of the insulating gate dielectric layer, and sequentially deposit a 50-nm-thick Ni and a 150-nm-thick Au in this area through the EBM process. After the metal deposition is completed, the sample is soaked in acetone solution and NMP solution in sequence to complete the metal lift-off and remove the photoresist; then the sample is ultrasonically cleaned in acetone, absolute ethanol solution and deionized water for 5 min respectively and then dried with high-purity N2 to form the gate electrode.

[0094] Step eleven, open holes, as Figure 4 (k)

[0095] Photolithograph the source / drain / base electrode areas on the insulating gate dielectric layer. Set the chamber pressure to 5.0 Pa, the power of the plasma to 150 W, and the flow rates of BCl3 and Ar to 30 sccm and 20 sccm respectively. Through the reactive ion etching (RIE) method, dry-etch the source / drain / base electrode areas to expose the ohmic contact metal in the source / drain / base areas, and finally complete the device fabrication.

[0096] Example 3. On a Mg-doped Ga2O3 semi-insulating substrate, a first unintentionally doped AlGaO layer with a thickness of 2 nm, a second unintentionally doped AlGaO layer with a thickness of 28 nm, and a δ-Ge-doped AlGaO layer with a thickness of 1 nm and a doping concentration of 2×10 19 cm -3 , p + A Cu2O thin film layer with a thickness of 10 nm and a doping concentration of 5×10 19 cm -3 , p - A Cu2O thin film layer with a thickness of 180 nm and a doping concentration of 3×10 17 cm -3 Gallium oxide superjunction MOSFET device.

[0097] Step A. Using the MOCVD process, grow a Ga2O3 buffer layer epitaxially on the Mg-doped Ga2O3 substrate layer, as shown in Figure 4 (a).

[0098] A1) Place a semi-insulating Ga2O3 substrate doped with Mg and having a thickness of 3 μm in acetone, anhydrous ethanol solution, and deionized water in sequence, ultrasonically clean for 5 min, and dry with high-purity N2;

[0099] A2) Place the cleaned substrate layer in the reaction chamber, and grow a Ga2O3 buffer layer with a thickness of 1 μm on the substrate by the MOCVD process. The process conditions for MOCVD growth are as follows:

[0100] Using TEGa as the gallium source, O2 as the oxygen source, and N2 as the carrier gas, set the flow rates of TEGa and O2 introduced to be 60 sccm and 2500 sccm respectively, the reaction chamber temperature is 600 °C, and the growth pressure is 25 Torr.

[0101] Step B. Using the MBE process, grow a barrier layer on the Ga2O3 buffer layer, as shown in Figure 4 (b).

[0102] B1) Clean the sample epitaxially grown with the Ga2O3 buffer layer successively with organic solvents and deionized water, and dry with high-purity N2;

[0103] B2) Place the cleaned sample in the molecular beam epitaxy MBE growth chamber, heat high-purity Ga blocks and high-purity Al blocks in the K chamber to provide gallium and aluminum elements, and use a mixed gas with 5% O3 and 95% O2 to provide oxygen elements;

[0104] B3) First, grow a 2-nm-thick first unintentionally doped AlGaO layer. After the growth is completed, suspend the supply of the molecular beam fluxes of Al, Ga, and O, and at the same time, turn on the Ge source furnace to start δ-doping, and prepare a δ-Ge-doped AlGaO layer with a doping concentration of 2×10 19 cm -3 and a thickness of 1 nm. After the preparation is completed, turn off the Ge source furnace, reopen the molecular beam fluxes of Al, Ga, and O, and continue to grow a 28-nm-thick second unintentionally doped AlGaO layer to cover the δ-doped layer.

[0105] Step C, deposit a regrowth mask on the surface of the second unintentionally doped AlGaO layer, as shown in Figure 4 (c).

[0106] Using PECVD method, deposit 500 nm of SiO2 on the sample surface as the regrowth mask. The process conditions of the PECVD method are as follows:

[0107] Using SiH4 as the silicon source and O2 as the oxygen source, set their flow rates to 40 sccm and 200 sccm respectively, the reaction chamber temperature is 300 °C, the growth pressure is 800 mTorr, and the RF power is 150 W.

[0108] Step D, etch the regrowth mask to etch out the growth region, as shown in Figure 4 (d).

[0109] Perform photolithography on the regrowth mask to expose the source-drain region, etch the regrowth mask to a depth of 550 nm by RIE, and finally remove the remaining photoresist. The process conditions of the RIE etching are as follows:

[0110] Set the chamber pressure to 5.0 Pa, the power of the plasma to 150 W, and the flow rates of BCl3 and Ar to 30 sccm and 20 sccm respectively.

[0111] Step E, in the etched growth region, grow the source region and the drain region, and remove the mask, as shown in Figure 4 (e).

[0112] E1) Use metalorganic chemical vapor deposition MOCVD to grow a heavily doped n-type Ga2O3 layer with a doping concentration of 5×10 19 cm -3 and a thickness of 50 nm in the etched region. The process conditions of the MOCVD method are as follows:

[0113] Using TEGa as the gallium source and O2 as the oxygen source, set their flow rates into the reaction chamber to 60 sccm and 2500 sccm respectively, using N2 as the carrier gas, the reaction chamber temperature is 600 °C, and the growth pressure is 25 Torr;

[0114] E2) Use wet etching to etch the remaining regrown mask with an HF solution (HF:H2O = 1:10) at room temperature for 3 minutes. After etching, wash the sample with a large amount of deionized water.

[0115] Step F, fabricate source-drain ohmic electrodes, as shown in Figure 4 (f).

[0116] F1) Perform photolithography on the sample after etching the mask to obtain the source-drain preset area. Sequentially deposit 60 nm of Ti and 200 nm of Au in this area by the EBM process. After completion, place the sample in an acetone solution for lift-off and soak it in an NMP solution for 1 minute to remove the photoresist.

[0117] F2) Place the sample in acetone, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes, then dry it with high-purity N2, and perform thermal annealing at a temperature of 450 °C and a nitrogen flow rate of 3 L / min for 1 minute to form a good ohmic contact.

[0118] Step G, fabricate a double-layer p-type Cu2O thin film, as shown in Figure 4 (g).

[0119] G1) Photolithograph the Cu2O sputtering area on the sample with source-drain electrodes formed. Obtain a p-type Cu2O thin film layer with a thickness of 180 nm and a doping concentration of 3×10 17 cm -3 by magnetron sputtering in the sputtering area, where the process conditions of the magnetron sputtering method are as follows: - Select 99.99% high-purity Cu2O doped with Li element as the target material, set the magnetron sputtering power to 150 W, use 99.99% high-purity Ar as the sputtering gas, and control the Ar flow rate to be 30 sccm;

[0120] Select 99.99% high-purity Cu2O doped with Li element as the target material, set the magnetron sputtering power to 150 W, use 99.99% high-purity Ar as the sputtering gas, and control the Ar flow rate to be 30 sccm;

[0121] G2) Sputter a p-type Cu2O thin film layer with a thickness of 10 nm and a doping concentration of 5×10 - on the p-type Cu2O thin film layer, where the process conditions of the magnetron sputtering technology are as follows: 19 cm -3 Select 99.99% high-purity Cu2O doped with Li element as the target material, set the magnetron sputtering power to 150 W, use 99.99% high-purity Ar as the sputtering gas, and control the Ar flow rate to be 10 sccm; + Select 99.99% high-purity Cu2O doped with Li element as the target material, set the magnetron sputtering power to 150 W, use 99.99% high-purity Ar as the sputtering gas, and control the Ar flow rate to be 10 sccm;

[0122] Select 99.99% high-purity Cu2O doped with Li element as the target material, set the magnetron sputtering power to 150 W, use 99.99% high-purity Ar as the sputtering gas, and control the Ar flow rate to be 10 sccm;

[0123] G3) Remove the photoresist on the sputtered sample and anneal it in an oxygen atmosphere at 400 °C for 30 minutes to improve the crystallinity and stability of the thin film.

[0124] Step H, fabricate the base electrode, as Figure 4 (h).

[0125] H1) Photolithograph the preset base electrode region on the surface of the p + Cu2O thin film. Sequentially deposit 60 nm of Ni and 200 nm of Au in this region by the EBM process. After the metal deposition is completed, immerse the sample in an acetone solution for lift-off and soak it in an NMP solution for 1 minute to remove the photoresist.

[0126] H2) Ultrasonically clean the sample in acetone, absolute ethanol solution, and deionized water for 5 minutes respectively, then dry it with high-purity N2 to form the base electrode; and thermally anneal it at 450 °C with a nitrogen flow rate of 3 L / min for 1 minute to form a good ohmic contact.

[0127] Step I, fabricate the insulating gate dielectric layer using the ALD process, as Figure 4 (i).

[0128] Deposit 50 nm of Al2O3 on the surface of the sample by atomic layer deposition (ALD) to form the insulating gate dielectric layer. The ALD deposition process conditions are as follows:

[0129] Use trimethylaluminum (TMA) as the aluminum source and H2O as the oxygen source. The reaction chamber temperature is 400 °C, and the growth rate is 0.1 nm / cycle.

[0130] Step J, fabricate the gate electrode, as Figure 4 (j).

[0131] J1) Photolithograph the preset gate electrode region on the surface of the insulating gate dielectric layer. Sequentially deposit 60 nm of Ni and 200 nm of Au in this region by the EBM process. After the metal deposition is completed, immerse the sample in an acetone solution for lift-off and soak it in an NMP solution for 1 minute to remove the photoresist.

[0132] J2) Ultrasonically clean the sample in acetone, absolute ethanol solution, and deionized water for 5 minutes respectively, then dry it with high-purity N2 to form the gate electrode.

[0133] Step K, open holes, as Figure 4 (k).

[0134] K1) Photolithographically define the source / drain / base electrode regions on the insulating gate dielectric layer;

[0135] K2) The source / drain / base regions are dry etched using the reactive ion etching (RIE) method to expose the ohmic contact metal in the source / drain / base regions, and the device fabrication is completed. The process conditions for the RIE etching are as follows:

[0136] The chamber pressure is 5.0 Pa, the power of the plasma is 150 W, and the flow rates of BCl3 and Ar are 30 sccm and 20 sccm, respectively.

[0137] The above description is only three specific examples of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various parameter corrections and changes in form and details may be made without departing from the principle and structure of the present invention. For example, in addition to the acceptor elements Mg and Fe used in this example for the semi-insulating substrate, deep-level defects can also be formed by introducing them; in addition to NiO, MnO, and Cu2O used in this example for the P-type material in the superjunction structure, semiconductor materials such as CoO can also be used; in addition to the RF magnetron sputtering process used in this example for the formation of the double-layer P-type thin film, it can also be formed by the conventional sol-gel method process; in addition to MOCVD used in this example for the preparation process of the Ga2O3 buffer layer, hydride vapor phase epitaxy (HVPE) or molecular beam epitaxy (MBE) can also be used. However, these corrections and changes based on the idea of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A MOSFET device with a gallium oxide superjunction structure, comprising: A substrate (1), a Ga2O3 buffer layer (2), a barrier layer (3), a P-type thin film layer (4), an insulating gate dielectric layer (5), a source electrode (6), a drain electrode (7), a gate electrode (8), and a base electrode (9), characterized in that: The barrier layer (3) includes two unintentionally doped AlGaO layers (31, 33) and one δ-doped AlGaO layer (32), and the δ-doped AlGaO layer (32) is located between the two unintentionally doped AlGaO layers (31, 33); The Ga2O3 buffer layer (2) is located below the barrier layer (3); The P-type thin film layer (4) includes two p-type thin film layers (41) and (42) with different doping concentrations, one on top of the other. + thin film layer (41) and p - thin film layer (42); The base electrode (9) is electrically connected to the gate electrode (8).

2. The device according to claim 1, characterized in that: The substrate (1) is located below the Ga2O3 buffer layer (2); The P-type thin film layer (4) is located above the barrier layer (3); The base electrode (9) is located on the upper surface of the P-type thin film layer (4); The source electrode (6) and the drain electrode (7) are respectively located at both ends of the Ga2O3 buffer layer (2); The gate electrode (8) is located between the source electrode (6) and the drain electrode (7), and an insulating gate dielectric layer (5) is provided below the gate electrode (8).

3. The device according to claim 1, characterized in that: The substrate (1) is made of semi-insulating β-Ga2O3 material doped with Mg or Fe, and the thickness is 2 - 3 μm; The Ga2O3 buffer layer (2) is made of β-Ga2O3 material, and the thickness is 400 nm - 1 μm; The P-type thin film layer (4) is made of any one of NiO, MnO, Cu2O, CoO materials; The insulating gate dielectric layer (5) is made of any one of Al2O3, SiO2, HfO2, SiN materials, and the thickness is 20 - 60 nm.

4. The device according to claim 1, characterized in that: The thickness of the unintentionally doped AlGaO layer (31) is 2 - 5 nm; The thickness of the unintentionally doped AlGaO layer (33) is 25 - 30 nm; The thickness of the δ-doped AlGaO layer (32) is 1 to 3 nm, and its doping material is Si or Ge, with a doping concentration of 3×10 18 ~2×10 19 cm -3 ; The p of the upper layer + thin film layer (41) with a thickness of 5 - 10 nm and a doping concentration of 3×10 19 - 8×10 19 cm -3 ; The p of the lower layer - thin film layer (42) with a thickness of 100 to 200 nm and a doping concentration of 10 17 to 10 18 cm -3 .

5. A manufacturing method of a MOSFET device with a gallium oxide superjunction structure, characterized in that, Comprises the following steps: S1) After epitaxially growing the Ga2O3 buffer layer (2) on the substrate layer (1) by using the MOCVD process, successively perform organic cleaning and deionized water cleaning, and dry with high-purity N2; S2) Using the MOCVD or MBE process, first deposit a first unintentionally doped AlGaO layer (31) on the surface of the cleaned sample, and then deposit a δ-doped AlGaO layer (32) with a doping concentration of 3×10 18 ~2×10 19 cm -3 to form a barrier layer (3) by depositing a second unintentionally doped AlGaO layer (33) on the δ-doped AlGaO layer; S3) By using the PECVD process, deposit a SiO2 layer as a regrowth mask on the surface of the sample deposited with the barrier layer, perform photolithography and etching on the regrowth mask layer until below the heterojunction interface, and remove the photoresist after etching is completed; S4) Using the MOCVD process, grow an n-type Ga2O3 layer with a doping concentration of 5×10 19 cm -3 as the source and drain regions in the etched area, and use wet etching to remove the regrowth mask; S5) By using the EBM process, deposit 30 - 60 nm / 100 - 200 nm thick Ti / Au on the source and drain regions, and then perform annealing in an N2 atmosphere at 400 - 500 °C to form the source electrode (6) and the drain electrode (7); S6) Lithography is performed on the sample for forming source and drain electrodes to form a sputtering region of the P-type thin film layer, and a p thin film layer (42) with a doping concentration of 10 17 ~10 18 cm -3 is first prepared on the surface of the sample by radio frequency magnetron sputtering technology, and then a p thin film layer (41) with a doping concentration of 3×10 - ~8×10 19 ~8×10 19 cm -3 is prepared; + ​ S7) At p + The base region is lithographed on the surface of the thin film layer (41). After depositing Ni / Au with a thickness of 30 - 60 nm / 100 - 200 nm on the base region by using the EBM process, annealing is then carried out in an N2 atmosphere at 400 - 500 °C to form the base (9). S8) By using the ALD process, deposit Al2O3 with a thickness of 20 - 60 nm on the surface of the sample after completing the operation of step S7) to form the insulating gate dielectric layer (5); S9) Lithographically pattern the gate region on the insulating gate dielectric layer (5). Using the EBM process, deposit Ni / Au with a thickness of 30 - 60 nm / 100 - 200 nm on the gate region. After metal lift-off, perform cleaning and blow dry with high-purity N2 to form the gate electrode (8). S10) Lithographically pattern the source / drain / base regions on the insulating gate dielectric layer (5). Use the RIE process to perform dry etching on the source / drain / base regions to expose the ohmic contact metal in the source / drain / base regions, and complete the device fabrication.

6. The method according to claim 5, characterized in that, For the MOCVD processes in steps S1) and S4), the condition parameters are set as follows: The reaction chamber temperature is 600 - 700 °C, and the growth pressure is 25 Torr. The organic sources are triethylgallium (TEGa) and oxygen (O2) to provide Ga element and O element. The flow rate of TEGa is 60 sccm. The flow rate of O2 is 2500 sccm.

7. The method according to claim 5, characterized in that For the MOCVD process in step S2), the condition parameters are set as follows: The reaction chamber temperature is 600 - 700 °C, and the growth pressure is 25 Torr. Use triethylgallium (TEGa), trimethylaluminum (TMAl), and oxygen (O2) as organic sources to provide Ga element, Al element, and O element. Use tetraethyl orthosilicate (TEOS) as the Si doping source. The flow rates of TEGa, TMAl, and O2 are 60 sccm, 25 sccm, and 2500 sccm respectively.

8. The method according to claim 5, characterized in that, For the etching in step S3), use the RIE process, and the condition parameters are set as follows: The RIE chamber pressure is 1.3 - 5.0 Pa. The power of the plasma is 100 W - 150 W. The flow rates of boron trichloride (BCl3) and argon (Ar) are 30 sccm and 20 sccm respectively.

9. The method according to claim 5, characterized in that, For realizing the P-type thin film layer in step S6) by magnetron sputtering technology, the condition parameters are set as follows: The growth environment is 0.6 Pa. The target material is a high-purity material of 99.9%. The RF power is 100 W - 150 W. The sputtering gas is Ar.

10. The method according to claim 5, characterized in that, For the ALD process in step S8), the condition parameters are set as follows: The reaction chamber temperature is 200 - 400 °C. Use trimethylaluminum (TMAl) and water (H2O) as organic sources to provide Al element and O element. The growth rate is 0.07 - 0.1 nm / cycle.

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