Semiconductor chip

Abstract

The invention provides a semiconductor chip. The semiconductor chip comprises a semiconductor crystal grain, a filling layer, a first electrode, a second electrode and a reflecting layer. The semiconductor crystal grain comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are stacked in sequence. The fill layer surrounds the semiconductor die. The first electrode is disposed on the first side of the semiconductor die and electrically connected to the first type semiconductor layer. The second electrode is disposed on the second side of the semiconductor die and electrically connected to the second type semiconductor layer. The second electrode includes a transparent conductive material. The reflecting layer is arranged on the filling layer. In a top view, a first virtual line segment penetrating a center of the semiconductor die and an edge of the filling layer intersect at a first point and a second point, and a distance between the center of the semiconductor die and the first point is different from a distance between the center of the semiconductor die and the second point. The semiconductor chip disclosed by the invention can change the luminous pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor chip, and more particularly to a semiconductor chip capable of changing a light emission pattern. Background Art

[0002] Electronic devices or spliced electronic devices have been widely used in different fields such as communication, display, automotive or aviation. With the booming development of electronic devices, electronic devices are developed towards being thinner and lighter, so the requirements for the reliability or quality of electronic devices are higher. Summary of the Invention

[0003] The present disclosure provides a semiconductor chip that can change a light emission pattern.

[0004] According to an embodiment of the present disclosure, the semiconductor chip includes a semiconductor die, a filling layer, a first electrode, a second electrode, and a reflective layer. The semiconductor die includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence. The filling layer surrounds the semiconductor die. The first electrode is disposed on a first side of the semiconductor die and electrically connected to the first-type semiconductor layer. The second electrode is disposed on a second side of the semiconductor die and electrically connected to the second-type semiconductor layer. The second electrode includes a transparent conductive material. The reflective layer is disposed on the filling layer. In a top view, a first virtual line segment passing through the center of the semiconductor die intersects the edge of the filling layer at a first point and a second point, and the distance between the center of the semiconductor die and the first point is different from the distance between the center of the semiconductor die and the second point.

[0005] According to an embodiment of the present disclosure, the semiconductor chip includes a semiconductor die, a filling layer, a first electrode, a second electrode, and a reflective layer. The semiconductor die includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence. The filling layer surrounds the semiconductor die. The first electrode is disposed on a first side of the semiconductor die and electrically connected to the first-type semiconductor layer. The second electrode is disposed on a second side of the semiconductor die and electrically connected to the second-type semiconductor layer. The second electrode includes a transparent conductive material. The reflective layer is disposed on the filling layer. In a top view, a first virtual line segment passing through the center of the semiconductor die intersects the edge of the filling layer at a first point, a second virtual line segment passing through the center of the semiconductor die intersects the edge of the filling layer at a third point, and the distance between the center of the semiconductor die and the first point is different from the distance between the center of the semiconductor die and the third point. Brief Description of the Drawings

[0006] The drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0007] Figure 1ATop view schematic diagram of the semiconductor chip according to the first embodiment of the present disclosure;

[0008] Figure 1B is Figure 1A Cross-sectional schematic diagram of the semiconductor chip along the section line I-I';

[0009] Figure 1C is Figure 1A Emission viewing angle diagram of the semiconductor chip;

[0010] Figure 2 Top view schematic diagram of the semiconductor chip according to the second embodiment of the present disclosure;

[0011] Figure 3A Top view schematic diagram of the semiconductor chip according to the third embodiment of the present disclosure;

[0012] Figure 3B is Figure 3A Emission viewing angle diagram of the semiconductor chip;

[0013] Figure 4 Top view schematic diagram of the semiconductor chip according to the fourth embodiment of the present disclosure;

[0014] Figure 5 Top view schematic diagram of the semiconductor chip according to the fifth embodiment of the present disclosure;

[0015] Figure 6 Top view schematic diagram of the semiconductor chip according to the sixth embodiment of the present disclosure;

[0016] Figure 7A Top view schematic diagram of the semiconductor chip according to the seventh embodiment of the present disclosure;

[0017] Figure 7B is Figure 7A Emission viewing angle diagram of the semiconductor chip;

[0018] Figure 8 Application of the electronic device according to an embodiment of the present disclosure.

[0019] Explanation of the reference numerals in the drawings

[0020] 10: Electronic device;

[0021] 100, 100a, 100b, 100c, 100d, 100e, 100f: Semiconductor chips;

[0022] 101, 101b, 102, 102b: Sides;

[0023] 110, 110a, 110b, 110c, 110d, 110e, 110f: Semiconductor dies;

[0024] 1101: First side;

[0025] 1102: Second side;

[0026] 1103, 123: Side surface;

[0027] 111: First-type semiconductor layer;

[0028] 112: Active layer;

[0029] 113: Second-type semiconductor layer;

[0030] 120, 120f: Filling layer;

[0031] 121: First surface;

[0032] 122: Second surface;

[0033] 125: Edge;

[0034] 130: First electrode;

[0035] 140: Second electrode;

[0036] 150: Reflective layer;

[0037] 151: First part;

[0038] 152: Second part;

[0039] 200: Windshield;

[0040] 300: Driver;

[0041] C1, C2: Center;

[0042] D1, D2, D3, D4: Distance;

[0043] D5, D6: Sum;

[0044] L: Normal line;

[0045] L1: First virtual line segment;

[0046] L2: Second virtual line segment;

[0047] P1: First point;

[0048] P2: Second point;

[0049] P3: Third point;

[0050] P4: Fourth point;

[0051] PAT1, PAT2, PAT3, PAT4, PAT5, PAT6: Pattern;

[0052] X, Y, Z: Directions;

[0053] θ1: Included angle;

[0054] θ2: Incident angle. Detailed implementation

[0055] This disclosure can be understood by referring to the following detailed description and simultaneously combining the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, only a part of the electronic device is shown in the multiple drawings of this disclosure, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of this disclosure.

[0056] In the following specification and claims, words such as "comprising" and "including" are open-ended terms, and thus should be interpreted as meaning "including but not limited to...".

[0057] It should be understood that when an element or film layer is said to be "on" or "connected to" another element or film layer, it can be directly on this other element or film layer or directly connected to this other element or layer, or there are intervening elements or film layers between them (non-direct situation). On the contrary, when an element is said to be "directly" "on" another element or film layer or "directly connected to" another element or film layer, there are no intervening elements or film layers between them.

[0058] Although terms such as "first", "second", "third",... can be used to describe various component elements, the component elements are not limited to these terms. This term is only used to distinguish a single component element in the specification from other component elements. The same terms may not be used in the claims, and the first, second, third,... are used to replace them according to the order of the element declarations in the claims. Therefore, in the following specification, the first component element may be the second component element in the claims.

[0059] In the text, terms such as "about", "approximately", "substantially", "substantively" usually mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially", "substantively" can still be implied even without specific mention of "about", "approximately", "substantially", "substantively".

[0060] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect" and "interconnect", unless otherwise specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed therebetween. Moreover, these terms related to joining and connection may also include cases where both structures are movable, or both structures are fixed. In addition, the term "coupled" encompasses any direct and indirect means of electrical connection.

[0061] In some embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means may be used to measure the area, width, thickness, or height of each element, or the distance or spacing between elements. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structure image of the elements to be measured, and the area, width, thickness, or height of each element, or the distance or spacing between elements may be measured.

[0062] In this disclosure, semiconductor chips can be applied to electronic devices. The electronic devices can include display devices, light-emitting devices, backlight devices, virtual reality devices, augmented reality (AR) devices, antenna devices, sensing devices, splicing devices, or any combination thereof, but not limited thereto. The display device can be a non-self-emitting display or a self-emitting display according to requirements, and can be a color display or a monochrome display according to requirements. The antenna device can be a liquid crystal type antenna device or a non-liquid crystal type antenna device, the sensing device can be a sensing device for sensing capacitance, light, heat energy, or ultrasonic waves, and the splicing device can be a display splicing device or an antenna splicing device, but not limited thereto. The electronic components in the electronic device can include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode can include a light emitting diode (LED) or a photodiode. The light emitting diode can, for example, include an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but not limited thereto. The transistor can, for example, include a top gate thin film transistor, a bottom gate thin film transistor, or a dual gate thin film transistor, but not limited thereto. The electronic device can also include fluorescence materials, phosphor materials, quantum dot (QD) materials, or other suitable materials according to requirements, but not limited thereto. The electronic device can have peripheral systems such as a driving system, a control system, a light source system, etc. to support the display device, the antenna device, the wearable device (such as including an augmented reality or virtual reality device), the vehicle-mounted device (such as including an automotive windshield), or the splicing device. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. The following will illustrate the content of this disclosure with semiconductor chips in electronic devices, but this disclosure is not limited thereto.

[0063] It should be noted that, without departing from the spirit of this disclosure, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments in the following examples. As long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily mixed and used.

[0064] Now, reference will be made in detail to the exemplary embodiments of this disclosure, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same element symbols are used in the drawings and the description to represent the same or similar parts.

[0065] Figure 1A A top view schematic diagram of the semiconductor chip according to the first embodiment of the present disclosure. Figure 1B is Figure 1A A cross-sectional schematic diagram of the semiconductor chip along the section line I-I'. Figure 1C is Figure 1A The light-emitting view angle diagram of the semiconductor chip. For the clarity and convenience of the drawings, Figure 1A Some elements in the semiconductor chip 100 are omitted from being shown.

[0066] Please refer to Figure 1A and Figure 1B The semiconductor chip 100 of the present embodiment includes a semiconductor die 110, a filling layer 120, a first electrode 130, a second electrode 140, and a reflective layer 150.

[0067] Specifically, please refer to Figure 1B The semiconductor die 110 has a first side 1101, a second side 1102, and a side surface 1103. The first side 1101 is opposite to the second side 1102, and the first side 1101 faces the first electrode 130. The second side 1102 is closer to the second electrode 140 than the first side 1101. The side surface 1103 connects the first side 1101 and the second side 1102. In the present embodiment, the semiconductor die 110 can be a vertical type chip. Among them, in the direction Z (for example, the normal direction of the semiconductor chip 100), the semiconductor die 110 includes a first-type semiconductor layer 111, an active layer 112, and a second-type semiconductor layer 113 stacked in sequence. The first-type semiconductor layer 111 is closer to the first electrode 130 than the second-type semiconductor layer 113, and the active layer 112 is disposed between the first-type semiconductor layer 111 and the second-type semiconductor layer 113.

[0068] In the present embodiment, the direction X, the direction Y, and the direction Z are different directions respectively. For example, the direction X is, for example, the extending direction of the section line I-I', the direction Z is, for example, the normal direction of the semiconductor chip 100, the direction X is perpendicular to the direction Z, and the direction X and the direction Z are respectively perpendicular to the direction Y, but not limited thereto.

[0069] In the present embodiment, the semiconductor die 110 can be a light-emitting element (for example: organic light-emitting diode, submillimeter light-emitting diode, micro light-emitting diode, or quantum dot light-emitting diode, but not limited thereto), and the active layer 112 can be a light-emitting layer, but not limited thereto. In the present embodiment, the first-type semiconductor layer 111 can be a P-type semiconductor layer, and the second-type semiconductor layer 113 can be an N-type semiconductor layer, but not limited thereto. In some embodiments, the first-type semiconductor layer can also be an N-type semiconductor layer, and the second-type semiconductor layer can also be a P-type semiconductor layer.

[0070] Please refer to Figure 1B , the filling layer 120 surrounds the semiconductor die 110. The filling layer 120 can contact the side surface 1103 of the semiconductor die 110. The filling layer 120 has a first surface 121, a second surface 122, and a side surface 123. The first surface 121 and the second surface 122 face each other, and the first surface 121 faces the first electrode 130. The second surface 122 is closer to the second electrode 140 than the first surface 121. The side surface 123 is located between the first surface 121 and the second surface 122, and the side surface 123 connects the first surface 121 and the second surface 122. In this embodiment, the included angle θ1 between the side surface 123 and the first surface 121 has an angle (taper angle), and the angle of the included angle θ1 can be between 90 degrees and 150 degrees, between 100 degrees and 170 degrees, between 110 degrees and 150 degrees, or between 120 degrees and 160 degrees, so that the filling layer 120 can be a bowl-like structure, and the filling layer 120 can be used in combination with the reflective layer 150 to concentrate the light emitted by the semiconductor die 110, reduce the light-emitting angle of the semiconductor die 110, or improve the light-emitting efficiency of the semiconductor die 110, but not limited thereto. In this embodiment, the material of the filling layer 120 can include acrylic-based, epoxy alkane-based, siloxane, silica, other transparent filling materials, or a combination of the foregoing, but not limited thereto.

[0071] Please refer to Figure 1A , in the top view of the semiconductor chip 100, the outline of the semiconductor die 110 can be square, and the outline of the filling layer 120 can be circular, but not limited thereto. That is, in the top view of the semiconductor chip 100, the lengths of two adjacent sides of the semiconductor die 110 (i.e., side 101 and side 102) are the same. In some embodiments not shown, the outline of the semiconductor die can also be other shapes, such as rectangular, hexagonal, circular, or elliptical. In some embodiments not shown, the outline of the filling layer can also be other shapes, such as elliptical.

[0072] Please refer to Figure 1A, in the top view of the semiconductor chip 100, the semiconductor die 110 has a center C1, the filling layer 120 has a center C2, and the center C1 of the semiconductor die 110 does not overlap with the center C2 of the filling layer 120 in the Z direction. Specifically, in the top view of the semiconductor chip 100, the first virtual line segment L1 can pass through the center C1 of the semiconductor die 110 and intersect the edge 125 of the filling layer 120 at a first point P1 and a second point P2, and the second virtual line segment L2 can pass through the center C1 of the semiconductor die 110 and intersect the edge 125 of the filling layer 120 at a third point P3 and a fourth point P4, and the second virtual line segment L2 can be perpendicular to the first virtual line segment L1. In this embodiment, the first virtual line segment L1 can be substantially parallel to the Y direction, and the second virtual line segment L2 can be substantially parallel to the X direction, but is not limited thereto.

[0073] In this embodiment, the position of the center C1 of the semiconductor die 110 can be offset relative to the position of the center C2 of the filling layer 120. Specifically, in the top view of the semiconductor chip 100, the distance D1 between the center C1 of the semiconductor die 110 and the first point P1 can be different from the distance D2 between the center C1 of the semiconductor die 110 and the second point P2, and the distance D3 between the center C1 of the semiconductor die 110 and the third point P3 can be substantially the same as the distance D4 between the center C1 of the semiconductor die 110 and the fourth point P4, but is not limited thereto. In this embodiment, the distance D1 is, for example, the minimum distance measured along the Y direction between the center C1 and the first point P1, the distance D2 is, for example, the minimum distance measured along the Y direction between the center C1 and the second point P2, the distance D3 is, for example, the minimum distance measured along the X direction between the center C1 and the third point P3, and the distance D4 is, for example, the minimum distance measured along the X direction between the center C1 and the fourth point P4.

[0074] In this embodiment, the distance D2 can be greater than the distance D1 (i.e., D1 < D2), and the ratio of the distance D2 to the distance D1 can be greater than 1 and less than or equal to 2 (i.e., 1 < D2 / D1 ≤ 2), but is not limited thereto.

[0075] Please refer to Figure 1B, the first electrode 130 is disposed on the first side 1101 of the semiconductor die 110. The first electrode 130 can be electrically connected to the first-type semiconductor layer 111 of the semiconductor die 110. In some embodiments, an ohmic contact layer (not shown) may be provided between the first electrode 130 and the first-type semiconductor layer 111, and the ohmic contact layer may include transparent conductive oxides (TCO). In this embodiment, the material of the first electrode 130 may include a conductive material having high reflection characteristics, so that the first electrode 130 can be used to concentrate the light emitted by the semiconductor die 110, reduce the light-emitting angle of the semiconductor die 110, or improve the light-emitting efficiency of the semiconductor die 110.

[0076] Please refer to Figure 1B , the second electrode 140 is disposed on the second side 1102 of the semiconductor die 110 and the second surface 122 of the filling layer 120. The second electrode 140 can be connected to the reflective layer 150. The second electrode 140 can be electrically connected to the second-type semiconductor layer 113 of the semiconductor die 110. In some embodiments, an ohmic contact layer (not shown) may be provided between the second electrode 140 and the second-type semiconductor layer 113, and the ohmic contact layer may include transparent conductive oxides. In this embodiment, the material of the second electrode 140 may include a transparent conductive material, and the transparent conductive material may include metal oxides, graphene, other suitable transparent conductive materials, or a combination of the above, but is not limited thereto. Among them, the metal oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other metal oxides. As another option, the transparent conductive material may include a thin metal or a metal grid. For example, a thin metal layer (e.g., a magnesium layer or a silver layer) may be formed, or a metal grid layer having light-transmitting openings may be formed by screen printing or other patterning processes, so that light can pass through the transparent conductive layer.

[0077] Please refer to Figure 1B, a reflective layer 150 is disposed on the filling layer 120, and the reflective layer 150 and the first electrode 130 are separated from each other. The reflective layer 150 includes a first portion 151 and a second portion 152. The first portion 151 is disposed on the side surface 123 of the filling layer 120, and the second portion 152 is disposed on the first surface 121 of the filling layer 120. One side of the first portion 151 can be connected to the second electrode 140, and the other side of the first portion 151 can be connected to the second portion 152; thus, the second portion 152 can be electrically connected to the second-type semiconductor layer 113 of the semiconductor die 110 through the first portion 151 and the second electrode 140. In this embodiment, the material of the reflective layer 150 can include a conductive material with high reflection characteristics, so that the reflective layer 150 can be used to concentrate the light emitted from the semiconductor die 110, reduce the light-emitting angle of the semiconductor die 110, or improve the light-emitting efficiency of the semiconductor die 110. In this embodiment, the material of the reflective layer 150 can include silver, aluminum, tin, indium, gold, or a combination of the above, but is not limited thereto.

[0078] In this embodiment, since the first-type semiconductor layer 111 and the second-type semiconductor layer 113 of the vertical semiconductor die 110 can be electrically connected to the first electrode 130 and the second portion 152 of the reflective layer 150 respectively, and the first electrode 130 and the second portion 152 can be disposed on the same side (or on the same horizontal plane) of the semiconductor chip 100, the semiconductor chip 100 can be a vertical embedded flip-chip (VEFC), and the semiconductor chip 100 can be easily detected and subjected to mass transfer.

[0079] Please refer to Figure 1C , in the light-emitting view angle diagram of the semiconductor chip 100, the meridians represent the angles of the view angle, and the unit of the angle is degree (°); the latitudes represent the luminous intensity, and the unit of the luminous intensity is candela (cd); the pattern PAT1 is the light-emitting situation or light-emitting pattern observed by the semiconductor chip 100 in the direction Y, and the pattern PAT2 is the light-emitting situation or light-emitting pattern observed by the semiconductor chip 100 in the direction X.

[0080] Specifically, please refer to both Figure 1B and Figure 1C, since the distance D1 is different from the distance D2, when the positive view angle (0 - degree view angle) is used as the axis of symmetry, the light emission pattern of the pattern PAT1 is asymmetric; wherein, in the pattern PAT1, the maximum light intensity does not appear at the positive view angle but at the side view angle (for example, at about 10 - degree view angle). In addition, since the distance D3 is approximately the same as the distance D4, when the positive view angle (0 - degree view angle) is used as the axis of symmetry, the light emission pattern of the pattern PAT2 is symmetric; wherein, in the pattern PAT2, the maximum light intensity appears at the positive view angle rather than at the side view angle.

[0081] It can be known from this that when the distance D1 between the center C1 of the semiconductor die 110 and the first point P1 is different from the distance D2 between the center C1 of the semiconductor die 110 and the second point P2 (or when the position of the center C1 of the semiconductor die 110 is offset relative to the position of the center C2 of the filling layer 120), the light emission pattern of the semiconductor chip 100 can be changed (that is, the pattern PAT1 is different from the pattern PAT2), so that the electronic device containing the semiconductor chip 100 can have better light intensity or brightness at a specific view angle.

[0082] Other embodiments will be listed below for illustration. It must be noted here that the following embodiments follow the component numbers and some content of the previous embodiments, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the previous embodiments, and the following embodiments will not be repeated.

[0083] Figure 2 A top - view schematic diagram of the semiconductor chip according to the second embodiment of the present disclosure. Please also refer to Figure 2 and Figure 1A , the semiconductor chip 100a of this embodiment is similar to the semiconductor chip 100 of Figure 1A , but the difference between the two is that: in the top - view of the semiconductor chip 100a of this embodiment, the distance D3 between the center C1 of the semiconductor die 110a and the third point P3 is different from the distance D4 between the center C1 of the semiconductor die 110a and the fourth point P4. In this embodiment, the distance D4 can be greater than the distance D3 (that is, D3 < D4), and the ratio of the distance D4 to the distance D3 can be greater than 1 and less than or equal to 2 (that is, 1 < D4 / D3 ≤ 2), but it is not limited thereto.

[0084] Figure 3A A top - view schematic diagram of the semiconductor chip according to the third embodiment of the present disclosure. Figure 3B is Figure 3A the light - emitting view - angle diagram of the semiconductor chip of Figures 3A to 3B and please also refer to Figures 1A to 1C , the semiconductor chip 100b of this embodiment is the same asFigure 1A is similar to the semiconductor chip 100, except that in the top view of the semiconductor chip 100b in this embodiment, the contour of the semiconductor die 110b is rectangular, and the center C1 of the semiconductor die 110b overlaps with the center C2 of the filling layer 120 in the Z direction.

[0085] Specifically, please refer to Figure 3A , in the top view of the semiconductor chip 100b, the distance D1 between the center C1 of the semiconductor die 110b and the first point P1 is substantially the same as the distance between the center C1 of the semiconductor die 110b and the second point P2, and the distance D3 between the center C1 of the semiconductor die 110b and the third point P3 is substantially the same as the distance D4 between the center C1 of the semiconductor die 110b and the fourth point P4.

[0086] In this embodiment, in the top view of the semiconductor chip 100b, the lengths of two adjacent sides (i.e., side 101b and side 102b) of the semiconductor die 110b are different. Among them, side 101b can be the long side of the rectangle and can be substantially parallel to the Y direction, side 102b can be the short side of the rectangle and can be substantially parallel to the X direction, and the length of side 101b can be greater than the length of side 102b, but it is not limited thereto.

[0087] Please refer to Figure 3B , the pattern PAT3 is the light emission situation or light emission pattern observed from the Y direction of the semiconductor chip 100b, and the pattern PAT4 is the light emission situation or light emission pattern observed from the X direction of the semiconductor chip 100b.

[0088] Specifically, please refer to Figure 3A and Figure 3B simultaneously. Since the distance D1 is substantially the same as the distance D2, and the distance D3 is substantially the same as the distance D4, in the case where the positive view (0-degree view) is used as the axis of symmetry, the light emission patterns of the pattern PAT3 and the pattern PAT4 are both symmetric. In addition, although the maximum light intensity of both the pattern PAT3 and the pattern PAT4 does not appear at the positive view but at the side view, since the contour of the semiconductor die 110b is rectangular, the maximum light intensity of the pattern PAT3 and the pattern PAT4 respectively appears at about 10 degrees to 30 degrees and about 10 degrees.

[0089] Accordingly, it can be known that when the lengths of the adjacent sides 101b and 102b of the semiconductor die 110b are different, the light emission pattern of the semiconductor chip 100b can be changed (i.e., the pattern PAT3 is different from the pattern PAT4), so that the electronic device containing the semiconductor chip 100b can have better light intensity or brightness at a specific viewing angle.

[0090] Figure 4 A top view schematic diagram of the semiconductor chip according to the fourth embodiment of the present disclosure. Please refer to Figure 4 and Figure 3A simultaneously. The semiconductor chip 100c of this embodiment is similar to the semiconductor chip 100b of Figure 3A , except that in the top view of the semiconductor chip 100c of this embodiment, the contour of the semiconductor die 110c is circular.

[0091] Figure 5 A top view schematic diagram of the semiconductor chip according to the fifth embodiment of the present disclosure. Please refer to Figure 5 and Figure 3A simultaneously. The semiconductor chip 100d of this embodiment is similar to the semiconductor chip 100b of Figure 3A , except that in the top view of the semiconductor chip 100d of this embodiment, the contour of the semiconductor die 110d is hexagonal.

[0092] Figure 6 A top view schematic diagram of the semiconductor chip according to the sixth embodiment of the present disclosure. Please refer to Figure 6 and Figure 3A simultaneously. The semiconductor chip 100e of this embodiment is similar to the semiconductor chip 100b of Figure 3A , except that in the top view of the semiconductor chip 100e of this embodiment, the contour of the semiconductor die 110e is oval.

[0093] Figure 7A A top view schematic diagram of the semiconductor chip according to the seventh embodiment of the present disclosure. Figure 7B is Figure 7A a light-emitting view of the semiconductor chip of. Please refer to Figures 7A to 7B and Figures 3A to 3B simultaneously. The semiconductor chip 100f of this embodiment is similar to the semiconductor chip 100b of Figure 1A , except that in the top view of the semiconductor chip 100f of this embodiment, the contour of the semiconductor die 110f is square, and the contour of the filling layer 120f is oval.

[0094] Specifically, please refer to Figure 7A, since the contour of the filling layer 120f is oval, the sum D5 of the distance D1 and the distance D2 (i.e., the length of the filling layer 120f measured along the direction Y) is different from the sum D6 of the distance D3 and the distance D4 (i.e., the length of the filling layer 120f measured along the direction X). That is to say, although the center C1 of the semiconductor die 110f can overlap with the center C2 of the filling layer 120f in the direction Z, due to the oval contour of the filling layer 120f, the distance D1 between the center C1 of the semiconductor die 110f and the first point P1 is different from the distance D3 between the center C1 of the semiconductor die 110f and the third point P3 (or different from the distance D4 between the center C1 of the semiconductor die 110f and the fourth point P4).

[0095] In this embodiment, the distance D1 can be greater than the distance D3 (i.e., D3 < D1), the distance D2 can be greater than the distance D4 (i.e., D4 < D2), and the ratio of the sum D5 to the sum D6 can be greater than 1 and less than or equal to 3 (i.e., 1 < D5 / D6 ≤ 3), but it is not limited thereto. In addition, in this embodiment, since the center C1 of the semiconductor die 110f can overlap with the center C2 of the filling layer 120f in the direction Z, the distance D1 is equal to the distance D2, and the distance D3 is equal to the distance D4, but it is not limited thereto.

[0096] Please refer to Figure 7B , the pattern PAT5 is the light emission situation or light emission pattern observed from the direction Y of the semiconductor chip 100f, and the pattern PAT6 is the light emission situation or light emission pattern observed from the direction X of the semiconductor chip 100f.

[0097] Specifically, please refer to Figure 7A and Figure 7B , since the distance D1 is substantially the same as the distance D2, and the distance D3 is substantially the same as the distance D4, in the case where the positive view (0-degree view) is used as the axis of symmetry, the light emission patterns of the pattern PAT5 and the pattern PAT6 are both symmetric. In addition, although the maximum light intensity of the pattern PAT5 and the pattern PAT6 does not appear at the positive view but at the side view, due to the oval contour of the filling layer 120f, the maximum light intensities of the pattern PAT5 and the pattern PAT6 appear at approximately 15-degree view and approximately 5-degree view, respectively.

[0098] It can be known therefrom that when the distance D1 between the center C1 of the semiconductor die 110f and the first point P1 is different from the distance D3 between the center C1 of the semiconductor die 110f and the third point P3 (or when the length measured along the direction Y of the filling layer 120f is different from the length measured along the direction X of the filling layer 120f), the light emission pattern of the semiconductor chip 100f can be changed (i.e., the pattern PAT5 is different from the pattern PAT6), so that the electronic device containing the semiconductor chip 100f can have better light intensity or brightness at a specific viewing angle, or so that the electronic device containing the semiconductor chip 100f can have different viewable viewing angle ranges in different viewing directions.

[0099] Figure 8 This is the application of the electronic device according to an embodiment of the present disclosure. Please refer to Figure 8 , the electronic device 10 of this embodiment can be a vehicle-mounted head-up display (HUD) or a panoramic head-up display (PHUD), but is not limited thereto.

[0100] In this embodiment, the electronic device 10 may include the semiconductor chip 100 as shown in Figures 1A to 1B , the semiconductor chip 100a as shown in Figure 2 , the semiconductor chip 100b as shown in Figure 3A , the semiconductor chip 100c as shown in Figure 4 , the semiconductor chip 100d as shown in Figure 5 , the semiconductor chip 100e as shown in Figure 6 , or the semiconductor chip 100f as shown in Figure 7A , thereby providing better light intensity or brightness at a specific viewing angle, providing highly concentrated light, providing high-brightness light, or reducing the influence of external ambient light.

[0101] In this embodiment, relative to the normal line L of the windshield 200, the screen of the electronic device 10 can be projected onto the windshield 200 at an incident angle θ2 of, for example, 30 degrees to 70 degrees, so that the driver 300 can see the screen of the electronic device 10 from the windshield 200.

[0102] In summary, in the semiconductor chip of the embodiment of the present disclosure, by making the distance between the center of the semiconductor die and the first point different from the distance between the center of the semiconductor die and the second point, making the lengths of adjacent sides of the semiconductor die different, or making the distance between the center of the semiconductor die and the first point different from the distance between the center of the semiconductor die and the third point, the light emission pattern of the semiconductor chip can be changed, and further, the electronic device containing the semiconductor chip can have better light intensity or brightness at a specific viewing angle.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor chip, characterized in that, Comprising: A semiconductor grain including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence; A filling layer surrounding the semiconductor grain; A first electrode disposed on a first side of the semiconductor grain and electrically connected to the first-type semiconductor layer; A second electrode disposed on a second side of the semiconductor grain and electrically connected to the second-type semiconductor layer, wherein the second electrode includes a transparent conductive material; And A reflective layer disposed on the filling layer, wherein, in a top view, a first virtual line segment passing through the center of the semiconductor grain intersects the edge of the filling layer at a first point and a second point, and the distance between the center of the semiconductor grain and the first point is different from the distance between the center of the semiconductor grain and the second point.

2. The semiconductor chip according to claim 1, characterized in that, In the top view, a second virtual line segment passing through the center of the semiconductor grain intersects the edge of the filling layer at a third point and a fourth point, the second virtual line segment is perpendicular to the first virtual line segment, and the distance between the center of the semiconductor grain and the third point is different from the distance between the center of the semiconductor grain and the fourth point.

3. The semiconductor chip according to claim 1, characterized in that, In the top view, the contour of the semiconductor grain is square, rectangular, hexagonal, circular or oval.

4. The semiconductor chip according to claim 1, characterized in that, In the top view, the contour of the filling layer is circular or oval.

5. The semiconductor chip according to claim 1, characterized in that, The center of the semiconductor grain does not overlap with the center of the filling layer.

6. A semiconductor chip, characterized in that, Comprising: A semiconductor grain including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer stacked in sequence; A filling layer surrounding the semiconductor grain; A first electrode disposed on a first side of the semiconductor grain and electrically connected to the first-type semiconductor layer; A second electrode disposed on a second side of the semiconductor grain and electrically connected to the second-type semiconductor layer, wherein the second electrode includes a transparent conductive material; And A reflective layer disposed on the filling layer, wherein, in a top view, a first virtual line segment passing through the center of the semiconductor grain intersects the edge of the filling layer at a first point, a second virtual line segment passing through the center of the semiconductor grain intersects the edge of the filling layer at a third point, and the distance between the center of the semiconductor grain and the first point is different from the distance between the center of the semiconductor grain and the third point.

7. The semiconductor chip according to claim 6, wherein, In the top view, the lengths of two adjacent sides of the semiconductor grain are different.

8. The semiconductor chip according to claim 6, wherein In the top view, the contour of the semiconductor grain is square, rectangular, hexagonal, circular or oval.

9. The semiconductor chip according to claim 6, characterized in that, In the top view, the contour of the filling layer is oval.

10. The semiconductor chip according to claim 6, characterized in that, The center of the semiconductor grain overlaps with the center of the filling layer.

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