Method for superconducting communication TiN etching

Abstract

The application discloses a superconducting communication TiN etching method, which comprises the following steps: depositing a sacrificial layer on the surface of a silicon substrate, coating photoresist on the sacrificial layer, exposing a first target pattern, etching the exposed sacrificial layer by using plasma etching, detecting whether the interface characteristic spectrum line between the silicon substrate and the sacrificial layer appears during etching in real time, removing the remaining photoresist when the interface characteristic between the silicon substrate and the sacrificial layer appears during etching, depositing a TiN layer after the remaining photoresist is removed, coating photoresist on the TiN layer, exposing a second target pattern, etching the exposed TiN layer by using plasma etching, detecting whether the interface characteristic spectrum line between the sacrificial layer and the TiN layer appears during etching in real time, removing the remaining photoresist when the interface characteristic spectrum line between the sacrificial layer and the TiN layer appears during etching, removing the remaining sacrificial layer after the remaining photoresist is removed, obtaining a semiconductor composed of the silicon substrate and the TiN layer, protecting the silicon substrate by using the sacrificial layer, and improving superconducting performance.

Description

Technical Field

[0001] This invention relates to the field of superconducting quantum computing technology, and in particular to a method for etching superconducting connected TiN. Background Technology

[0002] TiN thin films exhibit superconductivity at a specific critical temperature, displaying zero resistance and enabling lossless current transmission. TiN grown on Si substrates using the ALD process exhibits good step coverage and excellent uniformity, making it suitable for patterning and application in superconducting quantum chips.

[0003] TiN thin film patterning transfer processes include plasma etching and ion beam etching. Ion beam etching has a slow etching rate and can damage the underlying material. Plasma etching, on the other hand, uses chlorine- or fluorine-based gases combined with plasma to etch TiN, resulting in a faster etching rate. However, these two gases typically exhibit poor selectivity and uniformity towards TiN and Si, leading to partial etching of the silicon substrate and affecting the performance of superconducting quantum chips. Furthermore, chlorine is a hazardous gas, posing potential dangers to the environment and personnel, and the removal of residual chlorides after etching is complex.

[0004] Therefore, how to improve the etching process of TiN thin films to reduce etching complexity has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a method for etching superconducting connected TiN films to address the problem of how to improve the etching process of TiN films and reduce etching complexity.

[0006] This invention provides a method for etching superconducting connected TiN, comprising: A sacrificial layer is deposited on the surface of a silicon substrate, and photoresist is coated on the sacrificial layer to obtain a first photoresist layer. Exposure is performed on the first photoresist layer to expose a first target pattern. Plasma etching is used to etch the exposed sacrificial layer, and the appearance of interface feature spectral lines between the silicon substrate and the sacrificial layer is detected in real time. When the appearance of interface features between the silicon substrate and the sacrificial layer is detected, the remaining photoresist is removed. After removing the remaining photoresist, a TiN layer is deposited, and photoresist is coated on the TiN layer to obtain a second photoresist layer. Exposure is performed on the second photoresist layer to expose the second target pattern. The exposed TiN layer is etched using plasma etching. The appearance of interface feature spectral lines between the sacrificial layer and the TiN layer during etching is detected in real time. When interface feature spectral lines between the sacrificial layer and the TiN layer are detected during etching, the remaining photoresist is removed. After removing the remaining photoresist, the remaining sacrificial layer is removed to obtain a semiconductor consisting of the silicon substrate and the TiN layer.

[0007] Optionally, the sacrificial layer is SiO2, the thickness of the sacrificial layer is 100nm-300nm, and the deposition temperature of the sacrificial layer is 250°C-300°C.

[0008] Optionally, the etching of the exposed sacrificial layer using plasma etching includes: The exposed sacrificial layer is etched using an ICP plasma etching system. The gas ratio in the ICP plasma etching system is CHF3 / O2=6:1, the total flow rate is controlled at 35-100 sccm, the RF power is 500-1000W for the upper electrode and 10-50W for the lower electrode, the chamber pressure is 5-20 mTorr, and the substrate temperature is 20-50℃.

[0009] Optionally, the ICP plasma etching system is equipped with a cooling system using He as the back-cooling gas.

[0010] Optionally, the etching of the exposed TiN layer using plasma etching includes: The exposed sacrificial layer is etched using the ICP plasma etching system, wherein the gas ratio in the ICP plasma etching system is CF4 / Ar=1:1, the total flow rate is controlled at 50-100 sccm, the RF power is 500-8000W for the upper electrode and 40-100W for the lower electrode, the chamber pressure is 4-10 mTorr, and the substrate temperature is 0-20℃.

[0011] Optionally, the etching of the exposed sacrificial layer using the ICP plasma etching system includes: Using the ICP plasma etching system, the exposed sacrificial layer is etched based on an etching selectivity ratio of 1:1 between the sacrificial layer and the TiN layer.

[0012] Optionally, removing the remaining sacrificial layer includes: The SiO2 sacrificial layer was selectively removed using a fully automated single-wafer wet etching system. The wet etching solution was 49% DHF, the etching rate was 20 nm / s, and the etching time was controlled at 5-10 s.

[0013] Optionally, after removing the remaining sacrificial layer, the process further includes: The surface roughness of the silicon substrate was detected by SEM and AFM, and the roughness was controlled to be Rq < 0.5 nm and Rz < 5 nm.

[0014] Optionally, the thickness of the deposited TiN layer is 100 nm.

[0015] Optionally, the removal of residual photoresist includes: The remaining photoresist was removed using a fully automated single-wafer wet etching system. The photoresist stripping solution was DMSO, and the time was controlled to be 15 minutes.

[0016] The technical advantages of this invention compared to existing technologies are as follows: This invention deposits a sacrificial layer on a silicon substrate surface, coats the sacrificial layer with photoresist to obtain a first photoresist layer, exposes the first photoresist layer to reveal a first target pattern, uses plasma etching to etch the exposed sacrificial layer, and monitors in real time whether interface feature lines between the silicon substrate and the sacrificial layer appear during etching. When interface features between the silicon substrate and the sacrificial layer are detected, the remaining photoresist is removed. After removing the remaining photoresist, a TiN layer is deposited, and photoresist is coated on the TiN layer to obtain a second photoresist layer. The second photoresist layer is then... The first step involves exposure of the second photoresist layer to reveal the second target pattern. Plasma etching is then used to etch the exposed TiN layer. The presence of interface characteristic spectral lines between the sacrificial layer and the TiN layer is monitored in real time. When these spectral lines are detected, the remaining photoresist is removed. After removing the remaining photoresist, the remaining sacrificial layer is removed, resulting in a semiconductor composed of a silicon substrate and a TiN layer. The sacrificial layer protects the silicon substrate, improving superconductivity. The synergy of deposition, exposure, and etching processes, along with the use of plasma etching parameters, enhances the precision of the final TiN layer. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of an embodiment of the present invention for etching superconducting interconnected TiN. Figure 2 This is a schematic diagram of a process for etching superconducting connected TiN according to an embodiment of the present invention. Detailed Implementation

[0019] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] like Figure 1 The diagram shown is a flowchart of a method for etching superconducting connected TiN according to Embodiment 1 of the present invention. This method may include the following steps: Step S101: A sacrificial layer is deposited on the surface of a silicon substrate, and photoresist is coated on the sacrificial layer to obtain a first photoresist layer. Exposure is performed on the first photoresist layer to expose a first target pattern.

[0021] Step S102: Use plasma etching to etch the exposed sacrificial layer, and detect in real time whether the etching produces interface feature spectral lines between the silicon substrate and the sacrificial layer. When the etching produces interface features between the silicon substrate and the sacrificial layer, remove the remaining photoresist.

[0022] Step S103: After removing the remaining photoresist, deposit a TiN layer, coat the TiN layer with photoresist to obtain a second photoresist layer, and expose the second photoresist layer to expose the second target pattern.

[0023] Step S104: Use plasma etching to etch the exposed TiN layer, and detect in real time whether the interface feature spectral lines between the sacrificial layer and the TiN layer appear during etching. When the interface feature spectral lines between the sacrificial layer and the TiN layer are detected during etching, remove the remaining photoresist.

[0024] Step S105: After removing the remaining photoresist, remove the remaining sacrificial layer to obtain a semiconductor composed of the silicon substrate and the TiN layer.

[0025] Optionally, the sacrificial layer is SiO2, the thickness of the sacrificial layer is 100nm-300nm, and the deposition temperature of the sacrificial layer is 250°C-300°C.

[0026] Optionally, the etching of the exposed sacrificial layer using plasma etching includes: The exposed sacrificial layer is etched using an ICP plasma etching system. The gas ratio in the ICP plasma etching system is CHF3 / O2=6:1, the total flow rate is controlled at 35-100 sccm, the RF power is 500-1000W for the upper electrode and 10-50W for the lower electrode, the chamber pressure is 5-20 mTorr, and the substrate temperature is 20-50℃.

[0027] Optionally, the ICP plasma etching system is equipped with a cooling system using He as the back-cooling gas.

[0028] Optionally, the etching of the exposed TiN layer using plasma etching includes: The exposed sacrificial layer is etched using the ICP plasma etching system, wherein the gas ratio in the ICP plasma etching system is CF4 / Ar=1:1, the total flow rate is controlled at 50-100 sccm, the RF power is 500-8000W for the upper electrode and 40-100W for the lower electrode, the chamber pressure is 4-10 mTorr, and the substrate temperature is 0-20℃.

[0029] Optionally, the etching of the exposed sacrificial layer using the ICP plasma etching system includes: Using the ICP plasma etching system, the exposed sacrificial layer is etched based on an etching selectivity ratio of 1:1 between the sacrificial layer and the TiN layer.

[0030] Optionally, removing the remaining sacrificial layer includes: The SiO2 sacrificial layer was selectively removed using a fully automated single-wafer wet etching system. The wet etching solution was 49% DHF, the etching rate was 20 nm / s, and the etching time was controlled at 5-10 s.

[0031] Optionally, after removing the remaining sacrificial layer, the process further includes: The surface roughness of the silicon substrate was detected by SEM and AFM, and the roughness was controlled to be Rq < 0.5 nm and Rz < 5 nm.

[0032] Optionally, the thickness of the deposited TiN layer is 100 nm.

[0033] Optionally, the removal of residual photoresist includes: The remaining photoresist was removed using a fully automated single-wafer wet etching system. The photoresist stripping solution was DMSO, and the time was controlled to be 15 minutes.

[0034] This invention utilizes a SiO2 sacrificial layer to protect the Si substrate (including but not limited to SiO2), employs an environmentally friendly gas system for etching, and coordinates related processes such as deposition, exposure, and etching. High-precision plasma etching process parameters ensure the Si substrate surface roughness meets the Q-value requirements of superconducting quantum chips. TiN is used not only for superconducting connectivity but also as a barrier layer and anti-reflective coating in semiconductors. Compared to IBE etching, the etching rate is faster; compared to chlorine-based gas plasma etching, the use of fluorine-based gases poses no danger. The sacrificial layer protects the Si substrate from etching, improving superconducting performance and allowing for greater process window control to meet the requirements of superconducting quantum chips.

[0035] like Figure 2 The diagram shown is a schematic representation of a method for etching superconducting connected TiN according to an embodiment of the present invention. Details are as follows: (1) A 100-300 nm thick SiO2 sacrificial layer is deposited on the silicon substrate using the ICPPECVD process, with the deposition temperature controlled at 250-300℃ to ensure the film density; (2) Coat the photoresist (such as AZ1500) and expose the target pattern using a UV exposure machine; (3) An ICP plasma etching system is used, with a gas ratio of CHF3 / O2=6:1, a total flow rate of 35-100 sccm, RF power of 500-1000W for the upper electrode and 10-50W for the lower electrode, chamber pressure of 5-20 mTorr, and substrate temperature of 20-50℃ (equipped with a back He cooling system). The etching process is monitored in real time by an endpoint detection system, and the etching is terminated when the characteristic spectral lines of the SiO2 / Si interface are detected. (4) Use a fully automatic single-piece wet etching system to remove the adhesive. The adhesive removal solution is DMSO, and the time is controlled at 15 min. (5) A 100 nm thick TiN layer was deposited on the entire wafer (SiO2 region and Si substrate region after etching) using atomic layer deposition (ALD) process; (6) Coat with photoresist (such as AZ1500) and expose it with a UV exposure machine to etch the target pattern; (7) An ICP plasma etching system is used, with a gas ratio of CF4 / Ar=1:1, a total flow rate of 50-100 sccm, RF power of 500-8000W for the upper electrode and 40-100W for the lower electrode, chamber pressure of 4-10 mTorr, and substrate temperature of 0-20℃ (equipped with a back He cooling system). The etching process is monitored in real time by an endpoint detection system. The SiO2 sacrificial layer etching selectivity is 1:1 (TiN:SiO2). The etching is automatically terminated when the characteristic spectral lines of the TiN / SiO2 interface are detected. (8) Use a fully automated single-piece wet etching system to remove the adhesive. The adhesive removal solution is DMSO, and the time is controlled at 15 min. (9) Use a fully automated single-wafer wet etching system to selectively remove the SiO2 sacrificial layer. The wet etching solution is DHF (49%), the etching rate is 20 nm / s, and the time is controlled at 5-10 s. (10) The surface roughness of the Si substrate was controlled at Rq<0.5nm and Rz<5nm by SEM and AFM.

[0036] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for etching superconducting connected TiN, characterized in that, include: A sacrificial layer is deposited on the surface of a silicon substrate, and photoresist is coated on the sacrificial layer to obtain a first photoresist layer. Exposure is performed on the first photoresist layer to expose a first target pattern. Plasma etching is used to etch the exposed sacrificial layer, and the appearance of interface feature spectral lines between the silicon substrate and the sacrificial layer is detected in real time. When the appearance of interface features between the silicon substrate and the sacrificial layer is detected, the remaining photoresist is removed. After removing the remaining photoresist, a TiN layer is deposited, and photoresist is coated on the TiN layer to obtain a second photoresist layer. Exposure is performed on the second photoresist layer to expose the second target pattern. The first target image and the second target graphic are overlaid and aligned; The exposed TiN layer is etched using plasma etching. The appearance of interface feature spectral lines between the sacrificial layer and the TiN layer during etching is detected in real time. When interface feature spectral lines between the sacrificial layer and the TiN layer are detected during etching, the remaining photoresist is removed. After removing the remaining photoresist, the remaining sacrificial layer is removed to obtain a semiconductor consisting of the silicon substrate and the TiN layer.

2. The method for etching superconducting interconnected TiN according to claim 1, characterized in that, The sacrificial layer is SiO2, the thickness of the sacrificial layer is 100nm-300nm, and the deposition temperature of the sacrificial layer is 250°C-300°C.

3. The method for etching superconducting connected TiN according to claim 1, characterized in that, The etching of the exposed sacrificial layer using plasma etching includes: The exposed sacrificial layer is etched using an ICP plasma etching system. The gas ratio in the ICP plasma etching system is CHF3 / O2=6:1, the total flow rate is controlled at 35-100 sccm, the RF power is 500-1000W for the upper electrode and 10-50W for the lower electrode, the chamber pressure is 5-20 mTorr, and the substrate temperature is 20-50℃.

4. The method for etching superconducting interconnected TiN according to claim 3, characterized in that, The ICP plasma etching system is equipped with a cooling system using He as the back-cooling gas.

5. The method for etching superconducting interconnected TiN according to claim 3, characterized in that, The etching of the exposed TiN layer using plasma etching includes: The exposed TiN layer is etched using the ICP plasma etching system, wherein the gas ratio in the ICP plasma etching system is CF4 / Ar=1:1, the total flow rate is controlled at 50-100 sccm, the RF power is 500-8000W for the upper electrode and 40-100W for the lower electrode, the chamber pressure is 4-10 mTorr, and the substrate temperature is 0-20℃.

6. The method for etching superconducting interconnected TiN according to claim 5, characterized in that, The etching of the exposed TiN layer using the ICP plasma etching system includes: Using the ICP plasma etching system, the exposed TiN layer is etched based on an etching selectivity ratio of 1:1 between the sacrificial layer and the TiN layer.

7. The method for etching superconducting connected TiN according to claim 1, characterized in that, The removal of the remaining sacrificial layer includes: The SiO2 sacrificial layer was selectively removed using a fully automated single-wafer wet etching system. The wet etching solution was 49% DHF, the etching rate was 20 nm / s, and the etching time was controlled at 5-10 s.

8. The method for etching superconducting connected TiN according to claim 1, characterized in that, After removing the remaining sacrificial layer, the process further includes: The surface roughness of the silicon substrate was detected by SEM and AFM, and the roughness was controlled to be Rq < 0.5 nm and Rz < 5 nm.

9. The method for etching superconducting interconnected TiN according to claim 1, characterized in that, The thickness of the deposited TiN layer is 100 nm.

10. The method for etching superconducting connected TiN according to claim 1, characterized in that, The removal of residual photoresist includes: The remaining photoresist was removed using a fully automated single-wafer wet etching system. The photoresist stripping solution was DMSO, and the time was controlled to be 15 minutes.

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