Battery cell test system and multi-stage boost speed regulation control system

Abstract

The invention discloses a cell test system and a multistage boost speed regulation control system, the cell test system comprises a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switch circuit, a current measurement circuit, a voltage measurement circuit and a controller, the voltage output by the power supply circuit, the on-off state of the switching circuit and the working state of the bus output power modulation circuit are controlled according to the capacitance until the voltage at the two ends of the load to be measured reaches the set voltage, then the MOS tube Q7 and the MOS tube Q8 are controlled to be switched off, and the load to be measured is in a self-discharge state. When the voltage measuring circuit measures that the voltage of the to-be-measured load is higher than the second set voltage, the to-be-measured load is qualified, otherwise, the to-be-measured load is unqualified. The cell test system can effectively identify the size of the load and select a proper topological structure and boost speed according to the size of the load, so that the boost speed conforms to the load, and the technical problems of overshoot of a small load and low test efficiency of a large load are avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of cell testing, and specifically, relates to a cell testing system and a multi-stage boost speed control system. Background Art

[0002] With the popularization of new energy, lithium batteries are more and more widely used. Whether the quality of lithium batteries is qualified is directly related to safety issues. Therefore, it is necessary to test lithium batteries during the production process. In terms of structure, insulation should be maintained between the positive and negative electrodes of lithium-ion batteries, and between each electrode and the outer shell. In the production process of lithium-ion batteries, if metal foreign objects are mixed in or the separator is damaged, the insulation resistance will become lower. If the insulation state cannot be maintained, it will lead to a reduction in battery life or a fire accident.

[0003] To meet the needs of the electric vehicle industry, for the lithium-ion batteries installed in electric vehicles, it is required that the lithium-ion batteries have high energy density, can be charged with large current, have a long life, and are safe from catching fire. To achieve these characteristics, it is necessary to detect the performance of lithium-ion batteries during the production and manufacturing process. Currently, there are mainly two methods for testing lithium battery cells. The first method uses pulse testing. After charging the battery cell to a specified voltage, it stops, and then tests whether the battery voltage will drop rapidly. After reaching the test time, the cell is discharged. The second insulation testing method is to apply a specified voltage to the cell and then test its insulation resistance. Both of these testing methods use a high-voltage DC source, and have relatively high requirements for the voltage fluctuation of the high-voltage DC source output.

[0004] Before the lithium battery cell is filled with liquid, its equivalent model is a capacitor, and the capacitance values of equivalent capacitors of different capacities are different. The capacitance value of a small capacitor will cause overshoot of the high-voltage DC source output, and the voltage overshoot will cause a certain degree of damage to the cell. For a cell with a large capacitor, the boost speed is slow, which seriously affects the testing efficiency.

[0005] In addition, cells with the same capacity also have different performances at different boost speeds. When the cell is impacted by the instantaneous pulse method, the performance of metal ions on the internal separator under the action of a rapidly changing electric field force is also different.

[0006] The above information disclosed in this background art is only used to increase the understanding of the background art of the present application. Therefore, it may include prior art that is not known to those of ordinary skill in the art. Summary of the Invention

[0007] The present invention provides a cell testing system to solve the technical problems that the existing cell testing system causes overshoot of the high-voltage DC source output for small-capacitance cells, resulting in damage to the cells, and has low testing efficiency for large-capacitance cells.

[0008] To achieve the above-mentioned invention / design objectives, the present invention is implemented by the following technical solutions: A battery cell testing system, the battery cell testing system comprising: A power supply circuit; A bus output power modulation circuit, including a MOS transistor driver chip, MOS transistor Q7, MOS transistor Q8, capacitor C1 and capacitor C2; the gates of the MOS transistor Q7 and MOS transistor Q8 are connected to the MOS transistor driver chip, the source of the MOS transistor Q7 is connected to the drain of the MOS transistor Q8, and a series-connected capacitor C1 and C2 are connected between the drain of the MOS transistor Q7 and the source of the MOS transistor Q8; A transformer, the primary coil of the transformer is connected between the capacitor C1 and C2, and between the source of the MOS transistor Q7 and the drain of the MOS transistor Q8; A rectifier bridge, including diode D1, diode D2, diode D3 and diode D4, the positive electrode of the diode D1 and the negative electrode of the diode D3, and the positive electrode of the diode D2 and the negative electrode of the diode D4 are respectively connected to the secondary coil of the transformer; between the negative electrodes of the diode D1 and the diode D2, and between the positive electrodes of the diode D3 and the diode D4, a series-connected load under test C4 and resistor R2 are connected; A first switch circuit, connected to the power supply circuit, the drain of the MOS transistor Q7 and the capacitor C1; A second switch circuit, connected between the primary coil of the transformer, the capacitor C1 and the capacitor C2; A third switch circuit, connected to the power supply circuit, the primary coil of the transformer and the second switch circuit; A fourth switch circuit, connected between the positive electrode of the diode D2 and the negative electrode of the diode D4; A voltage measurement circuit, used to measure the voltage of the load under test C4; A current measurement circuit, used to measure the current flowing through the resistor R2; A controller, outputting control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, the third switch circuit, and receiving the signals of the voltage measurement circuit and the current measurement circuit; Controlling the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; controlling the power supply circuit to output a first voltage, controlling the MOS transistor Q8 to turn on and off according to a first duty cycle, receiving the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and timing t, and calculating the capacitance of the load under test C4; Control the voltage output by the power supply circuit according to the capacitance of the load C4 to be measured, and control the on / off states of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; control the working state of the bus output power modulation circuit until the voltage across the load C4 to be measured reaches the set voltage. After the voltage across the load C4 to be measured reaches the set voltage, control the MOS transistors Q7 and Q8 to turn off. The load C4 to be measured is in a self-discharging state. When the voltage measurement circuit measures that the voltage of the load C4 to be measured is higher than the second set voltage, it is determined that the load C4 to be measured is qualified; otherwise, it is unqualified. Wherein, the second set voltage is lower than the set voltage.

[0009] For the cell testing system as described above, the controller is configured to: When the capacitance of the load C4 to be measured is within the first capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to turn off, the second switch circuit to turn off, the third switch circuit to turn on, and the fourth switch circuit to turn off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load C4 to be measured reaches the set voltage. When the capacitance of the load C4 to be measured is within the second capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to turn on, the second switch circuit to turn on, the third switch circuit to turn off, and the fourth switch circuit to turn on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the first set voltage; control the first switch circuit to turn off, the second switch circuit to turn off, the third switch circuit to turn on, and the fourth switch circuit to turn off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load C4 to be measured reaches the set voltage. When the capacitance of the load C4 to be measured is within the third capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to turn on, the second switch circuit to turn on, the third switch circuit to turn off, and the fourth switch circuit to turn on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the set voltage. Wherein, the capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range. Wherein, the first set voltage is lower than the set voltage.

[0010] For the cell testing system as described above, the controller is configured to calculate C according to the formula where C is the capacitance of the load C4 to be measured, and t represents time.

[0011] The battery cell testing system as described above, the testing system comprising: A digital-to-analog converter connected to the controller; Comparator A2, whose non-inverting input terminal is connected to the digital-to-analog converter, inverting input terminal is connected to the voltage measurement circuit, and output terminal is connected to the fifth switch circuit; The fifth switch circuit is connected to the cathodes of the diodes D1 and D2 and the load under test C4; The overshoot prevention capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end is connected to the cathodes of the diodes D1 and D2 through the diode D6. The anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the overshoot prevention capacitor C3; The controller is configured to receive the maximum rising voltage set for each step, calculate the maximum value of the next voltage boost according to the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of comparator A2 controls the fifth switch circuit to disconnect, stopping charging the load under test C4 until the controller calculates the maximum value of the next voltage boost.

[0012] The battery cell testing system as described above, the system comprising: The first voltage measurement circuit is connected between the overshoot prevention capacitor C3 and the cathode of the diode D6; Comparator A1, whose non-inverting input terminal is connected to the digital-to-analog converter, inverting input terminal is connected to the first voltage measurement circuit, and output terminal is connected to the sixth switch circuit; The sixth switch circuit is connected to the resistor R1 and the anodes of the diodes D3 and D4. The resistor R1 is connected between the diode D6 and the overshoot prevention capacitor C3; When the voltage at the non-inverting input terminal of comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switch circuit to conduct, and the electric energy of the overshoot prevention capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switch circuit to disconnect.

[0013] The battery cell testing system as described above, the controller is configured to send data to the digital-to-analog converter after the test is completed, output a low-voltage analog quantity, and the output terminal of comparator A1 controls the sixth switch circuit to conduct to release the electric energy of the overshoot prevention capacitor C3 and the load under test C4.

[0014] A multi-stage boost speed control system, the system comprising: A power supply circuit; The bus output power modulation circuit includes a MOS transistor driver chip, MOS transistor Q7, MOS transistor Q8, capacitor C1, and capacitor C2; the gates of MOS transistor Q7 and MOS transistor Q8 are connected to the MOS transistor driver chip, the source of MOS transistor Q7 is connected to the drain of MOS transistor Q8, and a series-connected capacitor C1 and capacitor C2 are connected between the drain of MOS transistor Q7 and the source of MOS transistor Q8; A transformer, the primary coil of the transformer is connected between capacitor C1 and capacitor C2, and between the source of MOS transistor Q7 and the drain of MOS transistor Q8; A rectifier bridge includes diode D1, diode D2, diode D3, and diode D4. The positive electrode of diode D1 and the negative electrode of diode D3, and the positive electrode of diode D2 and the negative electrode of diode D4 are respectively connected to the secondary coil of the transformer; between the negative electrodes of diode D1 and diode D2, and between the positive electrodes of diode D3 and diode D4, they are connected through a series-connected load under test C4 and resistor R2; A first switch circuit is connected between the power supply circuit, the drain of MOS transistor Q7, and capacitor C1; A second switch circuit is connected between the primary coil of the transformer, capacitor C1, and capacitor C2; A third switch circuit is connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit; A fourth switch circuit is connected between the positive electrode of diode D2 and the negative electrode of diode D4; A voltage measurement circuit is used to measure the voltage of the load under test C4; A current measurement circuit is used to measure the current flowing through resistor R2; A controller outputs control signals to the power supply circuit, MOS transistor driver chip, first switch circuit, second switch circuit, and third switch circuit, and receives the signals from the voltage measurement circuit and current measurement circuit; The controller is configured to control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the power supply circuit to output a first voltage, control MOS transistor Q8 to turn on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t, and calculate the capacitance of the load under test C4; Control the voltage output by the power supply circuit according to the capacitance of the load under test C4, control the on and off of the first switch circuit, second switch circuit, third switch circuit, and fourth switch circuit; control the working state of the bus output power modulation circuit until the voltage across the load under test C4 reaches the set voltage.

[0015] The multi - stage boost speed control system as described above The controller is configured to: When the capacitance of the load C4 to be measured is within the first capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be off, the second switch circuit to be off, the third switch circuit to be on, and the fourth switch circuit to be off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; When the capacitance of the load C4 to be measured is within the second capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be on, the second switch circuit to be on, the third switch circuit to be off, and the fourth switch circuit to be on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the first set voltage; control the first switch circuit to be off, the second switch circuit to be off, the third switch circuit to be on, and the fourth switch circuit to be off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load C4 to be measured reaches the set voltage; When the capacitance of the load C4 to be measured is within the third capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be on, the second switch circuit to be on, the third switch circuit to be off, and the fourth switch circuit to be on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load C4 to be measured until the voltage across the load C4 to be measured reaches the set voltage; Wherein, the capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; wherein, the first set voltage is lower than the set voltage.

[0016] The multi - stage boost speed control system as described above, the system includes: A digital - to - analog converter, connected to the controller; Comparator A2, whose non - inverting input terminal is connected to the digital - to - analog converter, the inverting input terminal is connected to the voltage measurement circuit, and the output terminal is connected to the fifth switch circuit; The fifth switch circuit, connected to the cathodes of the diodes D1 and D2 and the load C4 to be measured; The anti - overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end is connected to the cathodes of the diodes D1 and D2 through the diode D6. The anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti - overshoot capacitor C3; The controller is configured to receive the maximum rising voltage set for each step, calculate the maximum value of the next boost based on the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of comparator A2 controls the fifth switching circuit to disconnect, stopping the charging of the load under test C4 until the controller calculates the maximum value of the next boost.

[0017] The multi-stage boost speed control system as described above, the system includes: A first voltage measurement circuit connected between the anti-overshoot capacitor C3 and the negative electrode of the diode D6; Comparator A1, whose non-inverting input terminal is connected to the digital-to-analog converter, the inverting input terminal is connected to the first voltage measurement circuit, and the output terminal is connected to the sixth switching circuit; The sixth switching circuit is connected to the resistor R1 and the positive electrodes of the diodes D3 and D4. The resistor R1 is connected between the diode D6 and the anti-overshoot capacitor C3; When the voltage at the non-inverting input terminal of comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to conduct, and the electrical energy of the anti-overshoot capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to disconnect.

[0018] Compared with the prior art, the advantages and positive effects of the present invention are: The cell test system of the present invention includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switching circuit, a current measurement circuit, a voltage measurement circuit, and a controller. The controller first calculates the capacitance of the load under test, and controls the voltage output by the power supply circuit, the on-off state of the switching circuit, and the working state of the bus output power modulation circuit according to the capacitance size until the voltage across the load under test reaches the set voltage. After the voltage across the load under test reaches the set voltage, the MOS transistors Q7 and Q8 are controlled to disconnect, and the load under test is in a self-discharging state. When the voltage measurement circuit measures that the voltage of the load under test is higher than the second set voltage, the load under test is qualified; otherwise, it is unqualified. The cell test system of the present invention can effectively identify the load size, select an appropriate topology and boost speed according to the load size, so that the boost speed conforms to the load, avoiding the technical problems of overshoot for small loads and low test efficiency for large loads.

[0019] The multi - stage boost speed - control system of the present invention includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a switching circuit, a current measurement circuit, a voltage measurement circuit, and a controller. The controller first calculates the capacitance of the load to be measured, and controls the voltage output by the power supply circuit, the on - off state of the switching circuit, and the working state of the bus output power modulation circuit according to the capacitance size until the voltage across the load to be measured reaches the set voltage. The multi - stage boost speed - control system of the present invention can effectively identify the load size, select an appropriate topology and boost speed according to the load size, so as to make the boost speed match the load, and avoid the technical problems of over - shooting for small loads and slow boost speed for large loads.

[0020] After reading the specific embodiments of the present invention in conjunction with the accompanying drawings, other features and advantages of the present invention will become clearer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a circuit architecture principle block diagram of the cell test system in the specific embodiment of the present invention; Figure 2 It is a schematic diagram of the flyback bus structure in the specific embodiment of the present invention; Figure 3 It is a schematic diagram of the half - bridge bus structure in the specific embodiment of the present invention: Figure 4 It is a waveform diagram of the gate voltages of N - type MOS transistor Q7 and N - type MOS transistor Q8 when the capacitance of the load to be measured in the specific embodiment of the present invention is in the first capacitance range; Figure 5 It is a waveform diagram of the gate voltages of N - type MOS transistor Q7 and N - type MOS transistor Q8 when the capacitance of the load to be measured in the specific embodiment of the present invention is in the second capacitance range; Figure 6 It is a waveform diagram of the gate voltages of N - type MOS transistor Q7 and N - type MOS transistor Q8 when the capacitance of the load to be measured in the specific embodiment of the present invention is in the third capacitance range; Figure 7 It is a test comparison diagram of three load types in the specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0024] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore, should not be construed as a limitation of the present invention.

[0025] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations. In the description of the embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0026] The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0027] In the description of the present invention, unless otherwise stated, the meaning of "a plurality" is two or more.

[0028] As Figure 1 shown, the battery cell test system includes a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, first to fourth switch circuits, a voltage measurement circuit, a current measurement circuit, and a controller. The following will specifically describe each part: Power supply circuit. In some embodiments, the power supply circuit is a BUCK - BOOST power supply circuit, and the output voltage range is from 3V to 48V.

[0029] Bus output power modulation circuit, including a MOS transistor driver chip, MOS transistor Q7, MOS transistor Q8, capacitor C1, and capacitor C2.

[0030] In some embodiments, the MOS transistor driving chip is an EG1160 MOS driving chip. The EG1160 MOS driving chip can be directly controlled by an MCU to achieve single MOS transistor control and dual MOS transistor control. The on-time period and duty cycle of the MOS transistor can be adjusted by the MCU control chip through a program, providing flexible control.

[0031] MOS transistors Q7 and Q8 are N-type MOS transistors. The gates of MOS transistors Q7 and Q8 are connected to the MOS transistor driving chip. The source of MOS transistor Q7 is connected to the drain of MOS transistor Q8. A series of capacitors C1 and C2 are connected between the drain of MOS transistor Q7 and the source of MOS transistor Q8. Capacitor C1 is connected to the drain of MOS transistor Q7, and capacitor C2 is connected to the source of MOS transistor Q8.

[0032] N-type MOS transistor Q7 and N-type MOS transistor Q8 operate at a frequency of 4KHZ, and the range of their duty cycle is adjustable from 1% to 40%.

[0033] The first switching circuit is connected between the power supply circuit, the drain of MOS transistor Q7, and capacitor C1.

[0034] In some embodiments, the first switching circuit includes N-type MOS transistor Q1, N-type MOS transistor Q2, and MOS transistor driving circuit 1.

[0035] The gates of MOS transistors Q1 and Q2 are connected to MOS transistor driving circuit 1. The drain of MOS transistor Q1 is connected to the power supply circuit. The source of MOS transistor Q1 is connected to the source of MOS transistor Q2. The drain of MOS transistor Q2 is connected between MOS transistor Q7 and capacitor C1.

[0036] MOS transistor driving circuit 1 is connected to the controller.

[0037] The primary coil of transformer T1 is connected between capacitor C1 and capacitor C2, and between the source of MOS transistor Q7 and the drain of MOS transistor Q8.

[0038] The second switching circuit is connected to the primary coil of transformer T1, between capacitor C1 and capacitor C2.

[0039] The second switching circuit includes N-type MOS transistor Q5, N-type MOS transistor Q6, and MOS transistor driving circuit.

[0040] The gates of MOS transistors Q5 and Q6 are connected to the MOS transistor driving circuit. The drain of MOS transistor Q5 is connected between capacitor C1 and capacitor C2. The source of MOS transistor Q5 is connected to the source of MOS transistor Q6. The drain of MOS transistor Q6 is connected to the primary coil of transformer T1.

[0041] The third switching circuit is connected between the power supply circuit, the primary coil of the transformer, and the second switching circuit.

[0042] The third switching circuit includes an N-type MOS transistor Q3, an N-type MOS transistor Q4, and a MOS transistor driving circuit.

[0043] The gates of MOS transistors Q3 and Q4 are connected to the MOS transistor driving circuit. The drain of MOS transistor Q3 is connected to the power supply circuit. The source of MOS transistor Q3 is connected to the source of MOS transistor Q4. The drain of MOS transistor Q4 is connected to the primary coil of transformer T1.

[0044] In some embodiments, the second switching circuit and the third switching circuit share the MOS transistor driving circuit 2, and the MOS transistor driving circuit 2 is connected to the controller.

[0045] The gates of MOS transistors Q5, Q6, Q3, and Q4 are connected to the MOS transistor driving circuit 2.

[0046] The rectifier bridge includes diodes D1, D2, D3, and D4. The positive electrode of diode D1 and the negative electrode of diode D3, and the positive electrode of diode D2 and the negative electrode of diode D4 are respectively connected to the secondary coil of the transformer. Between the negative electrodes of diodes D1 and D2, and between the positive electrodes of diodes D3 and D4, they are connected through the series-connected load under test C4 and resistor R2. The load under test C4 is connected to the negative electrodes of diodes D1 and D2, and resistor R2 is connected to the positive electrodes of diodes D3 and D4.

[0047] The fourth switching circuit is connected between the positive electrode of diode D2 and the negative electrode of diode D4.

[0048] The fourth switching circuit includes an N-type MOS transistor Q11 and a MOS transistor driving circuit 3. The gate of MOS transistor Q11 is connected to the MOS transistor driving circuit 3. The drain of MOS transistor Q11 is connected to the negative electrode of diode D4. The source of MOS transistor Q11 is connected to the positive electrode of diode D2.

[0049] The MOS transistor driving circuit 3 is connected to the controller.

[0050] The voltage measurement circuit 2 is used to measure the voltage of the load under test C4.

[0051] The current measurement circuit is used to measure the current flowing through resistor R2.

[0052] The voltage measurement circuit 2 and the current measurement circuit are connected to the controller through the ADC chip.

[0053] The controller outputs control signals to the power supply circuit, the MOS transistor driver chip, the first switch circuit, the second switch circuit, and the third switch circuit, and receives signals from the voltage measurement circuit and the current measurement circuit; The controller is configured to control the first switch circuit to be off, the second switch circuit to be off, the third switch circuit to be on, and the fourth switch circuit to be off; control the power supply circuit to output a first voltage, control MOS transistor Q8 to turn on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t, and calculate the capacitance of the load under test C4.

[0054] The controller is configured to calculate C according to the formula where C is the capacitance of the load under test C4, and t represents time.

[0055] Control the voltage output by the power supply circuit according to the capacitance of the load under test C4, control the on and off of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; control the working state of the bus output power modulation circuit until the voltage across the load under test C4 reaches the set voltage.

[0056] In order to adapt to different sizes of loads to quickly reach the set voltage without overshoot, the working states, switching frequencies, and duty cycles of MOS transistors Q7 and Q8 are different under different loads.

[0057] The controller is configured to, after the voltage across the load under test C4 reaches the set voltage, control MOS transistors Q7 and Q8 to be off, and the load under test C4 is in a self-discharge state. When the voltage measurement circuit measures that the voltage of the load under test C4 is higher than the second set voltage, the load under test C4 is qualified; otherwise, it is unqualified.

[0058] Wherein, the second set voltage is lower than the set voltage. In some embodiments, the second set voltage is 85%-95% of the set voltage.

[0059] The controller is configured to: When the capacitance of the load under test C4 is in the first capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be off, the second switch circuit to be off, the third switch circuit to be on, and the fourth switch circuit to be off. MOS transistor Q7 is always off. Just adjusting the duty cycle of MOS transistor Q8 can quickly reach the set voltage. Control MOS transistor Q8 to turn on and off according to the first duty cycle until the voltage across the load under test C4 reaches the set voltage. Wherein, the gate voltage waveform diagrams of MOS transistors Q7 and Q8 are as Figure 4 shown.

[0060] When the capacitance of the load under test C4 is in the second capacitance range, in order to quickly reach the set voltage, it is necessary to simultaneously adjust the switching frequencies of MOS transistors Q7 and Q8: control the power supply circuit to output a first voltage, control the first switching circuit to conduct, the second switching circuit to conduct, the third switching circuit to disconnect, and the fourth switching circuit to conduct; control MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the first set voltage; control the first switching circuit to disconnect, the second switching circuit to disconnect, the third switching circuit to conduct, and the fourth switching circuit to disconnect; turn off MOS transistor Q7, control MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load under test C4 reaches the set voltage; adjust the duty cycle of MOS transistor Q8 to reduce the output power to achieve a fast and overshoot-free reach of the set voltage. Among them, the gate voltage waveforms of MOS transistors Q7 and Q8 are as shown in Figure 5 shown.

[0061] When the capacitance of the load under test C4 is in the third capacitance range, the load is relatively large, and it is necessary to simultaneously adjust the switching frequencies of MOS transistors Q7 and Q8: control the power supply circuit to output a first voltage, control the first switching circuit to conduct, the second switching circuit to conduct, the third switching circuit to disconnect, and the fourth switching circuit to conduct; control MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the set voltage; since the load is relatively large and the voltage rise rate is slow, only by adjusting the switching frequencies of MOS transistors Q7 and Q8 can the set voltage be reached without overshoot.

[0062] Among them, the gate voltage waveforms of MOS transistors Q7 and Q8 are as shown in Figure 6 shown.

[0063] Among them, the capacitance value in the first capacitance range is lower than that in the second capacitance range, and the capacitance value in the second capacitance range is lower than that in the third capacitance range.

[0064] The first set voltage is lower than the set voltage. In some embodiments, the first set voltage is 70%-90% of the set voltage.

[0065] It can effectively identify the size of the load under test and select an appropriate topology and boost speed according to the size of the load cell.

[0066] The system further includes: a digital-to-analog converter, a comparator A2, and a fifth switching circuit.

[0067] The digital-to-analog converter is connected to the controller, and the digital-to-analog converter is a DAC chip.

[0068] The non-inverting input terminal of comparator A2 is connected to the digital-to-analog converter, the inverting input terminal is connected to the voltage measurement circuit, and the output terminal is connected to the fifth switching circuit.

[0069] The fifth switching circuit is connected to the cathodes of diode D1 and diode D2, and the load C4 to be measured.

[0070] The fifth switching circuit includes N-type MOS transistor Q9 and MOS transistor drive circuit 4. The gate of MOS transistor Q9 is connected to MOS transistor drive circuit 4, the source of MOS transistor Q9 is connected to the load C4 to be measured, and the drain of MOS transistor Q9 is connected to the negative electrodes of diode D1 and diode D2.

[0071] MOS transistor drive circuit 4 is connected to the output terminal of comparator A2.

[0072] The controller is configured to receive the maximum rising voltage set by the user for each step, calculate the maximum value of the next voltage boost according to the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of comparator A2 controls the fifth switching circuit to disconnect, stopping the charging of the load C4 to be measured until the controller calculates the maximum value of the next voltage boost.

[0073] The system further includes an anti-overshoot capacitor C3. One end of it is connected to the positive electrodes of diode D3 and diode D4, and the other end is connected to the negative electrodes of diode D1 and diode D2 through diode D6. The positive electrode of diode D6 is connected to the negative electrodes of diode D1 and diode D2, and the negative electrode of diode D6 is connected to anti-overshoot capacitor C3.

[0074] The system further includes: a first voltage measurement circuit, comparator A1, and a sixth switching circuit.

[0075] The first voltage measurement circuit (voltage measurement circuit 1 in the figure) is connected between the anti-overshoot capacitor C3 and the negative electrode of diode D6; Comparator A1, whose non-inverting input terminal is connected to the digital-to-analog converter, the inverting input terminal is connected to the first voltage measurement circuit, and the output terminal is connected to the sixth switching circuit; The sixth switching circuit is connected to resistor R1 and the positive electrodes of diode D3 and diode D4. Resistor R1 is connected between diode D6 and anti-overshoot capacitor C3.

[0076] The first switching circuit is P-type MOS transistor Q10. The gate of MOS transistor Q10 is connected to the output terminal of comparator A1, the source of MOS transistor Q10 is connected to the positive electrodes of diode D3 and diode D4, and the drain of MOS transistor Q10 is connected to resistor R1.

[0077] When the voltage at the non-inverting input terminal of comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to conduct, and the electrical energy of the overshoot prevention capacitor C3 is released through resistor R1. When the voltage at the non-inverting input terminal of comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to disconnect.

[0078] Through the comparator, DAC, and MOS transistor drive circuit, the maximum rising voltage of the load to be measured within a period can be effectively controlled, and thus the overshoot voltage during transient changes in the output can be effectively reduced.

[0079] The controller is configured to send data to the digital-to-analog converter after the test is completed and output a low-voltage analog quantity. The output terminal of comparator A1 controls the sixth switching circuit to conduct, and releases the electrical energy of the overshoot prevention capacitor C3 and the load to be measured C4.

[0080] The working process is as follows: The MCU control chip sends instructions through the MOS transistor drive circuit 1 to control the N-type MOS transistors Q1 and Q2 to disconnect. The MCU control chip sends instructions through the MOS transistor drive circuit 2 to control the N-type MOS transistors Q3 and Q4 to conduct. The MCU control chip sends instructions through the MOS transistor drive circuit 2 to control the N-type MOS transistors Q5 and Q6 to disconnect. The MCU control chip sends instructions through the MOS transistor drive circuit 3 to control the N-type MOS transistor Q11 to disconnect. The electrical structure at this time is as Figure 2 Schematic diagram of a new flyback bus structure for a high-voltage output speed control system.

[0081] The MCU control chip sends instructions to control the BUCK-BOOST power supply circuit to output a voltage of 24V. Then, the MCU control chip sends instructions to control the EG1160 MOS transistor driver to drive the N-type MOS transistor Q8 to conduct for 5 us and then turn off for 245 us. According to the structural characteristics of the flyback switch, the voltage across the load to be measured C4 will increase. At the same time, there is current flowing through the current measuring resistor R2.

[0082] The voltage measurement circuit 2 transfers the real-time voltage V of the load to be measured C4 to the ADC chip. The current measurement circuit measures the current I across the current measuring resistor R2 and transfers it to the ADC chip in real time. The ADC chip sends the current I and the voltage V to the MCU control chip. The MCU control chip calculates the load capacitance value according to the following formula:

[0083] where C is the capacitance of the load to be measured C4, and t represents time.

[0084] The MCU control chip calculates the capacitance value of the load C4 to be measured and adjusts the structure and combination mode of the bus voltage according to the peak voltage set by the user.

[0085] 1. The capacitance value of the load C4 to be measured is between 0.01 uf and 0.5 uf.

[0086] The MCU control chip sends instructions to control the output voltage of the BUCK - BOOST power circuit to be 24V. The MCU control chip sends instructions through the MOS tube drive circuit 1 to control the N - type MOS tubes Q1 and Q2 to disconnect. The MCU control chip sends instructions through the MOS tube drive circuit 2 to control the N - type MOS tubes Q3 and Q4 to conduct. The MCU control chip sends instructions through the MOS tube drive circuit 2 to control the N - type MOS tubes Q5 and Q6 to disconnect. The MCU control chip sends instructions through the MOS tube drive circuit 3 to control the N - type MOS tube Q11 to disconnect. At this time, the electrical structure is in the flyback bus structure, and its equivalent electrical structure diagram is as Figure 2 shown. The MCU control chip adapts to different loads by sending instructions to control the duty cycle of the PWM signal output by the EG1160MOS drive chip to drive the N - type MOS tube Q8. At this time, it adopts Figure 4 shown.

[0087] 2. The capacitance value of the load C4 to be measured is between 0.5 uf and 20 uf.

[0088] The MCU control chip sends instructions through the MOS tube drive circuit 1 to control the N - type MOS tubes Q1 and Q2 to conduct. The MCU control chip sends instructions through the MOS tube drive circuit 2 to control the N - type MOS tubes Q3 and Q4 to disconnect. The MCU control chip sends instructions through the MOS tube drive circuit 2 to control the N - type MOS tubes Q5 and Q6 to conduct. The MCU control chip sends instructions through the MOS tube drive circuit 3 to control the N - type MOS tube Q11 to conduct. At this time, the electrical structure is in the half - bridge bus structure, and its equivalent electrical structure diagram is as Figure 3 shown. The MCU control chip controls the EG1160MOS drive chip to output and drive the N - type MOS tubes Q7 and Q8 to conduct alternately. The 24V DC voltage is converted into AC, and after being doubled by the transformer, it passes through the H - bridge structure composed of the rectifier diodes D1, D2, D3, and D4 to output DC high voltage. The conduction time of the N - type MOS tubes Q7 and Q8 and the completely closed time of the N - type MOS tubes Q7 and Q8 are in a fixed ratio, as Figure 6As shown in the figure. The MCU control chip sends instructions to control the output voltage of the BUCK-BOOST power circuit to vary between 24V and 48V to adapt to different loads. When the output voltage reaches 80% of the set voltage, at this time, the MCU control chip controls the MOS transistor drive circuit 1, MOS transistor drive circuit 2, and MOS transistor drive circuit 3 by sending instructions to control each N-type MOS to adjust the bus structure to Figure 2 state. The voltage waveforms of the gates of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 are as Figure 5 shown, which can effectively prevent overshoot.

[0089] 3. The capacitance value of the load capacitor is greater than 20 μF.

[0090] The MCU control chip sends instructions to control the output voltage of the BUCK-BOOST power circuit to be 24V. The MCU control chip sends instructions to control the N-type MOS transistor Q1 and the N-type MOS transistor Q2 to conduct through the MOS transistor drive circuit 1. The MCU control chip sends instructions to control the N-type MOS transistor Q3 and the N-type MOS transistor Q4 to disconnect through the MOS transistor drive circuit 2. The MCU control chip sends instructions to control the N-type MOS transistor Q5 and the N-type MOS transistor Q6 to conduct through the MOS transistor drive circuit 2. The MCU control chip sends instructions to control the N-type MOS transistor Q11 to conduct through the MOS transistor drive circuit 3. At this time, the electrical structure is in a half-bridge bus structure, and its equivalent electrical structure diagram is as Figure 3 shown. The MCU control chip controls the EG1160 MOS drive chip to output and drive the N-type MOS transistor Q7 and the N-type MOS transistor Q8 by sending instructions, in an alternating conduction manner, to convert the 24V DC voltage into AC. After being doubled in voltage by the transformer, it passes through the H-bridge structure composed of the rectifier diodes D1, rectifier diode D2, rectifier diode D3, and rectifier diode D4 to output a DC high voltage. By adjusting the ratio of the alternating conduction time of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 to the time when the N-type MOS transistor Q7 and the N-type MOS transistor Q8 are completely turned off, to adapt to different loads. The voltage waveforms of the N-type MOS transistor Q7 and the N-type MOS transistor Q8 at the gates are as Figure 6 shown.

[0091] The user can set the maximum rising voltage for each step. The MCU control chip can monitor the output voltage value in real time through the voltage measurement circuit 2. The MCU-controlled chip calculates the maximum value for the next voltage boost based on the current voltage value and the maximum rising voltage for each step. The MCU sends the calculated value to the DAC chip, and the DAC chip converts it into an analog quantity and transmits it to the non-inverting input terminal of the comparator A2. When the voltage measurement circuit 2 transmits the voltage value at the output terminal to the inverting input terminal of the comparator A2, and when the voltage value at the non-inverting input terminal of the comparator A2 is lower than the voltage value at its inverting input terminal, the comparator A2 outputs a signal to the MOS tube driving circuit 3 to turn off the N-type MOS tube Q9, thus stopping charging C4. Until the next time the MCU control chip sends a new upper limit value, the N-type MOS tube Q9 is turned on again.

[0092] After the N-type MOS tube Q9 is turned off, all the electrical energy output by the transformer will go into the overshoot prevention capacitor C3. If the voltage across the overshoot prevention capacitor C3 is higher than the voltage across C4, it will lose the function of preventing overshoot. To prevent the voltage across the overshoot prevention capacitor C3 from rising, it needs to be discharged. The MCU control chip can monitor the voltage value across the overshoot prevention capacitor C3 in real time through the voltage measurement circuit 1. The MCU-controlled chip calculates the maximum value for the next voltage boost based on the current voltage value and the maximum rising voltage for each step. The MCU sends the calculated value to the DAC chip, and the DAC chip converts it into an analog quantity and transmits it to the non-inverting input terminal of the comparator A1. When the voltage measurement circuit 1 transmits the voltage value at the output terminal to the inverting input terminal of the comparator A1, and when the voltage value at the non-inverting input terminal of the comparator A1 is lower than the voltage value at its inverting input terminal, the comparator A1 controls the N-type MOS tube Q10 to turn on. The electrical energy inside the overshoot prevention capacitor C3 is released through the resistor R1 until the voltage value at the non-inverting input terminal of the comparator A1 is higher than the voltage value at its inverting input terminal, at which point the comparator A1 controls the MOS tube Q10 to disconnect.

[0093] When the voltage across C4 reaches the set voltage, the MCU control chip sends a command to the EG1160 MOS driver chip to control the N-type MOS tubes Q7 and Q8 to disconnect, stopping the output. C4 is in the self-discharge stage. The voltage measurement circuit 2 measures the voltage drop value during the self-discharge stage of C4. If the drop value is lower than 10% of the set voltage, the load under test meets the requirements; otherwise, it does not. After the test is completed, the MCU control chip sends data to the DAC chip, and the DAC chip outputs a low-voltage analog quantity to control the comparator A1 to drive the MOS tube Q10 to turn on, releasing all the electrical energy in C3 and C4.

[0094] Among them, the load under test is an electric core, for example, a lithium battery electric core.

[0095] Such as Figure 7As shown, it is a test waveform diagram of three different loads to be measured. Among them, the first load < the second load < the third load. It can be seen from the figure that the time differences for the three high loads to reach the set voltage of 200V are very small. The first load is a light load with a fast rising voltage but no overshoot. The third load is heavy, but the time it takes to reach the set voltage has a very small difference from that of the first load. None of the three loads exceed the set voltage during the voltage rising process.

[0096] This embodiment also proposes a multi-stage boost speed control system, including a power supply circuit, a bus output power modulation circuit, a transformer, a rectifier bridge, a first to fourth switch circuit, a voltage measurement circuit, a current measurement circuit, and a controller. Each part will be specifically described below: Power supply circuit. In some embodiments, the power supply circuit is a BUCK-BOOST power supply circuit, and the output voltage range is from 3V to 48V.

[0097] Bus output power modulation circuit, including a MOS tube driver chip, MOS tube Q7, MOS tube Q8, capacitor C1, and capacitor C2.

[0098] In some embodiments, the MOS tube driver chip is an EG1160 MOS driver chip. The EG1160 MOS driver chip can be directly controlled by an MCU to achieve single MOS tube control and dual MOS tube control. The on-time period and duty cycle of the MOS tube can be adjusted by the MCU control chip through a program, with flexible control.

[0099] MOS tube Q7 and MOS tube Q8 are N-type MOS tubes. The gates of MOS tube Q7 and MOS tube Q8 are connected to the MOS tube driver chip. The source of MOS tube Q7 is connected to the drain of MOS tube Q8. A series of capacitor C1 and capacitor C2 are connected between the drain of MOS tube Q7 and the source of MOS tube Q8. Capacitor C1 is connected to the drain of MOS tube Q7, and capacitor C2 is connected to the source of MOS tube Q8.

[0100] N-type MOS tube Q7 and N-type MOS tube Q8 work with a period of 4KHZ, and the range of their duty cycle is adjustable from 1% to 40%.

[0101] The first switch circuit is connected between the power supply circuit, the drain of MOS tube Q7, and capacitor C1.

[0102] In some embodiments, the first switch circuit includes N-type MOS tube Q1, N-type MOS tube Q2, and MOS tube drive circuit 1.

[0103] The gates of MOS transistor Q1 and MOS transistor Q2 are connected to the MOS transistor driving circuit 1. The drain of MOS transistor Q1 is connected to the power supply circuit. The source of MOS transistor Q1 is connected to the source of MOS transistor Q2. The drain of MOS transistor Q2 is connected between MOS transistor Q7 and capacitor C1.

[0104] The MOS transistor driving circuit 1 is connected to the controller.

[0105] The primary coil of transformer T1 is connected between capacitor C1 and capacitor C2, and between the source of MOS transistor Q7 and the drain of MOS transistor Q8.

[0106] The second switching circuit is connected between the primary coil of transformer T1, capacitor C1 and capacitor C2.

[0107] The second switching circuit includes N-type MOS transistor Q5, N-type MOS transistor Q6 and a MOS transistor driving circuit.

[0108] The gates of MOS transistor Q5 and MOS transistor Q6 are connected to the MOS transistor driving circuit. The drain of MOS transistor Q5 is connected between capacitor C1 and capacitor C2. The source of MOS transistor Q5 is connected to the source of MOS transistor Q6. The drain of MOS transistor Q6 is connected to the primary coil of transformer T1.

[0109] The third switching circuit is connected between the power supply circuit, the primary coil of the transformer and the second switching circuit.

[0110] The third switching circuit includes N-type MOS transistor Q3, N-type MOS transistor Q4 and a MOS transistor driving circuit.

[0111] The gates of MOS transistor Q3 and MOS transistor Q4 are connected to the MOS transistor driving circuit. The drain of MOS transistor Q3 is connected to the power supply circuit. The source of MOS transistor Q3 is connected to the source of MOS transistor Q4. The drain of MOS transistor Q4 is connected to the primary coil of transformer T1.

[0112] In some embodiments, the second switching circuit and the third switching circuit share the MOS transistor driving circuit 2, and the MOS transistor driving circuit 2 is connected to the controller.

[0113] The gates of MOS transistor Q5, MOS transistor Q6, MOS transistor Q3 and MOS transistor Q4 are connected to the MOS transistor driving circuit 2.

[0114] The rectifier bridge includes diode D1, diode D2, diode D3 and diode D4. The positive electrode of diode D1 and the negative electrode of diode D3, and the positive electrode of diode D2 and the negative electrode of diode D4 are respectively connected to the secondary coil of the transformer. Between the negative electrodes of diode D1 and diode D2, and between the positive electrodes of diode D3 and diode D4, they are connected through the series-connected load under test C4 and resistor R2. The load under test C4 is connected to the negative electrodes of diode D1 and diode D2, and resistor R2 is connected to the positive electrodes of diode D3 and diode D4.

[0115] The fourth switch circuit is connected between the positive electrode of diode D2 and the negative electrode of diode D4.

[0116] The fourth switch circuit includes N-type MOS transistor Q11 and MOS transistor drive circuit 3. The gate of MOS transistor Q11 is connected to MOS transistor drive circuit 3. The drain of MOS transistor Q11 is connected to the negative electrode of diode D4, and the source of MOS transistor Q11 is connected to the positive electrode of diode D2.

[0117] MOS transistor drive circuit 3 is connected to the controller.

[0118] Voltage measurement circuit 2 is used to measure the voltage of the load under test C4.

[0119] Current measurement circuit is used to measure the current flowing through resistor R2.

[0120] Voltage measurement circuit 2 and current measurement circuit are connected to the controller through the ADC chip.

[0121] The controller outputs control signals to the power supply circuit, MOS transistor drive chip, first switch circuit, second switch circuit, third switch circuit, and receives the signals from the voltage measurement circuit and current measurement circuit. The controller is configured to control the first switch circuit to be off, the second switch circuit to be off, the third switch circuit to be on, and the fourth switch circuit to be off; control the power supply circuit to output the first voltage, control MOS transistor Q8 to turn on and off according to the first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t, and calculate the capacitance of the load under test C4.

[0122] The controller is configured to calculate C according to the formula where C is the capacitance of the load under test C4, and t represents time.

[0123] Control the voltage output by the power supply circuit according to the capacitance of the load under test C4, control the on and off of the first switch circuit, second switch circuit, third switch circuit and fourth switch circuit; control the working state of the bus output power modulation circuit until the voltage across the load under test C4 reaches the set voltage.

[0124] To enable the load of different sizes to quickly reach the set voltage without overshoot, the operating states, switching frequencies, and duty cycles of MOS transistors Q7 and Q8 are different under different loads.

[0125] The controller is configured as follows: When the capacitance of the load under test C4 is in the first capacitance range, control the power supply circuit to output a first voltage, control the first switching circuit to be off, the second switching circuit to be off, the third switching circuit to be on, the fourth switching circuit to be off, and MOS transistor Q7 to always be off. Only by adjusting the duty cycle of MOS transistor Q8 can the set voltage be quickly reached. Control MOS transistor Q8 to turn on and off according to the first duty cycle until the voltage across the load under test C4 reaches the set voltage. Among them, the gate voltage waveform diagrams of MOS transistors Q7 and Q8 are as Figure 4 shown.

[0126] When the capacitance of the load under test C4 is in the second capacitance range, to quickly reach the set voltage, it is necessary to simultaneously adjust the switching frequencies of MOS transistors Q7 and Q8: control the power supply circuit to output a first voltage, control the first switching circuit to be on, the second switching circuit to be on, the third switching circuit to be off, the fourth switching circuit to be on; control MOS transistors Q7 and Q8 to turn on and off according to the second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the first set voltage; control the first switching circuit to be off, the second switching circuit to be off, the third switching circuit to be on, the fourth switching circuit to be off; turn off MOS transistor Q7, control MOS transistor Q8 to turn on and off according to the first duty cycle until the voltage across the load under test C4 reaches the set voltage; adjust the duty cycle of MOS transistor Q8 to reduce the output power to achieve a quick and overshoot-free reach of the set voltage. Among them, the gate voltage waveform diagrams of MOS transistors Q7 and Q8 are as Figure 5 shown.

[0127] When the capacitance of the load under test C4 is in the third capacitance range, the load is relatively large, and it is necessary to simultaneously adjust the switching frequencies of MOS transistors Q7 and Q8: control the power supply circuit to output a first voltage, control the first switching circuit to be on, the second switching circuit to be on, the third switching circuit to be off, the fourth switching circuit to be on; control MOS transistors Q7 and Q8 to turn on and off according to the second duty cycle, and adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the set voltage; since the voltage rise speed is slow due to the relatively large load, only by adjusting the switching frequencies of MOS transistors Q7 and Q8 can the set voltage be reached without overshoot.

[0128] Among them, the gate voltage waveform diagrams of MOS transistors Q7 and Q8 are as Figure 6 shown.

[0129] Among them, the capacitance value in the first capacitance value range is lower than that in the second capacitance value range, and the capacitance value in the second capacitance value range is lower than that in the third capacitance value range.

[0130] The first set voltage is 70%-90% of the set voltage.

[0131] It can effectively identify the size of the load to be measured, and select an appropriate topology and boost speed according to the size of the load cell.

[0132] The system further includes: a digital-to-analog converter, a comparator A2, and a fifth switching circuit.

[0133] The digital-to-analog converter is connected to the controller, and the digital-to-analog converter is a DAC chip.

[0134] The non-inverting input terminal of the comparator A2 is connected to the digital-to-analog converter, the inverting input terminal is connected to the voltage measurement circuit, and the output terminal is connected to the fifth switching circuit.

[0135] The fifth switching circuit is connected to the cathodes of the diodes D1 and D2 and the load to be measured C4.

[0136] The fifth switching circuit includes an N-type MOS transistor Q9 and a MOS transistor driving circuit 4. The gate of the MOS transistor Q9 is connected to the MOS transistor driving circuit 4, the source of the MOS transistor Q9 is connected to the load to be measured C4, and the drain of the MOS transistor Q9 is connected to the negative electrodes of the diodes D1 and D2.

[0137] The MOS transistor driving circuit 4 is connected to the output terminal of the comparator A2.

[0138] The controller is configured to receive the maximum rising voltage of each step set by the user, calculate the maximum value of the next boost according to the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switching circuit to disconnect, stopping charging the load to be measured C4 until the controller calculates the maximum value of the next boost.

[0139] The system further includes an overshoot prevention capacitor C3. One end of it is connected to the positive electrodes of the diodes D3 and D4, and the other end is connected to the negative electrodes of the diodes D1 and D2 through a diode D6. The positive electrode of the diode D6 is connected to the negative electrodes of the diodes D1 and D2, and the negative electrode of the diode D6 is connected to the overshoot prevention capacitor C3.

[0140] The system further includes: a first voltage measurement circuit, a comparator A1, and a sixth switching circuit.

[0141] The first voltage measurement circuit (the voltage measurement circuit 1 in the figure) is connected between the overshoot prevention capacitor C3 and the negative electrode of the diode D6; Comparator A1, whose non-inverting input terminal is connected to a digital-to-analog converter, inverting input terminal is connected to a first voltage measurement circuit, and output terminal is connected to a sixth switching circuit; The sixth switching circuit is connected to resistor R1, and to the anodes of diode D3 and diode D4. Resistor R1 is connected between diode D6 and overshoot protection capacitor C3.

[0142] The first switching circuit is P-type MOS transistor Q10. The gate of MOS transistor Q10 is connected to the output terminal of comparator A1. The source of MOS transistor Q10 is connected to the anodes of diode D3 and diode D4. The drain of MOS transistor Q10 is connected to resistor R1.

[0143] When the voltage at the non-inverting input terminal of comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to conduct, and the electrical energy of overshoot protection capacitor C3 is released through resistor R1. When the voltage at the non-inverting input terminal of comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to disconnect.

[0144] Through the comparator, DAC, and MOS transistor drive circuit, the maximum rising voltage of the load to be measured within a period can be effectively controlled, and thus the overshoot voltage during transient changes in the output can be effectively reduced.

[0145] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, for those of ordinary skill in the art, it is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions required to be protected by the present invention.

Claims

1. A battery cell testing system, characterized in that, The cell testing system includes: A power supply circuit; A bus output power modulation circuit, including a MOS transistor driver chip, MOS transistor Q7, MOS transistor Q8, capacitor C1, and capacitor C2; the gates of MOS transistor Q7 and MOS transistor Q8 are connected to the MOS transistor driver chip, the source of MOS transistor Q7 is connected to the drain of MOS transistor Q8, and a series-connected capacitor C1 and capacitor C2 are connected between the drain of MOS transistor Q7 and the source of MOS transistor Q8; A transformer, the primary coil of the transformer is connected between capacitor C1 and capacitor C2, and between the source of MOS transistor Q7 and the drain of MOS transistor Q8; A rectifier bridge, including diode D1, diode D2, diode D3, and diode D4, the positive poles of diode D1 and diode D3, and the positive poles of diode D2 and diode D4 are respectively connected to the secondary coil of the transformer; a series-connected load under test C4 and resistor R2 are connected between the negative poles of diode D1 and diode D2, and between the positive poles of diode D3 and diode D4; A first switch circuit, connected between the power supply circuit, the drain of MOS transistor Q7, and capacitor C1; A second switch circuit, connected between the primary coil of the transformer, capacitor C1, and capacitor C2; A third switch circuit, connected between the power supply circuit, the primary coil of the transformer, and the second switch circuit; A fourth switch circuit, connected between the positive pole of diode D2 and the negative pole of diode D4; A voltage measurement circuit, used to measure the voltage of the load under test C4; A current measurement circuit, used to measure the current flowing through resistor R2; A controller, outputting control signals to the power supply circuit, MOS transistor driver chip, first switch circuit, second switch circuit, third switch circuit, and receiving signals from the voltage measurement circuit and current measurement circuit; Controlling the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; controlling the power supply circuit to output a first voltage, controlling MOS transistor Q8 to turn on and off according to a first duty cycle, receiving the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and timing t to calculate the capacitance of the load under test C4; Controlling the voltage output by the power supply circuit according to the capacitance of the load under test C4, controlling the on and off of the first switch circuit, second switch circuit, third switch circuit, and fourth switch circuit; controlling the working state of the bus output power modulation circuit until the voltage across the load under test C4 reaches a set voltage; After the voltage across the load under test C4 reaches the set voltage, controlling MOS transistor Q7 and MOS transistor Q8 to be turned off, the load under test C4 is in a self-discharge state, when the voltage measurement circuit measures that the voltage of the load under test C4 is higher than a second set voltage, it is determined that the load under test C4 is qualified, otherwise, it is unqualified; Wherein, the second set voltage is lower than the set voltage.

2. The cell testing system according to claim 1, wherein The controller is configured to: When the capacitance of the load under test C4 is within the first capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the MOS transistor Q8 to be turned on and off according to a first duty cycle until the voltage across the load under test C4 reaches a set voltage; When the capacitance of the load under test C4 is within the second capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS transistors Q7 and Q8 to be turned on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches a first set voltage; control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the MOS transistor Q8 to be turned on and off according to a first duty cycle until the voltage across the load under test C4 reaches a set voltage; When the capacitance of the load under test C4 is within the third capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS transistors Q7 and Q8 to be turned on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches a set voltage; Wherein, the capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; Wherein, the first set voltage is lower than the set voltage.

3. The battery cell testing system according to claim 1, wherein, The controller is configured to calculate C according to the formula where C is the capacitance of the load C4 to be measured, and t represents time.

4. The cell testing system according to any one of claims 1-3, characterized in that, The test system includes: A digital-to-analog converter, connected to the controller; Comparator A2, whose non-inverting input terminal is connected to the digital-to-analog converter, inverting input terminal is connected to the voltage measurement circuit, and output terminal is connected to the fifth switch circuit; The fifth switch circuit, connected to the cathodes of the diodes D1 and D2 and the load under test C4; An anti-overshoot capacitor C3, one end of which is connected to the anodes of the diodes D3 and D4, and the other end is connected to the cathodes of the diodes D1 and D2 through the diode D6, the anode of the diode D6 is connected to the cathodes of the diodes D1 and D2, and the cathode of the diode D6 is connected to the anti-overshoot capacitor C3; The controller is configured to receive the maximum rising voltage set for each step, calculate the maximum value of the next voltage boost according to the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to be turned off, stopping charging the load under test C4 until the controller calculates the maximum value of the next voltage boost.

5. The battery cell testing system according to claim 4, wherein, The system includes: A first voltage measurement circuit, connected between the anti-overshoot capacitor C3 and the cathode of the diode D6; Comparator A1, whose non-inverting input terminal is connected to the digital-to-analog converter, inverting input terminal is connected to the first voltage measurement circuit, and output terminal is connected to the sixth switching circuit; The sixth switching circuit is connected to resistor R1, and to the anodes of diode D3 and diode D4. Resistor R1 is connected between diode D6 and overshoot prevention capacitor C3; When the voltage at the non-inverting input terminal of comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to conduct, and the electrical energy of overshoot prevention capacitor C3 is released through resistor R1. When the voltage at the non-inverting input terminal of comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of comparator A1 controls the sixth switching circuit to disconnect.

6. The cell testing system according to claim 5, wherein The controller is configured to send data to the digital-to-analog converter after the test is completed, output a low-voltage analog quantity, and the output terminal of comparator A1 controls the sixth switching circuit to conduct, releasing the electrical energy of overshoot prevention capacitor C3 and the load under test C4.

7. A multi-stage boost speed control system, characterized in that, The system includes: A power supply circuit; A bus output power modulation circuit, including a MOS transistor driver chip, MOS transistors Q7, Q8, capacitor C1, and capacitor C2; the gates of MOS transistors Q7 and Q8 are connected to the MOS transistor driver chip, the source of MOS transistor Q7 is connected to the drain of MOS transistor Q8, and a series connection of capacitor C1 and capacitor C2 is connected between the drain of MOS transistor Q7 and the source of MOS transistor Q8; A transformer, whose primary coil is connected between capacitor C1 and capacitor C2, and between the source of MOS transistor Q7 and the drain of MOS transistor Q8; A rectifier bridge, including diodes D1, D2, D3, and D4. The anode of diode D1 and the cathode of diode D3, and the anode of diode D2 and the cathode of diode D4 are respectively connected to the secondary coil of the transformer; a series connection of the load under test C4 and resistor R2 is connected between the cathode of diode D1 and the cathode of diode D2, and between the anode of diode D3 and the anode of diode D4; A first switching circuit, connected to the power supply circuit, the drain of MOS transistor Q7, and capacitor C1; A second switching circuit, connected to the primary coil of the transformer, capacitor C1, and capacitor C2; A third switching circuit, connected to the power supply circuit, the primary coil of the transformer, and the second switching circuit; A fourth switching circuit, connected between the anode of diode D2 and the cathode of diode D4; A voltage measurement circuit, used to measure the voltage of the load under test C4; A current measurement circuit, used to measure the current flowing through resistor R2; A controller, outputting control signals to the power supply circuit, MOS transistor driver chip, first switching circuit, second switching circuit, third switching circuit, and receiving signals from the voltage measurement circuit and current measurement circuit; The controller is configured to control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the power supply circuit to output a first voltage, control the MOS transistor Q8 to turn on and off according to a first duty cycle, receive the current I detected by the current measurement circuit and the voltage V detected by the voltage measurement circuit, and time t, and calculate the capacitance of the load under test C4. Control the voltage output by the power supply circuit according to the capacitance of the load under test C4, control the on and off of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit; control the working state of the bus output power modulation circuit until the voltage across the load under test C4 reaches the set voltage.

8. The multi-stage boost speed control system according to claim 7, wherein The controller is configured to: When the capacitance of the load under test C4 is within the first capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load under test C4 reaches the set voltage. When the capacitance of the load under test C4 is within the second capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the first set voltage; control the first switch circuit to be turned off, the second switch circuit to be turned off, the third switch circuit to be turned on, and the fourth switch circuit to be turned off; control the MOS transistor Q8 to turn on and off according to a first duty cycle until the voltage across the load under test C4 reaches the set voltage. When the capacitance of the load under test C4 is within the third capacitance range, control the power supply circuit to output a first voltage, control the first switch circuit to be turned on, the second switch circuit to be turned on, the third switch circuit to be turned off, and the fourth switch circuit to be turned on; control the MOS transistors Q7 and Q8 to turn on and off according to a second duty cycle, adjust the output voltage of the power supply circuit according to the capacitance of the load under test C4 until the voltage across the load under test C4 reaches the set voltage. Wherein, the capacitance value of the first capacitance range is lower than that of the second capacitance range, and the capacitance value of the second capacitance range is lower than that of the third capacitance range; wherein, the first set voltage is lower than the set voltage.

9. The multi-stage boost speed control system according to any one of claims 7-8, characterized in that The system includes: A digital-to-analog converter, connected to the controller; Comparator A2, whose non-inverting input terminal is connected to the digital-to-analog converter, the inverting input terminal is connected to the voltage measurement circuit, and the output terminal is connected to the fifth switch circuit; The fifth switch circuit, connected to the cathodes of the diodes D1 and D2 and the load under test C4; The overshoot prevention capacitor C3 has one end connected to the positive electrodes of the diodes D3 and D4, and the other end connected to the negative electrodes of the diodes D1 and D2 through the diode D6. The positive electrode of the diode D6 is connected to the negative electrodes of the diodes D1 and D2, and the negative electrode of the diode D6 is connected to the overshoot prevention capacitor C3; The controller is configured to receive the maximum rising voltage set for each step, calculate the maximum value of the next voltage boost according to the current voltage detected by the voltage measurement circuit and the maximum rising voltage, and send it to the digital-to-analog converter; when the voltage at the non-inverting input terminal of the comparator A2 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A2 controls the fifth switch circuit to disconnect and stop charging the load under test C4 until the controller calculates the maximum value of the next voltage boost.

10. The multi-stage boost speed control system according to claim 9, characterized in that, The system includes: A first voltage measurement circuit connected between the overshoot prevention capacitor C3 and the negative electrode of the diode D6; A comparator A1, whose non-inverting input terminal is connected to the digital-to-analog converter, the inverting input terminal is connected to the first voltage measurement circuit, and the output terminal is connected to the sixth switch circuit; A sixth switch circuit connected to the resistor R1 and the positive electrodes of the diodes D3 and D4. The resistor R1 is connected between the diode D6 and the overshoot prevention capacitor C3; When the voltage at the non-inverting input terminal of the comparator A1 is lower than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to conduct, and the electric energy of the overshoot prevention capacitor C3 is released through the resistor R1. When the voltage at the non-inverting input terminal of the comparator A1 is higher than the voltage at the inverting input terminal, the output terminal of the comparator A1 controls the sixth switch circuit to disconnect.

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