Service upgrade system, electronic equipment, method, storage medium and product

Abstract

The present application discloses a service upgrade system, electronic device, method, storage medium and product, which relate to the field of computer technology. The service upgrade system includes a processor and a controller connected to the processor. The controller divides the monitored threads to obtain a first thread for performing upgraded services and a second thread for performing non-upgraded services. The controller also obtains the total time slice and reserved time slice preset by the processor, and determines the time slice allocated to the first thread based on the total time slice, the reserved time slice and the preset time slice dynamic allocation algorithm. The allocated time slice is used to characterize the length of time allocated to the first thread to use processor resources. The processor then generates the required clock signal within the time slice allocated to the first thread, and the clock signal is used to perform service upgrades. The present application improves the stability of the clock signal generated by the controller, thereby improving the success rate of service upgrades.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a service upgrade system, electronic equipment, method, storage medium, and product. Background Art

[0002] During the service upgrade process, the clock signal is the key to ensuring reliable transmission of upgrade data. The controller uses the generated clock signal to transmit the upgrade data corresponding to the upgraded service, and the generation of the clock signal depends on the allocation of processor resources.

[0003] In related technologies, fixed priority scheduling or static resource allocation is usually used to allocate processor resources. However, this allocation method cannot meet the clock signal stability requirements during service upgrades, which can easily lead to service upgrade failures. Summary of the Invention

[0004] The present application provides a service upgrade system, electronic device, method, storage medium and product to at least solve the problem that the resource allocation method of the processor in the related technology cannot meet the requirements for clock signal stability during the service upgrade process, which easily leads to the failure of the service upgrade.

[0005] This application provides a service upgrade system, including:

[0006] A processor and a controller connected to the processor;

[0007] The controller is configured to divide the monitored threads into a first thread for performing an upgrade service and a second thread for performing a non-upgrade service;

[0008] The controller is further configured to obtain a total time slice and a reserved time slice preset by the processor, and determine a time slice to be allocated to the first thread based on the total time slice, the reserved time slice, and a preset time slice dynamic allocation algorithm, where the allocated time slice is used to represent a duration allocated to the first thread for use of processor resources;

[0009] The controller is further configured to generate a required clock signal within the time slice allocated by the first thread, where the clock signal is used for performing service upgrade.

[0010] The present application provides an electronic device including a logic device and a service upgrade system, wherein the logic device is a target object for performing service upgrades.

[0011] This application provides a service upgrade method, including:

[0012] Dividing the monitored threads to obtain a first thread for performing an upgrade service and a second thread for performing a non-upgrade service;

[0013] Obtaining a total time slice and a reserved time slice preset by the processor, and determining a time slice to be allocated to the first thread based on the total time slice, the reserved time slice, and a preset time slice dynamic allocation algorithm, where the allocated time slice is used to represent a duration allocated to the first thread for using processor resources;

[0014] A required clock signal is generated within the time slice allocated by the first thread, and the clock signal is used for service upgrade.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned service upgrade methods are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned service upgrade methods when executed by a processor.

[0017] Through the present application, a service upgrade system is provided, including a processor and a controller connected to the processor. The controller divides the monitored threads to obtain a first thread for performing upgraded services and a second thread for performing non-upgraded services. The controller also obtains the total time slice and reserved time slice preset by the processor, and determines the time slice allocated to the first thread based on the total time slice, the reserved time slice and the preset time slice dynamic allocation algorithm. The allocated time slice is used to characterize the length of time allocated to the first thread to use processor resources. The processor then generates the required clock signal within the time slice allocated to the first thread, and the clock signal is used to perform service upgrades. In the service upgrade system of the present application, the controller in the service upgrade system can dynamically allocate time slices for the first thread used to perform upgraded services. The more sufficient the allocated time slices are, the more stable the clock signal generated by the controller is, thereby improving the success rate of service upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of an application scenario provided for this application;

[0020] Figure 2 A schematic diagram of the structure of a service upgrade system provided in an embodiment of the present application;

[0021] Figure 3 A thread classification diagram provided in an embodiment of the present application;

[0022] Figure 4 A flowchart of a method for determining a time slice allocated to a first thread provided in an embodiment of the present application;

[0023] Figure 5 Another thread classification diagram provided in an embodiment of the present application;

[0024] Figure 6 A flowchart of another method for determining a time slice allocated to a first thread provided in an embodiment of the present application;

[0025] Figure 7 A flowchart of a method for allocating a time slice to a second thread provided in an embodiment of the present application;

[0026] Figure 8 A flowchart of a service upgrade method provided in an embodiment of the present application;

[0027] Figure 9 A schematic diagram of the structure of a CPLD provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of the structure and function of a CPLD provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0031] The controller in an electronic device, acting as the core hub during service upgrades, generates a clock signal that is crucial for the accurate transmission of upgrade data. This clock signal establishes a precise timing benchmark for the entire upgrade data transmission process. Within each clock cycle, upgrade data is sampled and encoded in a predetermined sequence, and then transmitted through the communication interface to the target device corresponding to the upgrade service.

[0032] The stability of the clock signal generated by the controller directly depends on the rationality of processor resource allocation. For example, when processor resources are occupied by other tasks other than upgrading business, the controller's clock generation may be interrupted, resulting in an unstable clock signal.

[0033] In the related art, fixed priority scheduling is usually used to allocate processor resources. Fixed priority scheduling means that a fixed priority is assigned to each task in advance, and tasks with higher priorities are executed first. For example, assuming that there are multiple tasks in the controller, such as sensor monitoring tasks, network communication tasks, and firmware upgrade tasks, the priority of each task is pre-set. The sensor monitoring task may have the highest priority, while the firmware upgrade task may have a lower priority. When a high-priority task is running, a low-priority task will be preempted by the processor resources. At this time, the firmware upgrade task needs to generate a clock signal, which will cause the clock generation to be delayed because the processor resources are occupied, resulting in jitter, causing the generated clock signal to be unstable, thereby increasing the risk of firmware upgrade failure.

[0034] Alternatively, processor resources can be allocated using static resource allocation. Static resource allocation pre-allocates a fixed processor time slice for each task, allowing each task to take turns using the processor for a fixed time slice. For example, a firmware upgrade task might be allocated a certain time slice. However, if the upgrade process requires higher clock stability, such as the need to continuously generate a stable clock signal, and the allocated time slice is insufficient, resulting in discontinuous clock generation, this will affect the stability of the clock signal and increase the risk of firmware upgrade failure.

[0035] Therefore, in response to the aforementioned issues in related technologies, research has discovered that by using a controller to divide threads into a first thread for performing upgrade services and a second thread for performing non-upgrade services, and by allocating a dedicated time slice to the first thread based on the total time slice, reserved time slice, and a dynamic allocation algorithm, the processor can generate a stable clock signal within this time slice for service upgrades. Compared to fixed priority or static resource allocation methods, this can dynamically adapt to the clock signal stability requirements of service upgrades, reducing clock signal fluctuations caused by rigid resource allocation, thereby improving the processor resource guarantee capability of the first thread during service upgrades and reducing the risk of upgrade failures.

[0036] To facilitate understanding of this application, the following example provides an application scenario. Figure 1 , Figure 1A schematic diagram of an application scenario provided for this application includes a controller 01, a processor 02 and a logic device 03. The controller 01 uses the resources of the processor 02 to generate a clock signal and upgrades the upgrade file of the logic device 03 through the clock signal.

[0037] Specifically, the controller 01 divides the monitored threads to obtain a first thread for upgrading the logic device 03 and a second thread for performing other services, and determines the time slice allocated to the first thread based on the total time slice and reserved time slice preset by the processor 02, as well as the preset time slice dynamic allocation algorithm, generates the required clock signal within the time slice allocated by the first thread, and uses the clock signal to transmit the upgrade file of the logic device 03.

[0038] It is understandable that the above application scenarios are only used for illustration and do not limit the present application.

[0039] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] See Figure 2 , Figure 2 This is a structural diagram of a service upgrade system provided in an embodiment of the present application, which includes a controller 01 and a processor 02 connected to the controller 01.

[0041] In this embodiment, the controller 01 may be a baseboard management controller (BMC). The BMC divides the monitored threads into a first thread for performing an upgrade service and a second thread for performing a non-upgrade service.

[0042] In this application, threads can be classified according to the threads managed by BMC, as shown below: Figure 3 The thread classification shown, Figure 3 A thread classification diagram is provided for an embodiment of the present application. Taking the upgrade of the firmware in a complex programmable logic device (CPLD) as an example, the threads related to the CPLD upgrade can be divided into the first thread, and other threads unrelated to the CPLD upgrade can be divided into the second thread, such as the thread used for logging or the thread used for network communication.

[0043] The controller 01 is further configured to obtain a total time slice and a reserved time slice preset by the processor 02, and determine a time slice to be allocated to the first thread based on the total time slice, the reserved time slice, and a preset time slice dynamic allocation algorithm. The allocated time slice represents the duration of time allocated to the first thread to use the processor 02 resources.

[0044] In this embodiment, the processor 02 may be a central processing unit (CPU). The BMC obtains a total time slice and a reserved time slice preset by the CPU, and determines a time slice allocated to the first thread in combination with a preset time slice dynamic allocation algorithm. The unit of the time slice may be us.

[0045] The controller 01 is further configured to generate a required clock signal within the time slice allocated by the first thread, and the clock signal is used for performing service upgrade.

[0046] In this embodiment, the BMC generates a clock signal in the time slice allocated by the first thread. In this embodiment, the clock signal may be referred to as a test clock (TCK).

[0047] In the above embodiment of the present application, the service upgrade system includes a processor and a controller connected to the processor. The controller divides the monitored threads to obtain a first thread for performing the upgrade service and a second thread for performing the non-upgrade service. The controller also obtains the total time slice and the reserved time slice preset by the processor, and determines the time slice allocated to the first thread based on the total time slice, the reserved time slice and the preset time slice dynamic allocation algorithm. The allocated time slice is used to characterize the length of time allocated to the first thread to use the processor resources. The processor then generates the required clock signal within the time slice allocated to the first thread, and the clock signal is used to perform service upgrades. In the service upgrade system of this embodiment, the controller in the upgrade system can dynamically allocate time slices for the first thread used to perform the upgrade service. The more sufficient the allocated time slices are, the more stable the clock signal generated by the controller is, thereby improving the success rate of the service upgrade.

[0048] Furthermore, based on the above embodiment, the following embodiment illustrates a process in which the controller 01 determines the time slice allocated to the first thread based on the total time slice, the reserved time slice and the preset time slice dynamic allocation algorithm.

[0049] See Figure 4 , Figure 4 This is a flow chart of a method for determining a time slice allocated to a first thread provided in an embodiment of the present application. The controller 01 takes the BMC as an example. The BMC is configured to perform the following steps:

[0050] S401: The BMC determines a basic time slice allocated to a first thread according to a total time slice and a reserved time slice.

[0051] One possible implementation is:

[0052] The BMC obtains a first weight coefficient preset for the first thread, a second weight coefficient preset for the second thread, and a preset weighting coefficient.

[0053] When dividing threads in the above embodiment, the BMC further subdivides the subthreads in the second thread to obtain Figure 5 The second thread classification shown, Figure 5 Another thread classification diagram provided for an embodiment of the present application divides the second thread into a high-priority thread, i.e., a first sub-thread, a medium-priority thread, i.e., a second sub-thread, and a low-priority thread, i.e., a third sub-thread, according to the real-time requirements of other services being processed. The priority of the first sub-thread is greater than that of the second sub-thread, and the priority of the second sub-thread is greater than that of the third sub-thread.

[0054] Among them, high-priority threads can be threads used to process system status reporting tasks, status detection tasks or signal monitoring tasks, medium-priority threads can be threads used to process sensor monitoring tasks or alarm processing tasks, and low-priority threads can be threads used to process data backup or data synchronization tasks.

[0055] Optionally, the threads within the high-priority threads, medium-priority threads and low-priority threads can be further subdivided according to the CPU occupancy during actual operation, and divided into high-occupancy threads, medium-occupancy threads and low-occupancy threads respectively.

[0056] Illustratively, a high occupancy thread may be a thread with a CPU occupancy exceeding 50%, a medium occupancy thread may be a thread with a CPU occupancy between 10% and 50%, and a low occupancy thread may be a thread with a CPU occupancy less than 10%.

[0057] In this embodiment, the BMC obtains a first weight coefficient preset for the first thread, for example, the first weight coefficient may be 10. Furthermore, the BMC obtains a second weight coefficient preset for the second thread, which may include a third weight coefficient, a fourth weight coefficient, and a fifth weight coefficient. The third weight coefficient is a weight coefficient preset for a high-priority thread in the second thread, which may be 5; the fourth weight coefficient is a weight coefficient preset for a medium-priority thread in the second thread, which may be 3; and the fifth weight coefficient is a weight coefficient preset for a low-priority thread in the second thread, which may be 1.

[0058] It is understandable that the above examples are only for illustration, and the weight coefficients can be flexibly set according to actual needs, and this application does not limit them.

[0059] The BMC performs a sum calculation based on the first weight coefficient and the second weight coefficient to determine the total weight of the first thread, subtracts the total time slice from the reserved time slice to obtain a time slice difference, divides the time slice difference by the total weight of the first thread to obtain a division result, and multiplies the division result by the weight coefficient to obtain a multiplication result. The multiplication result is the basic time slice allocated to the first thread.

[0060] Specifically, the basic time slice is determined by the following formula (1).

[0061]

[0062] in, Represents the weight coefficient corresponding to the i-th time slice; Indicates the total number of time slices; represents the i-th time slice; represents the sum of the weights of the first threads mentioned above; Indicates the total time slice; Indicates the retention time slice; Represents the time slice difference mentioned above; Represents the above division result; represents the weighting coefficient; Represents the basic time slice, which is the multiplication result mentioned above.

[0063] For example, taking a second thread including a first thread, a high priority thread, a medium priority thread, and a low priority thread as an example, assuming The preset weight coefficient of the first thread is 10, the preset weight coefficient of the high priority thread is 5, the preset weight coefficient of the medium priority thread is 3, the preset weight coefficient of the low priority thread is 1, the total time slice is 1000us, and the reserved time slice is 100us. Substituting the above data into formula (1), we get us.

[0064] S402: The BMC obtains a preset maximum allowed time slice of the first thread.

[0065] Since different types of CPLDs require different clock signal frequencies when upgrading, the CPU occupancy requirements are also different. The higher the occupancy, the more time slices are required.

[0066] The BMC can determine the model by reading the identification information of the upgraded CPLD, and then determine the target maximum allowable time slice based on the mapping relationship between the model and the preset maximum allowable time slice, that is, the maximum allowable time slice preset by the first thread. .

[0067] S403: The BMC determines the minimum time slice value between the basic time slice and the maximum allowed time slice as the target time slice.

[0068] The target time slice is determined by the following formula (2).

[0069]

[0070] like is the minimum of the two, then is the target time slice. If the base time slice is the minimum of the two, then the base time slice is the target time slice.

[0071] S404: The BMC detects the jitter rate of the clock signal generated in the target time slice.

[0072] The BMC can create an extended policy module of the Completely Fair Scheduler (CFS) to detect the jitter rate of the clock signal generated under the target time slice, where the jitter rate can be determined based on the standard deviation of the clock signal in a preset period.

[0073] S405: If the jitter rate is less than or equal to the preset jitter rate threshold, the BMC determines the target time slice as the time slice allocated to the first thread.

[0074] If the jitter rate of the clock signal is less than or equal to the preset jitter rate threshold, it means that the usage requirement is met, and the BMC determines the target time slice as the time slice allocated to the first thread.

[0075] In the above embodiment of the present application, the controller determines the basic time slice allocated to the first thread based on the total time slice and the reserved time slice, and obtains the maximum allowed time slice preset for the first thread, and determines the minimum time slice value between the basic time slice and the maximum allowed time slice as the target time slice. The jitter rate of the clock signal generated under the target time slice is detected. If the jitter rate is less than or equal to the preset jitter rate threshold, the target time slice is determined as the time slice allocated to the first thread. This embodiment determines the basic time slice based on the total time slice and the reserved time slice, and forms a safety threshold range in combination with the maximum allowed time slice of the first thread to avoid excessive or insufficient resource allocation. By taking the minimum value to determine the target time slice, it not only guarantees the basic resource requirements of the upgraded business, but also prevents the risk of system resource preemption due to excessive time slices. By detecting the clock signal jitter rate under the target time slice in real time and comparing it with the preset threshold for verification, it is ensured that the allocated time slice can generate a stable clock signal that meets the business upgrade requirements. Compared with the resource allocation method in the related art, the resource allocation efficiency is improved.

[0076] In the above embodiment, if the BMC detects that the jitter rate is greater than the preset jitter rate threshold and the base time slice is the target time slice, it is necessary to re-determine the time slice allocated to the first thread.

[0077] See Figure 6 , Figure 6 A flowchart of another method for determining a time slice allocated to a first thread provided in an embodiment of the present application is provided. The controller 01, taking the BMC as an example, is configured to perform the following steps:

[0078] S601: Determine an adjustment time slice according to a target time slice, a jitter rate, and a preset jitter rate threshold.

[0079] The adjusted time is the time slice allocated to the first thread that needs to be increased.

[0080] The adjustment time slice is determined by the following formula (3):

[0081]

[0082] S602: Determine an adjustment time slice threshold according to the total time slice and a preset adjustment coefficient.

[0083] Assuming the preset adjustment coefficient is 70%, 70% is multiplied by the total time slice, and the multiplication result is determined as the adjustment time slice threshold. The adjustment time slice threshold is the upper limit constraint value of the time slice that the CPU can be allocated to the upgrade service.

[0084] S603: If the sum of the adjusted time slice and the target time slice is less than the adjusted time slice threshold, determine the sum of the adjusted time slice and the target time slice as the time slice allocated to the first thread.

[0085] The sum of the adjusted and target time slices is determined. If the sum is less than the adjusted time slice threshold, the upper limit of the CPU time slice allocated to the upgrade service has been exceeded, and the normal operation of other services other than the upgrade service is not affected.

[0086] S604: If the sum of the adjusted time slice and the target time slice is greater than or equal to the adjusted time slice threshold, determine the adjusted time slice threshold as the time slice allocated to the first thread.

[0087] If the sum of the time slices is greater than or equal to the adjusted time slice threshold, it indicates that the upper limit constraint value of the time slice that the CPU can allocate to the upgrade business has been exceeded, affecting the normal operation of other non-upgraded businesses. Therefore, the adjusted time slice threshold is determined as the time slice allocated to the first thread to ensure the normal operation of the non-upgraded business.

[0088] In the above embodiment of the present application, the BMC determines the adjustment time slice based on the target time slice, the jitter rate and the preset jitter rate threshold, and determines the adjustment time slice threshold based on the total time slice and the preset adjustment coefficient. If the sum of the adjustment time slice and the target time slice is less than the adjustment time slice threshold, the sum of the adjustment time slice and the target time slice is determined as the time slice allocated to the first thread. If the sum of the adjustment time slice and the target time slice is greater than or equal to the adjustment time slice threshold, the adjustment time slice threshold is determined as the time slice allocated to the first thread. In this embodiment, when the jitter rate preset jitter rate threshold is detected, the time slice required to be added is dynamically calculated based on the jitter rate deviation, the resource allocation upper limit is determined by the total time slice and the adjustment coefficient, and the time slice allocated to the first thread is determined based on the size relationship between the sum of the adjustment time slice and the target time slice and the resource allocation upper limit, so that other businesses can also operate normally while ensuring that the upgraded business can proceed normally.

[0089] In the present application, the time slice allocated to the second thread may also be determined based on the time slice allocated to the first thread.

[0090] See Figure 7 , Figure 7 This is a flowchart of a method for allocating a time slice to a second thread provided in an embodiment of the present application. The controller 01, taking the BMC as an example, is configured to perform the following steps:

[0091] S701: Obtain a first weight coefficient preset for a first thread, a third weight coefficient preset for a first sub-thread, a fourth weight coefficient preset for a second sub-thread, and a fifth weight coefficient preset for a third sub-thread.

[0092] As in the above embodiment, the first sub-thread is a high-priority thread in the second thread, the second sub-thread is a medium-priority thread in the second thread, and the third sub-thread is a low-priority thread in the second thread.

[0093] The BMC obtains a first weight coefficient preset for the first thread, which may be, for example, 10. A third weight coefficient preset for the high-priority thread, which may be, for example, 5. A fourth weight coefficient preset for the medium-priority thread, which may be, for example, 3. And a fourth weight coefficient preset for the low-priority thread, which may be, for example, 1.

[0094] S702 : Determine the total weight of the second thread by performing a summation calculation based on the first weight coefficient, the third weight coefficient, the fourth weight coefficient, and the fifth weight coefficient.

[0095] The sum of the second thread weights is , where j represents the jth thread in the second thread; p represents the total number of threads in the second thread.

[0096] S703: Determine the time slice allocated to the second thread according to the sum of the second thread weights and the time slice allocated to the first thread.

[0097] A remaining time slice is determined according to the total time slice, the reserved time slice, and the time slice allocated to the first thread.

[0098] The remaining time slice is determined by the following formula (4):

[0099]

[0100] in, Represents the time slice allocated to the first thread.

[0101] For each sub-thread in the second thread, the weight coefficient corresponding to each sub-thread is divided by the sum of the second thread weights to determine the weight ratio of each sub-thread, and the weight ratio of each sub-thread is multiplied by the remaining time slice to obtain the multiplication result of each sub-thread. The multiplication result corresponding to each sub-thread is the time slice allocated to each sub-thread.

[0102] The time slice allocated to each sub-thread is determined by the following formula (5):

[0103]

[0104] in, Indicated as the first The time slice allocated to each thread; Indicates the second thread The weight coefficient of each thread; represents the weight coefficient of the jth thread in the second thread; Indicates the second thread The weight ratio of the threads.

[0105] After determining the time slice allocated to the second thread and allocating it, detect the current total resource usage of the CPU. If the total resource usage exceeds the usage threshold, for example, 90%, start from the low-priority threads in the second thread, first reduce the time slices occupied by the low-occupancy threads, then reduce the time slices occupied by the medium-occupancy threads, and then reduce the time slices occupied by the high-occupancy threads. If the time slices still cannot be met, continue to reduce the time slices occupied by the medium-priority threads in the second thread until the time slices are met.

[0106] In the above embodiment of the present application, a first weight coefficient preset for the first thread, a third weight coefficient preset for the first sub-thread, a fourth weight coefficient preset for the second sub-thread, and a fifth weight coefficient preset for the third sub-thread are obtained, and the sum of the first, third, fourth, and fifth weight coefficients is added to determine the total weight of the second thread. Furthermore, the time slice allocated to the second thread is determined based on the total weight of the second thread and the time slice allocated to the first thread. This embodiment makes the allocation of the second thread more reasonable and improves the stability of the second thread in performing other services.

[0107] In the present application, when the controller 01 generates the required clock signal within the time slice allocated to the first thread, it is specifically used to generate the required multiple clock signals in each cycle in sequence based on the time slice allocated to the first thread, with a preset number of time slices as one cycle.

[0108] For any cycle, if a preset number of consecutive abnormal clock signals are detected within the cycle, at least one time slice is added within the cycle to generate a normal clock signal.

[0109] In this embodiment, the above-mentioned time slice lending mechanism can be adopted for the first thread, allowing the first thread to temporarily overuse, i.e., increase the time slice, within the current cycle. However, it should be noted that in subsequent cycles, it needs to be repaid in installments according to a preset ratio. This mechanism improves the stability of the second thread.

[0110] The controller 01 in the present application may also utilize a watchdog mechanism. When it is detected that an abnormality occurs in the way the processor 02 is allocated resources in the present application, the resources of the processor 02 may be allocated by the static resource allocation method in the related art.

[0111] The present application further provides an electronic device, including a logic device 03 and a service upgrade system according to any one of the above embodiments, wherein the logic device 03 may be a target object for performing service upgrade, and the target object may be a CPLD.

[0112] The method of the present application is compared with the method of allocating resources of the processor 02 in the related art. The comparison results are shown in Table 1:

[0113] Table 1

[0114]

[0115] It can be seen that the method of allocating resources of the processor 02 in the present application significantly reduces the CPLD upgrade failure rate compared with the related art.

[0116] This application also provides a service upgrade method, see Figure 8 , Figure 8 This is a flow chart of a service upgrade method provided in an embodiment of the present application. The execution subject of the method may be an electronic device, which includes a CPLD and a service upgrade system. The service upgrade system includes a processor 02 and a controller 01. The method may include the following steps:

[0117] S801 : The controller 01 divides the monitored threads into a first thread for performing an upgrade service and a second thread for performing a non-upgrade service.

[0118] S802: The controller 01 obtains the total time slice and the reserved time slice preset by the processor 02, and determines the time slice allocated to the first thread based on the total time slice, the reserved time slice and the preset time slice dynamic allocation algorithm.

[0119] The allocated time slice is used to represent the duration allocated to the first thread for using the processor 02 resources.

[0120] S803: The controller 01 generates a required clock signal within the time slice allocated by the first thread. The clock signal is used for service upgrade.

[0121] The specific implementation process and technical effects of each step have been described in the multiple embodiments above. Please refer to the above embodiments and will not be repeated here to avoid redundancy. The method of this application controls the CLK period jitter to within ±1.5μs, while the related art is around ±5μs, which increases the CPLD upgrade success rate from 95% in the related art to over 99.9%.

[0122] In order to facilitate a better understanding of the upgrade scenario of the present application, the following embodiment illustrates the process of upgrading the firmware in the CPLD by generating a clock signal through the service upgrade method of the present application.

[0123] CPLD upgrades usually use the Joint Test Action Group (JTAG) or similar interfaces, such as the Serial Peripheral Interface (SPI) or the Inter-Integrated Circuit (I2C) bus, to program data. Figure 9 as well as Figure 10 Describe the CPLD upgrade process. Figure 9 A schematic diagram of the structure of a CPLD provided in an embodiment of the present application is shown in FIG. Figure 10 A schematic diagram of the structure and function of a CPLD provided in an embodiment of the present application.

[0124] like Figure 9 As shown, the CPLD includes but is not limited to: a test access port (TAP), a test access port controller (TAPC), an instruction register (IR), and a test data register (TDR), where the test data register can also be referred to as a data register.

[0125] The Test Mode Select (TMS) signal serves as an input to the TAPC. By changing the level on the rising edge of TCK, the TAPC state machine switches between different states, thereby determining the JTAG test operation mode, such as selecting instruction register operation or test data register operation. The Test Data In (TDI) signal is used to serially input test data, instructions, and other information into the instruction register and test data registers. Test data registers include but are not limited to device flag registers, bypass registers, and boundary scan registers. The instruction register operation or test data register output is connected to a multiplexer, which outputs the output through the Test Data Out (TDO) signal based on the TAPC control signal.

[0126] During the CPLD configuration process, TAP acts as a bridge for data transmission.

[0127] TAPC is the core of controlling the entire JTAG operation. TAPC transforms the TMS signal according to TCK and test mode selection, outputs various timings and modes required by IR and TDR, and generates control signals for IR and TDR to capture, shift, and update.

[0128] TAPC is a 16-state synchronous finite state machine. Figure 10 As shown in Figure 1, the state machine can be divided into three columns, corresponding to reset operation, test data register operation and instruction register operation. The data on the state switching line is TMS, and the state of TAPC is switched on the rising edge of TCK.

[0129] exist Figure 10 The Test-Logic-Reset state is the initial state of the state machine. When the TMS signal remains high for multiple cycles on the rising edge of TCK, the state machine enters this state, resetting the TAPC and returning it to its initial ready state. The Run-Test / Idle state indicates that no test operation is currently in progress, or that the test logic is in an idle wait state. Starting from the Test-Logic-Reset state, if TMS is 0, the state machine enters this state.

[0130] Test data register operation corresponding to the data column status:

[0131] Select-DR-Scan, the data register scan state, is entered from the Run-Test / Idle state. If TMS is 1, this state is entered to select the TDR scan operation. Capture-DR, the data register state is entered from the Select-DR-Scan state if TMS is 0. In this state, the TAPC captures the current data value into the TDR. Shift-DR, the data register state is entered from the Capture-DR state if TMS is 0. Under the drive of TCK, the TDR data is input bit by bit through the test data input pin TDI, while the original data is output bit by bit through the test data output pin TDO, completing the data shift operation. Exit1-DR, the data register shift state, is entered from the Shift-DR state if TMS is 1, marking the end of the data shift operation and preparing for the next state. Pause-DR, the data register operation state is entered from the Exit1-DR state if TMS is 0. This state is used to pause the current data operation. Exit2–DR: In the Pause-DR state, if TMS is 1, this state is entered. Update–DR: In the Exit1-DR or Exit2-DR state, if TMS is 0, this state is entered. The data in TDR is updated to the target location.

[0132] The data column status corresponding to the instruction register operation:

[0133] Select-IR-Scan: From the Run-Test / Idle state, if TMS is continuously 1, this state is entered after Select-DR-Scan to select the IR scan operation. Capture-IR: From the Select-IR-Scan state, if TMS is 0, this state is entered. Instruction-related data is captured into the IR. Shift-IR: From the Capture-IR state, if TMS is 0, this state is entered. New instruction data is input bit by bit through the TDI pin, while the original instruction data is output bit by bit through the TDO pin. Exit-IR: From the Shift-IR state, if TMS is 1, this state is entered to terminate the instruction shift operation. Pause-IR: From the Exit1-IR state, if TMS is 0, this state is entered to pause the instruction register operation. Exit-IR: From the Pause-IR state, if TMS is 1, this state is entered. Update Instruction Register state Update-IR: In Exit1-IR or Exit2-IR state, if TMS is 0, enter this state. Update the new instruction data into IR so that the corresponding test operation can be performed according to the instruction.

[0134] The instruction register is 10 bits long. It receives and decodes instructions, generates control signals, selects test data registers for placement in the TDI to TDO scan link, and controls the source and destination of the test data registers. When the TAPC enters the instruction capture state (Capture-IR), the instruction register captures the data {1'b0, busy, wakedown_over, wakeup_over, init_n, init, isc_enabled, isc_done, 2'b01} on the rising edge of TCK. Busy indicates the embedded FLASH is busy, wakedown_over indicates wakeup completion, wakeup_over indicates wakeup completion, init_n indicates INIT_FLAG_N, init indicates device initialization completion, isc_enabled indicates JTAG ISC operation enablement, and isc_done indicates JTAG ISC operation completion. The two least significant bits are fixed to 01 to verify scan link integrity and facilitate fault location. When writing instructions to the instruction register, the lower bits are written first. When TAPC enters the instruction update state (Update-IR), the currently executed instruction is updated at the falling edge of TCK.

[0135] When the test data register is in programming mode and the CPLD is being updated, the BMC transmits configuration data to the CPLD via the TDR. The TDR acts as a temporary buffer, storing the bitstream to be written and shifting it bit by bit into the target register according to the TCK. When reading the CPLD's internal state, data is shifted from the device's internal register chain to the TDR for the BMC to read.

[0136] Based on the above content, the following describes the specific method of CPLD upgrade:

[0137] The essence of BMC upgrading CPLD is to simulate the hardware programming timing through software, replacing the above-mentioned JTAG programmer to complete firmware burning.

[0138] First, the firmware of the CPLD to be upgraded is pre-configured and then transferred to the BMC.

[0139] The CPLD firmware to be upgraded is transferred to the BMC. This is the starting point of the upgrade. It is necessary to obtain the adapted CPLD firmware file in advance, and then transfer the firmware to the BMC for storage through a certain method, such as network transmission.

[0140] Only when the correct firmware is prepared can the CPLD be upgraded based on the firmware. This is the material basis of the entire upgrade process. If the firmware is incorrect or not successfully transferred to the BMC, the subsequent steps cannot be performed.

[0141] Then reset the TAP and configure the instruction register to initialize the JTAG protocol.

[0142] Reset the TAPC state machine to its initial state (Test-Logic-Reset). This step ensures that the TAPC and related registers are in a known initial state to prevent residual operations from affecting subsequent JTAG operations. Configure the instruction register. After the TAP is reset, enter the relevant state, such as through the Select-IR-Scan, Capture-IR, and Shift-IR states, and shift the instruction bit by bit into the IR through the TDI.

[0143] Resetting the TAP is a prerequisite for configuring the instruction register. Only by ensuring that the TAPC is in its initial state can the instruction register be correctly configured. Initializing the JTAG protocol is a prerequisite for firmware programming. Only by properly initializing the JTAG protocol can the accuracy and stability of subsequent JTAG transmission of instructions and data be guaranteed. If JTAG protocol initialization fails, the instructions and data sent during firmware programming may not be correctly received and processed by the CPLD.

[0144] To program the firmware, the first step is to send an ERASE command. This command is specifically used to erase the CPLD's internal FLASH area, which stores the firmware. Specifically, the command is sent to the CPLD via the TDI pin, using the initialized JTAG protocol, to erase the FLASH area within the CPLD, which stores the firmware. This step clears the old firmware data and prepares for writing the new firmware. Failure to perform this erase operation before writing the new firmware may result in errors. A 512-byte block transfer method can be used. The BMC emulates the JTAG protocol's four-wire timing sequence (TCK, TMS, TDI, and TDO) using GPIO pins. TCK synchronizes data transmission, TMS controls the CPLD state machine transitions, TDI sends configuration data, and TDO reads back data. During the transfer process, a block-by-block readback is performed for verification. After each block of data is transferred, the data received by the CPLD is read via TDO and compared with the data sent to ensure data accuracy.

[0145] Erasing the flash memory is a prerequisite for slice transfer and verification. Only after erasing the old data can the new firmware slice data be correctly written. Slice transfer and verification are crucial for a successful firmware burn. Block-by-block transfer and verification ensure that the entire firmware is accurately burned into the CPLD. Incomplete erasure can cause the new firmware to fail to write. Problems with slice transfer or verification can cause firmware data errors, leading to malfunctioning CPLDs after the upgrade.

[0146] In this embodiment, the CPLD upgrade process is a common process and will not be described in more detail. The focus of this application is to use the service upgrade system in this application to better allocate CPU resources, so that the BMC can generate a more stable clock signal, and then use the generated stable clock signal to upgrade the CPLD.

[0147] The electronic device provided in the present application may include, in addition to the logic device and the service upgrade system of any of the above embodiments, a communication component, a memory, and a bus.

[0148] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0149] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0150] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned service upgrade method embodiments when running.

[0151] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0152] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned service upgrade method embodiments are implemented.

[0153] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned service upgrade method embodiments are implemented.

[0154] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0155] The above is a detailed introduction to a service upgrade system, electronic device, method, storage medium and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A service upgrade system, characterized in that: include: A processor and a controller connected to the processor; The controller is configured to divide the monitored threads into a first thread for performing an upgrade service and a second thread for performing a non-upgrade service; The controller is further configured to obtain a total time slice and a reserved time slice preset by the processor; Obtaining a first weight coefficient preset for the first thread, a second weight coefficient preset for the second thread, and a preset weighting coefficient; Determine a first thread weight sum by performing a sum calculation based on the first weight coefficient and the second weight coefficient; Subtracting the total time slice from the reserved time slice to obtain a time slice difference; Dividing the time slice difference by the sum of the first thread weights to obtain a division result; Multiplying the division result by the weighting coefficient to obtain a multiplication result, where the multiplication result is the basic time slice allocated to the first thread; Obtaining a maximum allowed time slice preset by the first thread; Determine the minimum time slice value between the basic time slice and the maximum allowed time slice as the target time slice; detecting a jitter rate of a clock signal generated in the target time slice; If the jitter rate is less than or equal to a preset jitter rate threshold, determining the target time slice as the time slice allocated to the first thread; If it is detected that the jitter rate is greater than the preset jitter rate threshold, and the base time slice is a target time slice, determining an adjusted time slice according to the target time slice, the jitter rate, and the preset jitter rate threshold, where the adjusted time is the time slice that needs to be increased allocated to the first thread; Determining an adjustment time slice threshold according to the total time slice and a preset adjustment coefficient; If the sum of the adjusted time slice and the target time slice is less than the adjusted time slice threshold, determining the sum of the adjusted time slice and the target time slice as the time slice allocated to the first thread; If the sum of the adjusted time slice and the target time slice is greater than or equal to the adjusted time slice threshold, the adjusted time slice threshold is determined as the time slice allocated to the first thread; the time slice allocated to the first thread is used to represent the duration allocated to the first thread for using processor resources; The controller is further configured to generate a required clock signal within the time slice allocated by the first thread, wherein the clock signal is used for performing service upgrade.

2. The service upgrade system according to claim 1, characterized in that: The controller is also used to: The time slice allocated to the second thread is determined according to the time slice allocated to the first thread.

3. The service upgrade system according to claim 2, characterized in that: The second thread includes multiple sub-threads, and the controller is further configured to: Priority is divided for each sub-thread in the second thread to obtain a first sub-thread, a second sub-thread, and a third sub-thread, wherein the priority of the first sub-thread is greater than that of the second sub-thread, and the priority of the second sub-thread is greater than that of the third sub-thread.

4. The service upgrade system according to claim 3, characterized in that: When the controller determines the time slice allocated to the second thread according to the time slice allocated to the first thread, the controller specifically includes: Obtaining a first weight coefficient preset for the first thread, a third weight coefficient preset for the first sub-thread, a fourth weight coefficient preset for the second sub-thread, and a fifth weight coefficient preset for the third sub-thread; Determine a second thread weight sum by performing a sum calculation based on the first weight coefficient, the third weight coefficient, the fourth weight coefficient, and the fifth weight coefficient; Determine the time slice allocated to the second thread according to the sum of the weights of the second threads and the time slice allocated to the first thread.

5. The service upgrade system according to claim 4, characterized in that: When the controller determines the time slice allocated to the second thread according to the sum of the weights of the second threads and the time slice allocated to the first thread, the controller is specifically configured to: determining a remaining time slice according to the total time slice, the reserved time slice, and the time slice allocated to the first thread; For each sub-thread in the second thread, dividing the weight coefficient corresponding to each sub-thread by the sum of the weights of the second threads to determine a weight ratio of each sub-thread; The weight ratio of each sub-thread is multiplied by the remaining time slice to obtain the multiplication result of each sub-thread, and the multiplication result corresponding to each sub-thread is the time slice allocated to each sub-thread.

6. The service upgrade system according to claim 1, characterized in that: When the controller generates the required clock signal within the time slice allocated by the first thread, the controller is specifically configured to: According to the time slices allocated to the first thread, a preset number of time slices is used as a cycle, and multiple required clock signals are generated in each cycle in sequence.

7. The service upgrade system according to claim 5, characterized in that: The controller is also used to: For any cycle, if a preset number of consecutive abnormal clock signals are detected within the cycle, at least one time slice is added within the cycle to generate a normal clock signal.

8. An electronic device, characterized in that: The service upgrade system comprising a logic device as claimed in any one of claims 1 to 7, wherein the logic device is a target object for performing service upgrade.

9. A method for service upgrade, characterized in that: include: Dividing the monitored threads to obtain a first thread for performing an upgrade service and a second thread for performing a non-upgrade service; Get the total time slice and reserved time slice preset by the processor; Obtaining a first weight coefficient preset for the first thread, a second weight coefficient preset for the second thread, and a preset weighting coefficient; Determine a first thread weight sum by performing a sum calculation based on the first weight coefficient and the second weight coefficient; Subtracting the total time slice from the reserved time slice to obtain a time slice difference; Dividing the time slice difference by the sum of the first thread weights to obtain a division result; Multiplying the division result by the weighting coefficient to obtain a multiplication result, where the multiplication result is the basic time slice allocated to the first thread; Obtaining a maximum allowed time slice preset by the first thread; Determine the minimum time slice value between the basic time slice and the maximum allowed time slice as the target time slice; detecting a jitter rate of a clock signal generated in the target time slice; If the jitter rate is less than or equal to a preset jitter rate threshold, determining the target time slice as the time slice allocated to the first thread; If it is detected that the jitter rate is greater than the preset jitter rate threshold, and the base time slice is a target time slice, determining an adjusted time slice according to the target time slice, the jitter rate, and the preset jitter rate threshold, where the adjusted time is the time slice that needs to be increased allocated to the first thread; Determining an adjustment time slice threshold according to the total time slice and a preset adjustment coefficient; If the sum of the adjusted time slice and the target time slice is less than the adjusted time slice threshold, determining the sum of the adjusted time slice and the target time slice as the time slice allocated to the first thread; If the sum of the adjusted time slice and the target time slice is greater than or equal to the adjusted time slice threshold, the adjusted time slice threshold is determined as the time slice allocated to the first thread; the time slice allocated to the first thread is used to represent the duration allocated to the first thread for using processor resources; A required clock signal is generated within the time slice allocated by the first thread, where the clock signal is used for performing service upgrade.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the service upgrade method according to claim 9 when executed by a processor.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the service upgrade method according to claim 9 are implemented.

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