Packaging structure and forming method thereof
By flattening the side pads of the chip stack structure, coplanaring them and forming electrically connected soldering bumps, the problem of poor soldering during semiconductor chip stacking is solved, and the reliability and stability of the packaging structure are improved.
Patent Information
- Application Number
- CN202510455428.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2025-07-22
AI Technical Summary
In the existing 3D packaging technology, when semiconductor chips are stacked in sequence parallel to the upper surface of the substrate, welding defects such as dummy welding, desoldering or continuous welding are prone to occur.
By flattening the portion of the side pad of the chip stack structure with non-coplanar defects, it is coplanar, and a soldering protrusion is formed electrically connected to the side pads. Then, the side surface of the exposed side pad of the chip stack structure is mounted on the substrate, so that the soldering protrusion is soldered with the pad of the substrate.
It effectively prevents the occurrence of welding defects such as dummy welding, de-soldering or continuous welding, and improves the reliability and stability of the packaging structure.
Smart Images
Figure CN120356829A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of packaging technology, and particularly to a packaging structure and a method for forming the same. Background Art
[0002] As it becomes increasingly difficult to miniaturize chips, and the market's pursuit of high-performance chips remains unabated, the industry has begun to explore breakthroughs in the field of packaging. In recent years, advanced IC packaging technologies such as 2.5D / 3D have become a focus of competition among foundries, packaging and testing factories, IDMs, chip design manufacturers, and EDA manufacturers.
[0003] 3D packaging technology stacks different chips such as CPUs, accelerators, memories, I / Os, power management, etc. together to form a three-dimensional structure. The main advantages of 3D packaging technology include: 3D packaging technology can stack multiple chips vertically along the direction perpendicular to the substrate, thereby improving the integration and performance of the chips; compared with the traditional planar connection method, it can reduce the total wiring length between the chips to increase the bandwidth, improve the signal delay, and thus improve the reliability and stability of the packaging structure. Existing 3D packaging technologies generally stack several semiconductor chips vertically along the direction perpendicular to the upper surface of the substrate. This stacking method will occupy a large substrate area and is not conducive to heat dissipation. Therefore, a 3D packaging technology that stacks several semiconductor chips horizontally along the direction parallel to the upper surface of the substrate has emerged. While improving the integration, it is beneficial to the heat dissipation of the stacked chips. When electrically connecting the semiconductor chips to the substrate in this 3D packaging technology, the side pads on the side of the semiconductor chip are welded to the corresponding side pads on the substrate. This method may cause welding defects such as virtual soldering, de-soldering, or bridging. Summary of the Invention The purpose of this application is to provide a packaging structure and a method for forming the same, which can prevent welding defects such as virtual soldering, de-soldering, or bridging when multiple semiconductor chips are stacked horizontally along the direction parallel to the upper surface of the substrate. To achieve the above purpose, on the one hand, an embodiment of this application provides a method for forming a packaging structure, including: Providing a chip stack structure, the chip stack structure includes a plurality of first semiconductor chips stacked in sequence, the chip stack structure includes four sides, and a side of the chip stack structure exposes the side pads of the corresponding sides of the plurality of first semiconductor chips, and the side pads have non-coplanar defects; Providing a carrier board, mounting one side of the chip stack structure on the upper surface of the carrier board, so that the side of the chip stack structure exposing the side pads is away from the upper surface of the carrier board; Forming a coating layer covering the chip stack structure; A planarization process is used to remove a part of the cladding layer, a part of the side surfaces of the chip stack structure away from the upper surface of the carrier board, and a part of the side pads, so that the side pads of different first semiconductor chips exposed on the side surfaces of the chip stack structure away from the upper surface of the carrier board are coplanar; After the planarization process, welding bumps are formed and electrically connected to the side pads; Remove the carrier board; Provide a substrate, and the upper surface of the substrate has a number of discrete first pads; Mount the side surface of the chip stack structure with the exposed side pads on the upper surface of the substrate, so that the welding bumps are welded to the corresponding first pads.
[0004] In some embodiments, the side pads are formed synchronously with the wiring layer of the first semiconductor chip.
[0005] In some embodiments, each of the first semiconductor chips in the chip stack structure includes an opposite active surface and a back surface, and four side surfaces located on the active surface and the back surface. One of the side surfaces of the first semiconductor chip has the side pad, and the surface of the side pad is exposed. The active surfaces and the back surfaces of the first semiconductor chips in the upper and lower layers of the chip stack structure are arranged oppositely.
[0006] In some embodiments, the active surface of the upper first semiconductor chip in the chip stack structure is arranged opposite to the back surface of the adjacent lower first semiconductor chip.
[0007] In some embodiments, the back surface of the upper first semiconductor chip in the chip stack structure is arranged opposite to the active surface of the adjacent lower first semiconductor chip.
[0008] In some embodiments, there is no electrical connection between the upper first semiconductor chip and the adjacent lower semiconductor chip.
[0009] In some embodiments, there is an adhesive layer or a bonding layer between the active surface or the back surface of the upper first semiconductor chip and the corresponding back surface or active surface of the adjacent lower semiconductor chip.
[0010] In some embodiments, there is an electrical connection between the upper first semiconductor chip and the adjacent lower semiconductor chip.
[0011] In some embodiments, the active surface of the first semiconductor chip has external pads, the first semiconductor chip has a via connection structure electrically connected to the external pads, and one end surface of the via connection structure is exposed on the back surface of the first semiconductor chip. The external pads on the active surface or the via connection structure on the back surface of the upper first semiconductor chip are soldered to the corresponding via connection structure on the back surface or the external pads on the active surface of the adjacent lower semiconductor chip.
[0012] In some embodiments, the planarization process is a chemical mechanical polishing process.
[0013] In some embodiments, the material of the coating layer includes resin.
[0014] In some embodiments, one side surface of the chip stack structure is mounted on the upper surface of the carrier board through a temporary bonding layer. In some embodiments, mounting one side surface of the chip stack structure on the upper surface of the carrier board includes: mounting one side surface of one chip stack structure on the upper surface of the carrier board.
[0015] In some embodiments, mounting one side surface of the chip stack structure on the upper surface of the carrier board includes: mounting one side surfaces of a plurality of chip stack structures on the upper surface of the carrier board.
[0016] In some embodiments, one side surfaces of a plurality of chip stack structures are mounted on the upper surface of the carrier board, and the plurality of chip stack structures are arranged in an array.
[0017] In some embodiments, after forming the solder bumps electrically connected to the side pads, it further includes: dividing the coating layer to form a plurality of discrete chip stack structures with coating layers.
[0018] In some embodiments, forming the solder bumps electrically connected to the side pads includes: forming solder bumps directly electrically connected to the side pads.
[0019] In some embodiments, forming the solder bumps electrically connected to the side pads includes: after the planarization process, forming a redistribution layer on the surface of the planarized coating layer, the redistribution layer being electrically connected to the solder bumps; forming solder bumps on the surface of the redistribution layer, the solder bumps being electrically connected to the redistribution layer.
[0020] In some embodiments, the redistribution layer includes a passivation layer and a plurality of discrete redistribution metal layers located in the passivation layer, and the redistribution metal layers are electrically connected to the corresponding side pads and solder bumps.
[0021] In some embodiments, the non-coplanarity defect of the side pads includes: some side pads on the sides of different first semiconductor chips in the chip stack structure are non-coplanar, and the side pads on the side of the same first semiconductor chip are coplanar.
[0022] In some embodiments, the non-coplanarity defect of the side pads includes: some side pads on the sides of different first semiconductor chips in the chip stack structure are non-coplanar, and some side pads on the side of the same first semiconductor chip are non-coplanar.
[0023] On the other hand, the present application also provides a packaging structure, including: A substrate, the upper surface of the substrate having a plurality of discrete first pads; A chip stack structure located on the upper surface of the substrate, the chip stack structure including a plurality of first semiconductor chips stacked in sequence along a direction parallel to the upper surface of the substrate, and side pads on the corresponding sides of the plurality of first semiconductor chips are exposed on a surface of the chip stack structure close to and parallel to the upper surface of the substrate; A coating layer covering the chip stack structure, and the side pads are exposed by the coating layer; A redistribution layer located between the coating layer and the surface of the chip stack structure close to and parallel to the upper surface of the substrate, the redistribution layer being electrically connected to the side pads; A solder bump located between the redistribution layer and the upper surface of the substrate, the solder bump welding the redistribution layer to the corresponding first pad.
[0024] In some embodiments, each of the first semiconductor chips in the chip stack structure includes an active surface and a back surface that are opposite and perpendicular to the upper surface of the substrate, and four sides located between the active surface and the back surface. A side of the first semiconductor chip close to and parallel to the upper surface of the substrate has the side pad and exposes the surface of the side pad. The active surfaces and back surfaces of the upper and lower first semiconductor chips in the chip stack structure are oppositely arranged.
[0025] In some embodiments, there is no electrical connection between the upper first semiconductor chip and the adjacent lower semiconductor chip, and there is an adhesive layer or a bonding layer between the active surface or the back surface of the upper first semiconductor chip and the corresponding back surface or active surface of the adjacent lower semiconductor chip.
[0026] In some embodiments, there is an electrical connection between the first semiconductor chip in the upper layer and the adjacent semiconductor chip in the lower layer; the active surface of the first semiconductor chip has external pads, and the first semiconductor chip has a via connection structure electrically connected to the external pads, and one end surface of the via connection structure is exposed on the back surface of the first semiconductor chip. The external pads on the active surface or the via connection structure on the back surface of the first semiconductor chip in the upper layer are soldered to the corresponding via connection structure on the back surface or the external pads on the active surface of the adjacent semiconductor chip in the lower layer.
[0027] In some embodiments, the side pads and the wiring layer of the first semiconductor chip are an integral structure.
[0028] In some embodiments, the redistribution layer includes a passivation layer and a plurality of discrete redistribution metal layers located in the passivation layer, and the redistribution metal layers are electrically connected to the corresponding side pads and solder bumps.
[0029] In some embodiments, it further includes: a second semiconductor chip mounted on the upper surface of a substrate on one side of the chip stack structure, and the second semiconductor chip is soldered to the corresponding first pads.
[0030] Advantages of the present application: The packaging structure of the present application and its forming method first provide a chip stack structure. The chip stack structure includes a plurality of first semiconductor chips stacked in sequence. The chip stack structure has four sides. One side of the chip stack structure exposes the side pads on the corresponding sides of the plurality of first semiconductor chips, and there are non-coplanarity defects in the side pads. Then, the chip stack structure is mounted on the upper surface of a carrier board. After the side of the chip stack structure exposing the side pads is away from the upper surface of the carrier board, a coating layer covering the chip stack structure is formed. A planarization process is used to remove part of the coating layer, part of the side surfaces of the chip stack structure away from the upper surface of the carrier board, and part of the side pads, so that the side pads of different first semiconductor chips exposed on the side surfaces of the chip stack structure away from the upper surface of the carrier board are coplanar. After the planarization process, welding bumps electrically connected to the side pads are formed. The carrier board is removed. A substrate is provided, and the upper surface of the substrate has a number of discrete first pads. The side surface of the chip stack structure exposing the side pads is mounted on the upper surface of the substrate, so that the welding bumps are welded to the corresponding first pads. In the present application, through the foregoing steps, it is possible to simply make the side pads with non-coplanarity defects in the chip stack structure coplanar through the planarization process. After the planarization process, welding bumps electrically connected to the side pads are formed. Since the side pads on the side surfaces of the chip stack structure are coplanar after the planarization process, the formed welding bumps will not have problems of uneven height. Therefore, when the side surface of the chip stack structure exposing the side pads is mounted on the upper surface of the substrate and the welding bumps are welded to the corresponding first pads on the upper surface of the substrate, there will be no welding defects such as virtual soldering, desoldering, or bridging between the welding bumps on the side pads and the first pads on the upper surface of the substrate. Description of the Drawings
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0032] Figure 1 It is a schematic structural diagram after providing a chip stack structure in the forming method of the packaging structure provided in some embodiments of the present application; Figure 2 It is a schematic structural diagram after mounting one side surface of the chip stack structure on the upper surface of a carrier board in the forming method of the packaging structure provided in some embodiments of the present application; Figure 3 It is a schematic structural diagram of forming a coating layer covering the chip stack structure in the forming method of the packaging structure provided in some embodiments of the present application; Figure 4 Schematic diagram of the structure after removing part of the coating layer, part of the side surface and part of the side pads of the chip stack structure away from the upper surface of the carrier board by a planarization process in the method for forming the encapsulation structure provided in some embodiments of the present application; Figure 5 Schematic diagram of the structure after forming the welding bumps electrically connected to the side pads in the method for forming the encapsulation structure provided in some embodiments of the present application; Figure 6 Schematic diagram of the structure after removing the carrier board in the method for forming the encapsulation structure provided in some embodiments of the present application; Figure 7 Schematic diagram of the structure after attaching the side surface of the exposed side pads of the chip stack structure to the upper surface of the substrate, so that the welding bumps are welded to the corresponding first pads in the method for forming the encapsulation structure provided in some embodiments of the present application; Figure 8 Schematic diagram of the structure after forming the redistribution layer in the method for forming the encapsulation structure provided in some other embodiments of the present application; Figure 9 Schematic diagram of the structure after forming the welding bumps connected to the redistribution layer in the method for forming the encapsulation structure provided in some other embodiments of the present application; Figure 10 Schematic diagram of the structure after removing the carrier board in the method for forming the encapsulation structure provided in some other embodiments of the present application; Figure 11 Schematic diagram of the structure after attaching the side surface of the exposed side pads of the chip stack structure to the upper surface of the substrate, so that the welding bumps on the redistribution layer are welded to the corresponding first pads in the method for forming the encapsulation structure provided in some other embodiments of the present application. Detailed implementation manners
[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present invention.
[0036] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0037] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" or the like specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the associated listed items.
[0038] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations caused by, for example, manufacturing techniques.
[0039] It can be understood that in the accompanying drawings of the present application specification, adjacent film layers with the same processed film layer material are drawn as connected in some figures to make them closer to the actual structure.
[0040] In the existing 3D packaging technology where several semiconductor chips are stacked in sequence along a direction parallel to the upper surface of the substrate, there will be welding defects such as virtual soldering, de-soldering, or bridging. It is found through research that when multiple semiconductor chips are stacked in sequence along a direction parallel to the upper surface of the substrate, the side pads exposed on the sides of the multiple semiconductor chips will have problems of non-coplanarity or unevenness, resulting in uneven heights of the solder balls formed on the side of the stacked chip structure and connected to the corresponding side pads. Therefore, when the solder balls on the side of the stacked chip structure are welded to the corresponding pads on the substrate, there will be welding defects such as virtual soldering, de-soldering, or bridging.
[0041] For this reason, the embodiments of the present application provide a packaging structure and a method for forming the same. Mount a chip stack structure with non-coplanar defects in side pads on the upper surface of a carrier board, such that the side of the chip stack structure exposing the side pads is away from the upper surface of the carrier board; then, form a coating layer covering the chip stack structure; next, use a planarization process to remove part of the coating layer, part of the side of the chip stack structure away from the upper surface of the carrier board, and part of the side pads, so that the side pads of different first semiconductor chips exposed on the side of the chip stack structure away from the upper surface of the carrier board are coplanar. After the planarization process, when forming welding bumps electrically connected to the side pads, since the side pads are all coplanar, uneven heights of the formed welding bumps can be prevented. Then, mount the side of the chip stack structure exposing the side pads on the upper surface of the substrate, so that when the welding bumps on the side pads are welded to the corresponding first pads on the upper surface of the substrate, welding defects such as virtual soldering, de-soldering, or bridging can be prevented.
[0042] Next, the packaging structure and the method for forming the same provided by the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings.
[0043] The embodiments of the present application first provide a method for forming a packaging structure. Figures 1 - 7 It is a schematic structural diagram of the formation process of the packaging structure provided in some embodiments of the present application. Next, in some embodiments, the formation process of the packaging structure will be described in detail with reference to the accompanying drawings.
[0044] Refer to Figure 1, a chip stack structure 100 is provided. The chip stack structure 100 includes a plurality of first semiconductor chips 101 stacked in sequence. The chip stack structure 100 includes four sides. One side 11 of the chip stack structure 100 exposes side pads 103 on corresponding sides of the plurality of first semiconductor chips 101, and the side pads 103 have non-coplanar defects.
[0045] The plurality of first semiconductor chips 101 stacked in sequence in the chip stack structure 100. Specifically, the number of the first semiconductor chips 101 can be two, three, four or more. Figure 1 Taking the chip stack structure 100 having four first semiconductor chips 101 as an example for illustration.
[0046] In some embodiments, the process of providing the chip stack structure 100 includes: providing a temporary carrier 301 and a plurality of first semiconductor chips 101. Each of the first semiconductor chips 101 includes an opposite active surface and a back surface, and four sides located on the active surface and the back surface. One of the sides of the first semiconductor chip 101 has a side pad 103, and the surface of the side pad 103 is exposed; mounting the plurality of first semiconductor chips 101 on the upper surface of the temporary carrier 301 in sequence along a direction perpendicular to the upper surface of the temporary carrier 301, and the active surface and the back surface of each first semiconductor chip 101 are parallel to the upper surface of the temporary carrier 301, and the four sides of the first semiconductor chip 101 are perpendicular to the upper surface of the temporary carrier 301, forming the chip stack structure 100. The lowermost first semiconductor chip 101 is mounted on the upper surface of the temporary carrier 301 through an adhesive layer 302; after forming the chip stack structure 10, the temporary carrier 301 is removed to facilitate subsequent processes.
[0047] The active surface of the first semiconductor chip 101 is the surface formed with semiconductor devices (not shown in the figure) and a wiring layer 104 electrically connected to the semiconductor devices. The back surface is the surface opposite to the active surface. Between the back surface and the active surface are four sides. One side of the first semiconductor chip 101 exposes a side pad 103, and the side pad 103 is electrically connected to the corresponding wiring layer 104. The side pad 103 serves as a connection port between the first semiconductor chip 101 in the chip stack structure 100 and other structures (such as a substrate provided subsequently in this application). The number of side pads 103 exposed on one side of the first semiconductor chip 101 is at least one, and specifically can be one or a plurality of discrete ones.
[0048] One side of the exposed side pads 103 of the multiple first semiconductor chips 101 in the chip stack structure 100 is located on the same side of the chip stack structure 100, such as side 11 of the chip stack structure 100.
[0049] Due to the manufacturing reasons of the first semiconductor chips 101 (such as process errors during the formation of side pads, or cutting accuracy reasons for cutting the wafer into several discrete first semiconductor chips 101) and / or the stacking process reasons when stacking several first semiconductor chips 101 once (such as alignment error reasons during stacking), there will be a defect of non-coplanarity in the side pads 103 in the formed chip stack structure 100. The defect of non-coplanarity means that among the several side pads 103 exposed on side 11 of the chip stack structure 100, the exposed surfaces of one or more side pads 103 are not in the same plane as the exposed surfaces of other side pads 103. For example, Figure 1 the exposed surface of the side pad 103 in the dashed box 12 is not in the same plane as the exposed surfaces of other side pads 103. If the side pads 103 on side 11 of the stacked chip structure 100 with non-coplanarity defects are welded to other structures (such as a substrate), due to the non-coplanarity defects of the side pads 103, the welding bumps formed on the side pads will be uneven, which easily causes problems such as virtual soldering, desoldering, or short-circuit soldering between some side pads 103 in the chip stack structure 100 and other structures (such as a substrate), affecting the welding quality.
[0050] In a specific embodiment, the non-coplanarity defect of the side pad 103 includes: partial side pads 103 on the sides of different first semiconductor chips 101 in the chip stack structure 100 are non-coplanar, and the side pads 103 on the side of the same first semiconductor chip 101 are coplanar.
[0051] In another specific embodiment, the non-coplanarity defect of the side pad 103 includes: partial side pads 103 on the sides of different first semiconductor chips 101 in the chip stack structure 100 are non-coplanar, and partial side pads 103 on the side of the same first semiconductor chip 101 are non-coplanar.
[0052] In a specific embodiment, the side pad is formed synchronously with the wiring layer of the first semiconductor chip, specifically including: forming a circuit synchronously with the corresponding scribe line side of the chip when manufacturing the wiring layer 104 on the active surface of the first semiconductor chip. After the chip is cut, the circuit is exposed on the corresponding side of the first semiconductor chip 101 to form the side pad 103. Therefore, the side pad and the wiring layer 104 of the first semiconductor chip are an integral structure.
[0053] In some embodiments, continue to refer to Figure 1When a plurality of first semiconductor chips 101 are stacked in sequence to form the chip stack structure 100, the active surface of the upper first semiconductor chip 101 is disposed opposite to the back surface of the adjacent lower first semiconductor chip 101. In some other embodiments, when a plurality of first semiconductor chips 101 are stacked in sequence to form the chip stack structure 100, the back surface of the upper first semiconductor chip 101 is disposed opposite to the active surface of the adjacent lower first semiconductor chip 101.
[0054] In some embodiments, continuing to refer to Figure 1 the upper first semiconductor chip 101 and the adjacent lower semiconductor chip are not electrically connected, and there is an adhesive layer or a bonding layer 102 between the active surface or the back surface of the upper first semiconductor chip 101 and the corresponding back surface or active surface of the adjacent lower semiconductor chip. In a specific example, there is an adhesive layer 102 between the active surface of the upper first semiconductor chip 101 and the corresponding back surface of the adjacent lower semiconductor chip, or there is an adhesive layer or a bonding layer 102 between the back surface of the upper first semiconductor chip 101 and the corresponding active surface of the adjacent lower semiconductor chip. When the upper first semiconductor chip 101 and the adjacent lower semiconductor chip are not electrically connected, the first semiconductor chips 101 in the chip stack structure 100 communicate and / or transfer data with other structures (such as a substrate) through side pads 103, and can communicate and / or transfer data between adjacent first semiconductor chips 101 through the substrate.
[0055] In some other embodiments, the first semiconductor chip 101 in the upper layer is electrically connected to an adjacent semiconductor chip in the lower layer, such that in addition to communicating and / or transferring data with other structures (such as a substrate) through the side pads 103, the first semiconductor chips 101 adjacent to each other in the chip stack structure 100 can also directly communicate and / or transfer data (without passing through the substrate), shortening the length of the signal or data transfer channel between adjacent first semiconductor chips 101, thereby improving the performance of the chip stack structure 100. In a specific example, the active surface of the first semiconductor chip 101 has external pads (not shown in the figure), the first semiconductor chip 101 has a via connection structure (not shown in the figure) electrically connected to the external pads, and one end surface of the via connection structure is exposed on the back surface of the first semiconductor chip 101. The external pads on the active surface or the via connection structures on the back surface of the first semiconductor chips 101 in the upper layer are soldered to the corresponding via connection structures on the back surfaces or the external pads on the active surfaces of the adjacent semiconductor chips in the lower layer. In a specific example, the external pads on the active surface of the first semiconductor chip 101 in the upper layer are soldered to the corresponding via connection structures on the back surfaces of the adjacent semiconductor chips in the lower layer, or the via connection structures on the back surface of the first semiconductor chip 101 in the upper layer are soldered to the corresponding external pads on the active surfaces of the adjacent semiconductor chips in the lower layer. The soldering includes a solder soldering process or a hybrid bonding soldering process. The solder soldering process can adopt a TC-NCF (Thermal Compression bonding, TC, Non-Conductive Film, NCF) process or an MR-MUF (Mass Reflow bonding with Molded Underfill, MR-MUF) process. The external pads and the corresponding via connection structures of the first semiconductor chips 101 in the upper and lower layers are soldered together with corresponding solder, and an isolation layer is filled between the first semiconductor chips 101 in the upper and lower layers. The hybrid bonding soldering process bonds the bonding layer on the active surface of the first semiconductor chip 101 in the upper layer to the bonding layer on the back surface of the semiconductor chip 101 in the lower layer. The bonding layer includes a silicon oxide layer and metal pads located in the silicon oxide layer, and the surface of the metal pads is exposed on the silicon oxide layer.
[0056] The functions of the multiple first semiconductor chips 101 in the chip stack structure 100 are the same or different. In some embodiments, when the functions of the multiple first semiconductor chips 101 are the same, the internal structures of the multiple first semiconductor chips 101 are the same. In another embodiment, when the functions of the multiple first semiconductor chips 101 are the same, the internal structures of the multiple first semiconductor chips 101 are different.
[0057] According to different functions, the first semiconductor chip 101 may include a logic chip and / or a memory chip. In some embodiments, the logic chip may include, but is not limited to, a gate array, a cell substrate array, an embedded array, a structured application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip, or a complementary metal-oxide-semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include, but is not limited to, a dynamic random access memory (DRAM), a static random-access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase-change memory (PRAM), a resistive random access memory (RRAM), or a non-volatile memory chip (such as a flash memory).
[0058] In some embodiments, all the first semiconductor chips 101 in the chip stack structure 100 have the same function. In a specific example, all the first semiconductor chips 101 in the chip stack structure 100 are memory chips. In another specific example, all the first semiconductor chips 101 in the chip stack structure 100 may also be logic chips.
[0059] In other embodiments, the functions of some of the first semiconductor chips 101 in the chip stack structure 100 are different from those of the other first semiconductor chips 101. In a specific example, some of the first semiconductor chips 101 in the chip stack structure 100 are logic chips, and some of the first semiconductor chips 101 are memory chips.
[0060] Reference Figure 2 , a carrier board 303 is provided, and one side surface of the chip stack structure 100 is mounted on the upper surface of the carrier board 303, so that the side surface 11 of the chip stack structure 100 exposing the side pads 103 is away from the upper surface of the carrier board 303.
[0061] In some embodiments, one side of the chip stack structure 100 is mounted on the upper surface of the carrier 303 through a temporary bonding layer 304. The temporary bonding layer 304 can be an adhesive layer.
[0062] In some embodiments, mounting one side of the chip stack structure 100 on the upper surface of the carrier 303 includes: mounting one side of one chip stack structure 100 on the upper surface of the carrier 303.
[0063] In some embodiments, mounting one side of the chip stack structure 100 on the upper surface of the carrier 303 includes: mounting one side of a plurality of chip stack structures 100 on the upper surface of the carrier 303. By subsequent processes, the sides of the plurality of chip stack structures 100 having side pads can be planarized simultaneously, so that the side pads on the corresponding sides of the plurality of chip stack structures 100 are coplanar, thereby improving the processing efficiency. In some embodiments, one side of a plurality of chip stack structures 100 is mounted on the upper surface of the carrier 303, and the plurality of chip stack structures 100 are arranged in an array, which is convenient for subsequent processes.
[0064] Reference Figure 3 , a coating layer 105 covering the chip stack structure 100 is formed.
[0065] In some embodiments, the material of the coating layer 105 includes resin. Specifically, the material of the coating layer 105 can be an epoxy resin, a polyimide resin, a benzocyclobutene resin, or a polybenzoxazole resin with or without fillers; or it can also be a polybutylene terephthalate, a polycarbonate, a polyethylene terephthalate, a polyethylene, a polypropylene, a polyolefin, a polyurethane, a polyolefin, a polyethersulfone, a polyamide, a polyurethane, an ethylene-vinyl acetate copolymer, or a polyvinyl alcohol with fillers. The filler can be an inorganic filler or an organic filler. The process for forming the coating layer 105 includes a compression molding process or a transfer molding process.
[0066] Reference Figure 4 , a planarization process is used to remove part of the coating layer 105, part of the side surface of the chip stack structure 100 away from the upper surface of the carrier 303, and part of the side pads 103, so that the side pads 103 of different first semiconductor chips 101 exposed on the side surface 11 of the chip stack structure 100 away from the upper surface of the carrier 303 are coplanar.
[0067] The coplanarity of the side pads 103 means that the surfaces of several side pads 103 exposed in the chip stack structure 100 are on the same plane. Therefore, when welding protrusions are formed on the subsequent side pads 103, there will be no problem of uneven height for the welding protrusions. When connecting the chip stack structure 100 after the planarization process to other structures (such as a substrate), it can avoid the occurrence of poor welding problems (such as virtual soldering, de-soldering or bridging) when the welding protrusions on the side pads of the side 11 of the chip stack structure 100 are welded to other structures (such as the first pads of the substrate), thereby improving the performance of the package structure.
[0068] In some embodiments, the planarization process is a chemical mechanical polishing process.
[0069] Reference Figure 5 , after the planarization process, welding protrusions 106 are formed that are electrically connected to the side pads 103.
[0070] The welding protrusions 106 are directly formed on the surface of the side pads 103.
[0071] In some embodiments, the welding protrusions 106 are solder balls. In other embodiments, the welding protrusions 106 may include metal posts (or metal bumps) and solder caps located at the tops of the metal posts. The material of the metal posts 106 is one or several of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, silver, and the material of the solder balls or solder caps is one or several of tin, tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony.
[0072] Reference Figure 6 , the carrier plate 303 is removed (reference Figure 5 ).
[0073] In some embodiments, when there is only one chip stack structure 100 on the carrier plate 303, the carrier plate 303 is directly removed.
[0074] In other embodiments, continuing to refer to reference Figure 5 and Figure 6 , when there are multiple chip stack structures 100 on the carrier plate 303, after forming the welding protrusions 106 that are electrically connected to the side pads 103, it further includes: dividing the coating layer 105 to form multiple discrete chip stack structures 100 with the coating layer 105; after division, the carrier plate 303 is removed.
[0075] Reference Figure 7, a substrate 201 is provided, and the upper surface of the substrate 201 has a plurality of discrete first pads (not shown in the figure); the side surface of the exposed side pads 103 of the chip stack structure 100 is mounted on the upper surface of the substrate 201, so that the welding protrusions 106 are welded to the corresponding first pads.
[0076] In some embodiments, the substrate 201 may include an opposite upper surface and a lower surface. The upper surface of the substrate 201 has a plurality of discrete first pads (not shown in the figure), and the lower surface of the substrate 101 has a plurality of discrete second pads (not shown in the figure). The substrate 201 has a first circuit (not shown in the figure). Part of the first circuit can be used for the electrical connection between the first pads on the upper surface of the substrate 201 and the corresponding second pads on the lower surface of the substrate 201. Part of the first circuit can also be used for the electrical connection between some of the first pads on the upper surface of the substrate 201. Part of the first circuit can also be used for the electrical connection between some of the second pads on the lower surface of the substrate 201. Some of the first pads on the upper surface of the substrate 201 are welded to the corresponding side pads of the chip stack structure 100. External solder protrusions (not shown in the figure) can be formed on the second pads on the lower surface of the substrate 201, and the external solder protrusions are used to connect to other devices, other substrates or packaging structures. The materials of the first pads, the second pads and the first circuit are metals, specifically one or several of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external solder protrusion is tin or a tin alloy, and the tin alloy is one or several of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony.
[0077] In some embodiments, the substrate 201 can be one of a resin substrate, a silicon substrate, a printed circuit board (PCB), a redistribution layer (RDL), a ceramic substrate, a glass substrate or a flexible printed circuit (FPC). In some embodiments, the substrate 201 can be a single-layer board or a multi-layer board. In some embodiments, the substrate 201 can be used as an interposer (or adapter board).
[0078] In some embodiments, it further includes: mounting a second semiconductor chip 120 on the upper surface of a substrate 201 on one side of the chip stack structure 100, welding the second semiconductor chip 120 to corresponding first pads on the upper surface of the substrate 201. In a specific embodiment, the second semiconductor chip 120 is flip-chip mounted on the upper surface of the substrate 201, and welding bumps 121 on the second semiconductor chip 120 are welded to corresponding first pads on the upper surface of the substrate 201. In some embodiments, the second semiconductor chip 120 can be electrically connected to the chip stack structure 100 through a first circuit in the substrate 201, and communication and / or data transfer can be performed between the second semiconductor chip 120 and the chip stack structure 100. In some embodiments, the second semiconductor chip 120 includes a CPU chip or a GPU chip.
[0079] In some embodiments, a first underfill layer 107 is further filled between the chip stack structure 100 and the upper surface of the substrate 201. A second underfill layer 122 is further filled between the second semiconductor chip 120 and the upper surface of the substrate 201.
[0080] Some other embodiments of the present application further provide a method for forming a packaging structure. The main difference between these embodiments and the foregoing embodiments is that the welding bumps are electrically connected to corresponding side pads in the chip stack structure through a redistribution layer. Through the redistribution layer, the external terminals on the side of the chip stack structure can be redistributed, thereby increasing the density of the external terminals on the side of the chip stack structure. Figures 8 - 11 It is a schematic structural diagram of the formation process of the packaging structure provided in some other embodiments of the present application.
[0081] Reference Figure 8 , a planarization process is used to remove part of the coating layer 105, part of the side surface of the chip stack structure 100 away from the upper surface of the carrier plate 303, and part of the side pads 103, so that the side pads 103 of different first semiconductor chips 102 exposed on the side surface of the chip stack structure 100 away from the upper surface of the carrier plate 303 are coplanar. Then, a redistribution layer is formed on the surface of the planarized coating layer 105, and the redistribution layer is electrically connected to the welding bumps 103. In a specific example, the redistribution layer includes a passivation layer 109 and a plurality of discrete redistribution metal layers 110 located in the passivation layer 109, and the redistribution metal layers 110 are electrically connected to corresponding side pads 103; reference Figure 9 , welding bumps 106 are formed on the surface of the redistribution layer, and the welding bumps 106 are electrically connected to the redistribution layer. In a specific example, the welding bumps 106 are electrically connected to corresponding redistribution metal layers 110.
[0082] The passivation layer 109 includes an organic material or an inorganic material. The organic material includes a resin material or a polymer, such as an epoxy resin, a polyimide resin, a benzocyclobutene resin, or a polybenzoxazole resin. The inorganic material includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The material of the redistribution metal layer 110 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and WSi.
[0083] Reference Figure 10 , divide the wiring layer and the coating layer 105 to form a plurality of discrete chip stack structures 100 each having a wiring layer and a coating layer 105; remove the carrier board 303; Reference Figure 11 , provide a substrate 201, the upper surface of the substrate 201 having a plurality of discrete first pads (not shown in the figure); mount the side of the chip stack structure 100 having the wiring layer and the coating layer 105 on the upper surface of the substrate 201 such that the solder bumps 106 are soldered to the corresponding first pads.
[0084] It should be noted that in other embodiments, when two or more sides of the chip stack structure 100 expose the side pads 103 corresponding to the corresponding sides of the first semiconductor chip 101, each side of the chip stack structure 100 having side pads can sequentially adopt the foregoing steps (mount one side of the chip stack structure on the upper surface of the carrier board; form a coating layer covering the chip stack structure; use a planarization process to remove part of the coating layer, part of the side of the chip stack structure away from the upper surface of the carrier board, and part of the side pads, so that the side pads of different first semiconductor chips exposed on the side of the chip stack structure away from the upper surface of the carrier board are coplanar; after the planarization process, form solder bumps electrically connected to the side pads), so that the side pads on the corresponding sides are coplanar, and form solder bumps connected to the side pads on the corresponding sides after the planarization process.
[0085] Some embodiments of the present application also provide a packaging structure. Reference Figure 11 , including: A substrate 201, the upper surface of the substrate 201 having a plurality of discrete first pads (not shown in the figure); A chip stack structure 100, located on the upper surface of the substrate 201, the chip stack structure 100 including a plurality of first semiconductor chips 101 stacked in sequence along a direction parallel to the upper surface of the substrate 201, and a side 11 of the chip stack structure 100 close to and parallel to the upper surface of the substrate 201 exposing the side pads 103 corresponding to the corresponding sides of the plurality of first semiconductor chips 101; The encapsulation layer 105 encapsulates the chip stack structure 100, and the encapsulation layer 105 exposes the side pads 103; The redistribution layers (109, 110) are located on a surface of the encapsulation layer 105 and the chip stack structure 100 that is close to and parallel to the upper surface of the substrate 201, and the redistribution layers are electrically connected to the side pads 103; The solder bumps 106 are located between the redistribution layers and the upper surface of the substrate 201, and the solder bumps 106 weld the redistribution layers to the corresponding first pads together.
[0086] In some embodiments, the side pads 103 and the circuit layers in the first semiconductor chip 101 are of an integral structure.
[0087] In some embodiments, each of the first semiconductor chips 101 in the chip stack structure 100 includes an active surface and a back surface that are opposite and perpendicular to the upper surface of the substrate 201, and four side surfaces located on the active surface and the back surface. A side surface of the first semiconductor chip 101 that is close to and parallel to the upper surface of the substrate 201 has the side pads 103 and exposes the surface of the side pads 103. The active surfaces and the back surfaces of the upper and lower first semiconductor chips 101 in the chip stack structure 100 are arranged opposite to each other.
[0088] In some embodiments, there is no electrical connection between the active surface or the back surface of the upper first semiconductor chip 101 and the adjacent lower semiconductor chip. There is an adhesive layer or a bonding layer 102 between the active surface or the back surface of the upper first semiconductor chip 101 and the corresponding back surface or active surface of the adjacent lower semiconductor chip. Multiple first semiconductor chips 101 can be electrically connected through the redistribution layers (109, 110) on the side pads 103.
[0089] In some embodiments, there is an electrical connection between the upper first semiconductor chip 101 and the adjacent lower semiconductor chip; the active surface of the first semiconductor chip 101 has an external pad, the first semiconductor chip 101 has a via connection structure electrically connected to the external pad, and one end surface of the via connection structure is exposed on the back surface of the first semiconductor chip 101. The external pad on the active surface or the via connection structure on the back surface of the upper first semiconductor chip 101 is welded to the corresponding via connection structure on the back surface or the external pad on the active surface of the adjacent lower semiconductor chip, and an isolation layer is filled between the active surface or the back surface of the upper first semiconductor chip 101 and the corresponding back surface or active surface of the adjacent lower semiconductor chip.
[0090] In some embodiments, the redistribution layer includes a passivation layer 109 and a plurality of discrete redistribution metal layers 110 located in the passivation layer 109. The redistribution metal layers 110 are electrically connected to corresponding side pads 103 and solder bumps 106.
[0091] In some embodiments, it further includes: a second semiconductor chip 120 mounted on the upper surface of a substrate 201 on one side of the chip stack structure 100. The second semiconductor chip 120 is soldered to corresponding first pads.
[0092] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0093] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0094] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A method for forming a packaging structure, characterized in that Including: Providing a chip stack structure, the chip stack structure including a plurality of first semiconductor chips stacked in sequence, the chip stack structure having four side faces, a side face of the chip stack structure exposing side pads on corresponding side faces of the plurality of first semiconductor chips, and the side pads having non-coplanarity defects; Providing a carrier board, mounting one side face of the chip stack structure on an upper surface of the carrier board, such that the side face of the chip stack structure exposing the side pads is away from the upper surface of the carrier board; Forming a coating layer covering the chip stack structure; Using a planarization process to remove part of the coating layer, part of the side faces of the chip stack structure away from the upper surface of the carrier board, and part of the side pads, such that the side pads of different first semiconductor chips exposed on the side faces of the chip stack structure away from the upper surface of the carrier board are coplanar; After the planarization process, forming solder bumps electrically connected to the side pads; Removing the carrier board; Providing a substrate, the upper surface of the substrate having a plurality of discrete first pads; Mounting the side face of the chip stack structure exposing the side pads on the upper surface of the substrate, such that the solder bumps are soldered to corresponding first pads.
2. The method for forming the encapsulation structure according to claim 1, wherein Each of the first semiconductor chips in the chip stack structure includes an opposite active face and a back face, and four side faces located on the active face and the back face. One of the side faces of the first semiconductor chip has the side pad and exposes the surface of the side pad. The active faces and the back faces of the upper and lower first semiconductor chips in the chip stack structure are oppositely arranged.
3. The method for forming the encapsulation structure according to claim 2, wherein The active face of the upper first semiconductor chip in the chip stack structure is oppositely arranged with the back face of the adjacent lower first semiconductor chip.
4. The method for forming the encapsulation structure according to claim 2, wherein The back face of the upper first semiconductor chip in the chip stack structure is oppositely arranged with the active face of the adjacent lower first semiconductor chip.
5. The method for forming the encapsulation structure according to claim 3 or 4, characterized in that There is no direct electrical connection between the upper first semiconductor chip and the adjacent lower semiconductor chip.
6. The method for forming the encapsulation structure according to claim 5, wherein There is an adhesive layer or a bonding layer between the active face or the back face of the upper first semiconductor chip and the corresponding back face or active face of the adjacent lower semiconductor chip.
7. The method for forming the encapsulation structure according to claim 3 or 4, characterized in that, There is a direct electrical connection between the upper first semiconductor chip and the adjacent lower semiconductor chip.
8. The method for forming the encapsulation structure according to claim 7, wherein The active face of the first semiconductor chip has an external pad, the first semiconductor chip has a via connection structure electrically connected to the external pad, and one end surface of the via connection structure is exposed on the back face of the first semiconductor chip. The external pad on the active face or the via connection structure on the back face of the upper first semiconductor chip is soldered to the corresponding via connection structure on the back face or the external pad on the active face of the adjacent lower semiconductor chip.
9. The method for forming the encapsulation structure according to claim 1, characterized in that The planarization process is a chemical mechanical polishing process.
10. The method for forming the encapsulation structure according to claim 1 or 9, characterized in that, The material of the coating layer includes resin.
11. The method for forming the encapsulation structure according to claim 1, wherein Mounting one side face of the chip stack structure on the upper surface of the carrier board through a temporary bonding layer.
12. The method for forming the encapsulation structure according to claim 11, wherein Mounting one side face of the chip stack structure on the upper surface of the carrier board includes: mounting one side face of one chip stack structure on the upper surface of the carrier board.
13. The method for forming the encapsulation structure according to claim 11, wherein, Mounting one side surface of the chip stack structure on the upper surface of the carrier plate includes: mounting one side surfaces of a plurality of the chip stack structures on the upper surface of the carrier plate.
14. The method for forming the encapsulation structure according to claim 13, wherein Mounting one side surfaces of a plurality of the chip stack structures on the upper surface of the carrier plate, and the plurality of the chip stack structures are arranged in an array.
15. The method for forming the encapsulation structure according to claim 14, wherein, After forming welding bumps electrically connected to the side pads, it further includes: dividing the coating layer to form a plurality of discrete chip stack structures each having a coating layer.
16. The method for forming the encapsulation structure according to claim 1, wherein Forming welding bumps electrically connected to the side pads includes: forming welding bumps directly electrically connected to the side pads.
17. The method for forming the encapsulation structure according to claim 1, wherein Forming welding bumps electrically connected to the side pads includes: after the planarization process, forming a redistribution layer on the surface of the planarized coating layer, the redistribution layer being electrically connected to the side pads; forming welding bumps on the surface of the redistribution layer, the welding bumps being electrically connected to the redistribution layer.
18. The method for forming the encapsulation structure according to claim 17, wherein, The redistribution layer includes a passivation layer and a plurality of discrete redistribution metal layers located in the passivation layer, and the redistribution metal layers are electrically connected to corresponding side pads and welding bumps.
19. The method for forming the encapsulation structure according to claim 1, wherein The side pads are formed synchronously with the wiring layer of the first semiconductor chip.
20. The method for forming the encapsulation structure according to claim 19, wherein The side pads are formed synchronously with the wiring layer of the first semiconductor chip includes: when forming the wiring layer of the active surface of the first semiconductor chip, forming lines synchronously with the corresponding scribe lane sides of the chip, and after the chip is diced, the lines are exposed on the corresponding sides of the first semiconductor chip to form side pads.
21. The method for forming the encapsulation structure according to claim 1, wherein, The side pads having non-coplanar defects includes: some of the side pads on the sides of different first semiconductor chips in the chip stack structure are non-coplanar, and some of the side pads on the side of the same first semiconductor chip are non-coplanar.
22. An encapsulation structure, characterized in that, Includes: A substrate, the upper surface of the substrate having a plurality of discrete first pads; A chip stack structure located on the upper surface of the substrate, the chip stack structure including a plurality of first semiconductor chips stacked in sequence along a direction parallel to the upper surface of the substrate, and a side pad on a side of each of the first semiconductor chips close to and parallel to the upper surface of the substrate is exposed; A coating layer covering the chip stack structure, and the coating layer exposes the side pads; A redistribution layer located on a side of the coating layer and the chip stack structure close to and parallel to the upper surface of the substrate, the redistribution layer being electrically connected to the side pads; Welding bumps located between the redistribution layer and the upper surface of the substrate, the welding bumps welding the redistribution layer to the corresponding first pads together.
23. The encapsulation structure according to claim 22, wherein, Each of the first semiconductor chips in the chip stack structure includes an active surface and a back surface opposite to and perpendicular to the upper surface of the substrate, and four side surfaces located on the active surface and the back surface. A side pad is provided on a side of the first semiconductor chip close to and parallel to the upper surface of the substrate and the surface of the side pad is exposed. The active surfaces and the back surfaces of the upper and lower first semiconductor chips in the chip stack structure are arranged oppositely.
24. The encapsulation structure according to claim 23, wherein There is no direct electrical connection between the first semiconductor chip in the upper layer and the adjacent semiconductor chip in the lower layer, and there is an adhesive layer or a bonding layer between the active surface or the back surface of the first semiconductor chip in the upper layer and the corresponding back surface or active surface of the adjacent semiconductor chip in the lower layer.
25. The encapsulation structure according to claim 23, wherein, There is a direct electrical connection between the first semiconductor chip in the upper layer and the adjacent semiconductor chip in the lower layer; the active surface of the first semiconductor chip has external pads, and there is a via connection structure in the first semiconductor chip that is electrically connected to the external pads. One end surface of the via connection structure is exposed on the back surface of the first semiconductor chip, and the external pads on the active surface or the via connection structure on the back surface of the first semiconductor chip in the upper layer are soldered to the corresponding via connection structure on the back surface or the external pads on the active surface of the adjacent semiconductor chip in the lower layer.
26. The encapsulation structure according to claim 22, wherein, The side pads and the wiring layer of the first semiconductor chip are an integral structure.
27. The encapsulation structure according to claim 22, characterized in that, The redistribution layer includes a passivation layer and several discrete redistribution metal layers located in the passivation layer, and the redistribution metal layers are electrically connected to the corresponding side pads and solder bumps.
28. The encapsulation structure according to claim 22, wherein It further includes: A second semiconductor chip mounted on the upper surface of a substrate on one side of the chip stack structure, and the second semiconductor chip is soldered to the corresponding first pads.