Method for preparing multi-chip connection structure

Abstract

The present invention belongs to the field of chip technology, and specifically relates to a method for preparing a multi-chip connection structure. Steps: coating a release layer and an adhesive layer on a substrate; copper pillar bumps are provided on a chip, the chip is temporarily bonded to the adhesive layer, and a control portion of the copper pillar bumps is embedded in the adhesive layer; a plastic encapsulation layer is formed on the adhesive layer, the plastic encapsulation layer wraps the chip and the remaining copper pillar bumps, and the chip and the plastic encapsulation layer together constitute module one; the adhesive layer is peeled off, and the copper pillar bumps embedded in the adhesive layer are exposed to the outside, and a non-metallic dielectric material is deposited on the side of module one with the copper pillar bumps to modify the copper pillar bumps, so that both sides of the copper pillar bumps are no longer exposed, and the remaining exposed surface of the copper pillar bumps is copper-copper bonded to a TSV intermediary layer; removing excess silicon substrate of the TSV intermediary layer to obtain module two, constructing a complete RDL layer at the bottom of module two, and making bumps on the surface of the complete RDL layer. The present invention improves the welding reliability, signal integrity, and heat dissipation performance of preparing a multi-chip connection structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of chips, and in particular relates to a method for preparing a multi-chip connection structure. Background Art

[0002] Existing technology typically involves electroplating uPads (microbumps) on a TSV interposer (TSV interposer), such as microbumps made of Cu / Ni / Au alloy solder or Cu / Ni / SnAg alloy solder. The chip is then soldered to the TSV interposer using a flip chip method and then plastic-encapsulated.

[0003] The technical problems of such preparation are as follows:

[0004] Soldering reliability: The reliability problem of micro-bumps is becoming increasingly prominent, and defects such as cold solder joints and cracks are prone to occur, affecting the long-term stability of the chip.

[0005] Signal integrity: As signal frequencies increase, parasitic capacitance and inductance of microbumps and solder can affect signal integrity and limit data transfer rates.

[0006] Thermal management: Microbumps and solder have high thermal resistance, which will affect the heat dissipation performance of the chip. Summary of the Invention

[0007] In view of the shortcomings of the prior art, an object of the present invention is to provide a method for preparing a multi-chip connection structure.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides the following technical solutions:

[0009] A method for preparing a multi-chip connection structure comprises the following steps:

[0010] coating a release layer on the substrate, and coating an adhesive layer on the release layer;

[0011] The chip includes SOC Die and HBM Die. There are copper pillar bumps on the chip. The chip is temporarily bonded to the adhesive layer, and the copper pillar bumps of the control part are embedded in the adhesive layer.

[0012] forming a plastic encapsulation layer on the adhesive layer, the plastic encapsulation layer encapsulating the chip and the remaining copper pillar bumps, the chip and the plastic encapsulation layer together constituting module one;

[0013] The adhesive layer is peeled off, and the copper pillar bumps embedded in the adhesive layer are exposed. A non-metallic dielectric material is deposited on the side of the module with the copper pillar bumps to modify the copper pillar bumps so that both sides of the copper pillar bumps are no longer exposed. The remaining exposed surface of the copper pillar bumps is then copper-copper bonded (Cu-Cu bonded) to the TSV interposer.

[0014] The excess silicon substrate of the TSV interposer is removed to obtain module 2, a complete RDL layer is constructed at the bottom of module 2, and bumps are made on the surface of the complete RDL layer.

[0015] It should be noted that in the above technical solution, 1) during plastic encapsulation, the plastic encapsulation layer only covers a portion of the copper pillar bumps on the chip, with the remaining portion embedded in the adhesive layer. This protects the cylindrical surface of the copper pillar bumps from moisture erosion and metal migration. 2) After stripping the adhesive layer, a non-metallic dielectric material is deposited to modify the copper pillar bumps, protecting their cylindrical surfaces. 3) The remaining exposed surface of the copper pillar bumps is copper-to-copper bonded to the TSV interposer, which can also be considered as forming a copper-to-copper bond between module one and module two.

[0016] The copper-copper bonding technology employed in this invention, compared to the micro-bump soldering method used in the traditional CoWoS-S process, avoids the problems of uneven heating, sunken or raised welds, and other issues associated with solder or solder paste reflow soldering, thereby improving the flatness of the bonding interface and the reliability of the electrical connection. The preparation method of this invention also enhances soldering reliability, signal integrity, and heat dissipation performance.

[0017] In one embodiment, the temporary bonding step includes: using a bonding machine to symmetrically arrange every two HBM dies on both sides of a SOC die, bonding the copper pillar bumps of the HBM die and the SOC die to the adhesive layer with the surface facing downward, and controlling the depth of the copper pillar bumps embedded in the adhesive layer to be 2-3μm; wherein the total number of HBM dies is ≥2, and the total number of SOC dies is ≥1.

[0018] In one embodiment, the metal pads of the SOC Die are provided with copper pillar bumps, the height of the copper pillar bumps is 4-8 μm, and the width of the copper pillar bumps is 5-25 μm; the metal pads of the HBM Die are provided with copper pillar bumps, the height of the copper pillar bumps is 4-8 μm, and the width of the copper pillar bumps is 5-25 μm.

[0019] In one embodiment, a method for preparing a TSV interposer includes the following steps:

[0020] Anisotropic etching is used to form horizontal and vertical deep holes on a silicon substrate, and the vertical deep holes are connected by horizontal deep holes.

[0021] An insulating layer is deposited in the deep hole of the silicon substrate, a barrier layer is deposited on the insulating layer, and then a seed layer is deposited or not deposited, and a metal material is electroplated in the deep hole to remove excess metal material on the surface of the silicon substrate; then the RDL process is used on the surface of the silicon substrate, specifically, insulating material is deposited on the surface of the silicon substrate, and then photoresist is coated on the insulating material, exposed and developed to form an RDL circuit pattern, and metal copper is sputter-deposited and / or electroplated in the RDL circuit pattern to form an interconnection line to form an intermediate connection layer, and the photoresist is stripped off to obtain a TSV interposer.

[0022] Furthermore, when the metal material is electroplated and filled in the deep hole, the metal material includes copper; when the remaining exposed surface of the copper pillar bump is copper-copper bonded to the TSV interposer, the exposed surface is copper-copper bonded to the intermediate connection layer.

[0023] In one embodiment, removing excess silicon substrate from the TSV interposer includes the following steps:

[0024] Use a grinder to reduce the excess silicon substrate thickness d1 to 3-10μm, then use an etching process to etch the bottom of the silicon substrate to expose a portion of the deep hole wrapped by the silicon substrate. The exposed thickness of the deep hole is 1-5μm. Then use a PECVD process to deposit non-metallic dielectric material on both sides of the exposed deep hole, and then use a CMP process to flatten the bottom of the silicon substrate.

[0025] Optionally, the non-metallic dielectric material includes at least one of silicon nitride and silicon dioxide.

[0026] In one embodiment, building a complete RDL layer at the bottom of module 2 includes the following steps:

[0027] A passivation layer is formed on the bottom of module 2. A mask is used to cover the passivation layer, and the passivation layer outside the mask is exposed and dissolved, leaving a designed pattern on module 2. Titanium and copper layers are sputtered on the designed pattern to form a PVD layer. The PVD layer and the remaining passivation layer constitute the first RDL layer.

[0028] A photoresist layer is formed on the first RDL layer, a mask is used to cover the photoresist layer, and the photoresist layer outside the mask is exposed to light. The photoresist layer is dissolved, leaving a designed pattern on the first RDL layer. Copper is electroplated on the designed pattern to form a conductive circuit;

[0029] Remove the remaining photoresist, retain the conductive circuit formed by electroplating, and etch away the unnecessary conductive circuits, leaving only the conductive circuits connected to the PVD layer. After etching, vacant gaps are generated, and a protective layer is formed in the gaps. The conductive circuits and the protective layer constitute the second RDL layer;

[0030] The first RDL layer and the second RDL layer together constitute a complete RDL layer.

[0031] In one embodiment, the parameters of temporary bonding include: an initial contact pressure of 0.5-1.0 MPa, in which the copper pillar bump contacts the adhesive layer but is not embedded; an embedding stage pressure of 2.5-3.5 MPa, in which a controlled portion of the copper pillar bump is embedded in the adhesive layer; and a holding time of 8-15 seconds.

[0032] In one embodiment, the plastic encapsulation uses a molding compound, and the preparation of the molding compound includes the following steps:

[0033] Bisphenol F epoxy resin and reactive diluent are mixed evenly to obtain a resin mixture.

[0034] Large-sized silica, small-sized silica and nanoparticles are uniformly mixed to obtain a mixed powder;

[0035] Slowly add the resin mixture into the mixed powder and stir to obtain a mixture;

[0036] Add defoaming agent and leveling agent to the mixture, stir to obtain a mixed solution;

[0037] Slowly add the curing agent into the mixed solution, stir, and vacuum degas to obtain a molding compound;

[0038] The particle size of the large-sized silicon dioxide is 10-20 μm, the particle size of the small-sized silicon dioxide is 0.1-0.5 μm, and the active diluent includes siloxane oligomer.

[0039] Furthermore, based on parts by weight, the amount of large-size silica added is 50-70 parts, the amount of small-size silica added is 10-15 parts, and the amount of nanoparticles added is 1-10 parts.

[0040] Optionally, the particle size of the nanoparticles is 50-100 nm. The nanoparticles include α-phase nano silicon nitride particles.

[0041] The beneficial effects of the present invention are:

[0042] The structure of the present invention has a higher transmission rate: compared with traditional micro-bump welding, Cu-Cu bonding has lower resistance and inductance, and can achieve a higher data transmission rate.

[0043] The structure of the present invention has a higher I / O density: Cu-Cu bonding can achieve a smaller bonding pitch, thereby supporting a higher I / O density.

[0044] The structure of the present invention has better reliability: the Cu-Cu bonding has higher bonding strength and better thermal cycle performance, thereby improving the long-term reliability of the chip.

[0045] The structure of the present invention has better thermal performance: Cu-Cu bonding has lower thermal resistance, which helps to dissipate heat from the chip.

[0046] Specifically, the exposed surface of the chip copper pillar bump is directly bonded to the middle connection layer of the TSV interposer. The TSV interposer does not need to make additional copper pillars or micro-bumps, which simplifies the process flow, reduces manufacturing costs, and improves bonding accuracy and interconnection density.

[0047] Furthermore, during the plastic encapsulation step, the molding compound wraps the exposed copper pillar bumps, which not only serves as a protective material to prevent copper metal migration, but also protects the sides of the copper pillar bumps from oxidation, further enhancing the long-term reliability of the packaging structure.

[0048] After stripping off the adhesive layer, silicon nitride and silicon dioxide are deposited on the exposed surface of the copper pillar bump, forming a three-layer protective structure (plastic sealing layer, silicon nitride, and silicon dioxide) on both sides of the copper pillar bump, effectively protecting the side surfaces of the copper pillar bump to prevent oxidation and metal migration, while retaining the exposed surface of the copper pillar bump to facilitate subsequent bonding.

[0049] In the RDL process, multi-layer redistribution (first RDL layer and second RDL layer) enables efficient reconstruction and distribution of lines, significantly improving the flexibility of signal transmission and integration density.

[0050] Furthermore, in the process of preparing module one, the present invention also provides chip bonding parameters to ensure that the depth of the copper pillar bump embedded in the adhesive layer is precisely controlled at 2-3μm, avoiding the offset or uneven embedding of the copper pillar bump due to instantaneous high voltage, thereby improving the position stability and structural reliability of the chip during the plastic packaging process.

[0051] The present invention also provides a molding compound formula to further improve the quality of the plastic encapsulation layer. The molding compound utilizes a low-viscosity, highly reactive bisphenol F epoxy resin, combined with a reactive diluent (siloxane oligomer), which reduces the viscosity of the resin system, improves fluidity, effectively fills small gaps, and reduces bubble generation. A high-efficiency defoamer and leveling agent are added. The defoamer quickly eliminates bubbles during the mixing and potting process, while the leveling agent improves fluidity and reduces surface defects, thereby ensuring that there are no bubble defects within the plastic encapsulation layer and improving the mechanical strength and electrical performance of the packaging structure. The use of a multi-level composite filler (large-sized silica, small-sized silica, and nano-silicon nitride particles) optimizes the packing density of the filler, reduces the thermal expansion coefficient, enhances the toughness and impact resistance of the molding compound, and further improves the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is a schematic structural diagram of the step of preparing a module in Example 1 of the present invention;

[0054] Figure 2 This is a schematic structural diagram of the step of preparing a module in Example 1 of the present invention;

[0055] Figure 3 This is a schematic structural diagram of the step of preparing a module in Example 1 of the present invention;

[0056] Figure 4 Schematic diagram of the structure of the stripping step in Example 1 of the present invention;

[0057] Figure 5 Schematic diagram of the structure of the hybrid bonding step in Example 1 of the present invention;

[0058] Figure 6 Schematic diagram of the structure of the bonding hole exposure process steps in Example 1 of the present invention;

[0059] Figure 7 Schematic diagram of the RDL process steps in Example 1 of the present invention;

[0060] Figure 8 Schematic diagram of the RDL process steps in Example 1 of the present invention;

[0061] Figure 9 Schematic diagram of the structure of the bump process step in Example 1 of the present invention;

[0062] The markings in the figure are: 1. Substrate; 2. Release layer; 3. Adhesive layer; 4. SOC Die; 5. HBM Die; 6. Plastic encapsulation layer; 7. Module 1; 8. Exposed surface; 9. TSV interposer; 10. Deep hole; 11. Intermediate connection layer; 12. Module 2; 13. PVD layer; 14. First RDL layer; 15. Conductive line; 16. Second RDL layer; 17. Complete RDL layer; 18. Bump.

[0063] Figures 1-9 Together they constitute a flow chart for preparing a multi-chip connection structure. DETAILED DESCRIPTION

[0064] The following is a detailed description of the method for fabricating a multi-chip connection structure according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0065] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean internal communication between two components; it can mean a wireless connection or a wired connection. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0066] Unless otherwise specified, the materials used in the examples can be easily obtained from commercial companies.

[0067] In the following, SOC (System on Chip) Die (bare chip) and HBM (High Bandwidth Memory) Die (bare chip) are named directly in English without repeating the Chinese annotations. The chips (SOC Die and HBM Die) used in the present invention can be purchased conventionally, and their specific mechanisms are also clearly known to those skilled in the art, so they are not described in detail.

[0068] Preparation method of multi-chip connection structure, refer to Figures 1-9 , the specific steps are as follows:

[0069] 1. Preparation module 1:

[0070] Make release layer 2 and adhesive layer 3: refer to Figure 1 A glass substrate is selected as substrate 1. A layer of release material is first coated on substrate 1 to form release layer 2. A layer of adhesive material is then coated on release layer 2 to form adhesive layer 3. The release material includes, but is not limited to, photosensitive materials and thermal release tapes. Adhesive materials include, but are not limited to, temporary chip bonding materials and temporary adhesive films.

[0071] Select a chip: The chip includes SOC Die 4 and HBM Die 5. SOC Die 4 has copper pillar bumps on its metal pads. The height of the copper pillar bumps is 4-8μm, and the width of the copper pillar bumps is 5-25μm. The copper pillar bumps on SOC Die 4 are electrically connected to the circuits within SOC Die 4.

[0072] HBM Die 5 also has copper pillar bumps on its metal pads. These are 4-8μm tall and 5-25μm wide. To ensure high production yield, HBM Die 5 must maintain the same height and width as SOC Die 4. The copper pillar bumps on HBM Die 5 are electrically connected to the circuitry within HBM Die 5.

[0073] Die bond: See Figure 2 Using a die bonding process, temporarily bond HBM Die 5 and SOC Die 4 to adhesive layer 3. The specific quantity and layout can be: using a bonding machine, symmetrically place two HBM Dies 5 on either side of a SOC Die 4, with the copper pillar bumps of the HBM Die 5 and SOC Die 4 facing downward and bonded to adhesive layer 3. The copper pillar bumps are embedded in the adhesive layer 3 to a depth of 2-3μm to facilitate subsequent plastic encapsulation. The total number of HBM Dies 5 must be ≥ 2, and the total number of SOC Dies 4 must be ≥ 1.

[0074] Plastic sealing: refer to Figure 3 Molding compound is used to encapsulate HBM Die 5 and SOC Die 4, forming a plastic encapsulation layer 6 on the adhesive layer 3. Plastic encapsulation layer 6 contains HBM Die 5 and SOC Die 4. HBM Die 5, SOC Die 4, and plastic encapsulation layer 6 together constitute module 1 7. During encapsulation, the molding compound also covers the exposed copper pillar bumps not embedded in the adhesive layer 3. The molding compound acts as a protective material for the copper pillar bumps, preventing copper metal migration and protecting the sides of the copper pillar bumps from oxidation.

[0075] Grinding: This step is optional. Using a grinding process, a precision grinder is used to grind the surface of the plastic layer 6 to make it smooth and flat.

[0076] 2. Peeling: Refer to Figure 4 , peel off the adhesive layer 3 and use a debonding process to remove the adhesive layer 3 attached to module 1 7. This process utilizes the adhesive material's characteristics, such as thermal sliding removal, laser depolymerization, or solvent-assisted stripping, and debonds according to the adhesive material's instructions. After removing the adhesive layer 3, the corresponding release layer 2 and substrate 1 are also removed. After debonding the adhesive layer 3, clean the surface of module 1 7 to remove any residue from the debonding process, then dry the surface.

[0077] After the adhesive layer 3 is peeled off, the copper pillar bumps embedded in the adhesive layer 3 in the early stage are exposed to the outside, so that the copper pillar bumps of the chip are partially inside the plastic packaging layer 6 and partially outside the plastic packaging layer 6.

[0078] 3. Modify the copper pillar bumps of the chip: refer to Figure 4On the side of module 1 (7) with the copper pillar bumps, a non-metallic dielectric material is deposited to modify the copper pillar bumps. Using PECVD (plasma-enhanced chemical vapor deposition), silicon nitride (SiNx) is first deposited on the bottom of the plastic layer (6), where the copper pillar bumps are located, to a thickness of 250-2000 Å. Silicon dioxide (SiO2) is then deposited on top of the silicon nitride to a thickness of 5000-30000 Å. CMP (chemical mechanical polishing) is then used to polish the SiO2 to a thickness of 3000-18000 Å. Here, 1 Å = 1 × 10^(-10) meters.

[0079] After that, the copper pillar bumps on both sides of the chip are no longer exposed. There are three layers of structure on both sides of the copper pillar bumps of the chip. From top to bottom, the first layer is the plastic sealing layer 6, the second layer is silicon nitride, and the third layer is SiO2. Figure 4 Silicon nitride and SiO2 are not shown.

[0080] The bottom surface of the copper pillar bump is not covered and is exposed. For the sake of convenience, it is named as the exposed surface 8. The structure of the exposed surface 8 is convenient for subsequent bonding.

[0081] 4. Hybrid bond: see Figure 5 Module 1 7 is connected to the TSV interposer 9. Specifically, the TSV interposer 9 is removed. The TSV interposer 9 is prepared by using a dry etching process, namely an anisotropic etching process, to create horizontal and vertical deep holes 10 in the silicon substrate. The vertical deep holes 10 are connected through the horizontal deep holes 10. To accurately etch the deep holes 10 and avoid etching the unwanted sidewalls, the sidewalls can be passivated during etching. Specifically, a plasma is first used to etch a section of the deep hole 10 in the silicon substrate. A passivating gas (such as silane) is then used to deposit a thin layer of insulating material, such as silicon dioxide, on the sidewalls of the deep hole 10 to form a passivation layer. The plasma is then switched to continue etching the next section of the deep hole 10 in a specific direction. This method also maintains a sufficient etched hole diameter and depth.

[0082] To ensure a passivation layer is formed throughout the deep hole 10, a thin layer of insulating material, such as silicon dioxide, is deposited within the deep hole 10 on the silicon substrate after etching to form an insulating layer. Ti (titanium) or TiN (titanium nitride) is deposited on the insulating layer as a barrier layer. Then, a fill metal material, typically copper, is electroplated within the deep hole 10. If another metal material is chosen, a layer of copper can be deposited on the barrier layer as a seed layer before electroplating the fill metal material.

[0083] Chemical mechanical polishing (CMP) then removes excess metal material from the silicon substrate surface used for electroplating. Next, an RDL (redistribution layer) process is used to deposit insulating materials onto the silicon substrate surface. These materials include silicon nitride (SiNx), silicon dioxide, and NDC (silicon carbide) thin films. A photoresist is then applied to the insulating material, exposed using a photolithography machine, and developed to form an RDL pattern. Copper is sputter-deposited and / or electroplated within the RDL pattern to create interconnects and form an intermediate connection layer 11, which is electrically connected to the metal material within the deep hole 10. The photoresist is then stripped and any excess residue is cleaned. After these steps, the TSV interposer 9 is produced.

[0084] The exposed surface 8 of the chip's copper pillar bumps is then connected to the intermediate connection layer 11 via Cu-Cu bonding (copper-copper bonding). Copper-copper bonding is a metal-to-metal bonding method that involves the mutual diffusion of copper atoms under certain bonding process conditions to achieve interconnection and bonding. Specifically, using a bonding machine, the exposed surface 8 of the copper pillar bumps on the HBM die 5 and the SOC die 4 are aligned with the intermediate connection layer 11 of the TSV interposer 9. The copper pillar bumps and the intermediate connection layer 11 are interconnected via hot compression bonding or low-temperature bonding. If hot compression bonding is selected, the bonding parameters are 250-400°C, 5-50 MPa, and 5-30 minutes under nitrogen protection. Copper atoms diffuse under high temperature and high pressure, forming a eutectic connection between the metals. If low-temperature bonding is selected, the surface to be bonded is pretreated with formic acid vapor or formic acid solution to increase the surface roughness, lower the bonding temperature, and then bond. The bonding parameters are 150-250°C, 10-20MPa, and 10-60 minutes.

[0085] It should be noted that in the prior art, in CoWoS-S (Chip on Wafer with Silicon Interposer), microbump soldering is typically used, using solder or solder paste to reflow solder the chip to the TSV interposer 9. This can easily lead to problems such as uneven heating, solder concavity, and bulging. Unlike the prior art, the present invention does not fabricate additional copper pillars and microbumps on the TSV interposer 9. Instead, the present invention utilizes a copper intermediate connection layer 11 and the copper pillar bumps of the HBM Die 5 and the SOC Die 4 to achieve copper-to-copper bonding.

[0086] 5. Backside Via Reveal (BVR): See Figure 5 and Figure 6The bottom of the TSV interposer 9 is ground, dry-etched, PECVD (plasma-enhanced chemical vapor deposition), and CMP (chemical mechanical polishing). The aforementioned processes can grind away the excess silicon substrate at the bottom of the TSV interposer 9. If all the excess silicon substrate is removed directly by grinding, multiple problems are likely to occur, such as: 1) Cracks and fragmentation: Grinding, as a mechanical process, can easily introduce local stress into the brittle silicon material, causing microcracks or edge fragmentation, reducing structural integrity and long-term reliability. 2) Lattice damage: Grinding may destroy the lattice structure of the silicon surface, forming a defect layer, affecting carrier mobility, increasing leakage current, and reducing device performance. 3) Uneven thickness: Grinding makes it difficult to precisely control the amount of silicon substrate removed, which may lead to inconsistent TSV heights, affecting the alignment and interconnection quality of three-dimensional integration.

[0087] The transverse and longitudinal deep holes 10 constructed in the previous step of the present application have complex structures and cannot avoid the above-mentioned problems. It is not possible to directly use a single grinding process to remove all the excess silicon substrate.

[0088] Therefore, multiple processes are used here to remove excess silicon substrate, specifically:

[0089] Use a grinder to grind the bottom of the silicon substrate (the side not contacting module 1 7) to reduce the thickness d1 of the silicon substrate to 3-10 μm, where d1 is the thickness from deep hole 10 to the bottom surface of the silicon substrate. Then, use a dry etching process to etch the bottom of the silicon substrate, exposing a portion of deep hole 10 enclosed by the silicon substrate. The exposed thickness of deep hole 10 is 1-5 μm. This is to expose the electroplated copper inside deep hole 10.

[0090] Then, a PECVD (plasma enhanced chemical vapor deposition) process is used to deposit silicon nitride (SiNx) on both sides of the exposed deep hole 10, and silicon dioxide is deposited on the silicon nitride. This can protect the electroplated copper in the deep hole 10, and its two sides are no longer exposed.

[0091] CMP (chemical mechanical polishing) is then used to flatten the bottom of the silicon substrate and remove excess copper and silicon dioxide.

[0092] After the above steps, all excess silicon substrate is removed, and a TSV interposer 9 with a suitable thickness is prepared. For the convenience of description, it is named module two 12 .

[0093] 6.RDL (Redistribution Layer) process:

[0094] Reference Figure 7 and Figure 8 , use RDL process to rewire at the bottom of module 2 12, specifically:

[0095] Glue coating: Polyimide (PI) is coated on the bottom of the module 2 12 as a passivation layer to provide electrical insulation and mechanical protection.

[0096] Exposure: Use a mask to cover the passivation layer, expose it, and use light to transfer the pattern designed on the mask to the passivation layer.

[0097] Development: A developer is used to dissolve the passivation layer outside the mask, thereby leaving a designed pattern on the second module 12. The developer includes TMAH (tetramethylammonium hydroxide) or other developers.

[0098] Physical vapor deposition (PVD): After the development, titanium (Ti) and copper (Cu) layers are sputtered on the designed pattern to form a PVD layer 13. Titanium acts as an adhesion layer to prevent copper diffusion, and copper acts as an electroplating seed layer. In this way, the PVD layer 13 and the remaining passivation layer constitute the first RDL layer 14. The PVD layer 13 is electrically connected to the deep hole 10. Figure 7 structure.

[0099] Then repeat the previous steps:

[0100] Glue coating: Spin-coat photoresist on the surface of the first RDL layer 14 to form a photoresist layer.

[0101] Secondary exposure: Use a mask to cover the photoresist layer, expose it, and use light to transfer the pattern designed on the mask to the photoresist layer.

[0102] Secondary development: A developer is used to dissolve the photoresist layer outside the mask, leaving a designed pattern on the first RDL layer 14. The developer includes TMAH (tetramethylammonium hydroxide) or other developers.

[0103] Electroplating: After the secondary development, copper is electroplated on the designed pattern to form a conductive circuit 15.

[0104] Resist removal: Use chemical stripping solution to remove excess photoresist, leaving the conductive circuit 15 formed by electroplating.

[0105] Etching: Etching removes unnecessary wire lines 15, leaving only the conductive lines 15 connected to the PVD layer 13. Vacant gaps will be generated after etching, and protective materials can be filled or coated in the gaps to form a protective layer. The protective material can be polyimide (PI), thereby ensuring the reliability of the overall structure.

[0106] The conductive traces 15 and the protective layer formed by electroplating constitute the second RDL layer 16 .

[0107] The first RDL layer 14 and the second RDL layer 16 together form a complete RDL layer 17, thereby achieving the reconstruction and distribution of the circuit. Figure 8 structure.

[0108] 7. Bump process: refer to Figure 9 , a C4 bump process is used to make bumps 18 on the surface of the complete RDL layer 17. The bumps 18 need to be electrically connected to the complete RDL layer 17, that is, the bumps 18 are electrically connected to the conductive lines 15, thereby achieving line connectivity.

[0109] In Example 1, when preparing module 1 7, during the plastic encapsulation step, the molding compound also wraps the copper pillar bumps that are exposed and not embedded in the adhesive layer 3.

[0110] To realize such a structure, it is necessary to control the depth of the chip embedded in the adhesive layer 3. Example 1 states that the depth of the copper pillar bump embedded in the adhesive layer 3 is controlled to be 2-3 μm to facilitate subsequent plastic packaging.

[0111] However, it is also necessary to control the chip bonding parameters, select the molding compound material and the molding parameters, to ensure that no bubbles are generated in the molding layer 6 and the chip is not displaced by impact.

[0112] Therefore, these parameters are provided in the following examples.

[0113] Example 2

[0114] In this embodiment, the specific parameters of chip bonding are provided:

[0115] Graded control of bonding pressure:

[0116] The initial contact pressure is 0.5-1.0 MPa, ensuring that the copper pillar bump is in contact with the adhesive layer 3 but not embedded;

[0117] Embedding stage pressure: 2.5-3.5 MPa, controlling the depth of the copper pillar bump embedded in the adhesive layer 3 to be 2-3 μm;

[0118] Holding time: 8-15 seconds, to avoid excessive deformation of the adhesive layer 3.

[0119] The rest is the same as Example 1.

[0120] It should be noted that the graded pressure can prevent the copper pillar bumps from being offset or unevenly embedded due to instantaneous high pressure.

[0121] Example 3

[0122] In this embodiment, a specific molding compound is provided. The preparation of the molding compound includes the following steps, calculated in parts by weight:

[0123] 22 parts of bisphenol F epoxy resin and 6 parts of reactive diluent were put into a container, and magnetically stirred at 300-500 rpm for 15-20 minutes at room temperature to mix evenly to obtain a resin mixture.

[0124] Take 50 parts of large-size silica with a particle size of 10-20 μm, 10 parts of small-size silica with a particle size of 0.1-0.5 μm, and 2 parts of nanoparticles with a particle size of 50-100 nm, add these three powders into a high-speed mixer, dry mix for 5-10 minutes, mix evenly, and obtain a mixed powder.

[0125] Slowly add the resin mixture into the mixed powder while stirring, disperse at 1000-1500 rpm for 10-15 minutes, gradually increase the speed to 2000-2500 rpm, and continue dispersing for 15-20 minutes to obtain a mixture.

[0126] 0.3 parts of a defoamer and 0.2 parts of a leveling agent were added to the mixture, and the mixture was stirred at 1500 rpm for 5 minutes to obtain a mixed solution. The defoamer can reduce bubbles in the molding compound, and the leveling agent can improve the fluidity of the molding compound.

[0127] Before use, slowly add 9.5 parts of modified amine curing agent to the mixed solution, stir at 1000 rpm for 10 minutes, and then vacuum degas: under a vacuum degree of -0.095 MPa, stir and degas at a speed of 800 rpm for 15 minutes to remove bubbles in the mixture and obtain a molding compound.

[0128] Among the above, the specific selection of raw materials used in this embodiment is:

[0129] Bisphenol F epoxy resin: epoxy equivalent weight 160-180g / eq, viscosity 3000-4000cps (25°C), NPEF-170 bisphenol F epoxy resin can be selected;

[0130] Reactive diluent: siloxane oligomer, Evonik TEGOPREN® 6875;

[0131] Large size silica: spherical, ADMAFINE® SO-E5, Admatechs;

[0132] Small size silica: spherical, Admatechs® SO-C3, Admatechs;

[0133] Nanoparticles: α-phase nano silicon nitride particles (Si3N4), particle size 50-100nm, silicon content 99%;

[0134] Defoaming agent: BYK-A 530, BYK;

[0135] Leveling agent: BYK-354, BYK;

[0136] Modified amine curing agent: Huntsman Aradur 2958.

[0137] Furthermore, it is worth mentioning that

[0138] (1) Resin system:

[0139] Main Resin: Low-viscosity, highly reactive bisphenol F epoxy resin is used. Compared to traditional bisphenol A epoxy resin, the selected bisphenol F resin has lower viscosity, better fluidity, and faster curing speed, which is beneficial for filling small gaps and reducing bubble generation.

[0140] Reactive diluent: Add a small amount of epoxy-functional siloxane oligomer. The selected siloxane oligomer not only reduces the viscosity of the resin system and improves fluidity, but also reacts with the epoxy resin to form flexible siloxane segments, improving the toughness and impact resistance of the molding compound.

[0141] (2) Multi-level composite fillers: Fillers of different sizes and functions are combined. Large-size silica is large-size silica, which is used as the main filler with a particle size of 10-20 μm and a weight of 50-70 parts. It provides low thermal expansion coefficient and high filling capacity. Small-size silica is submicron spherical silica with a particle size of 0.1-0.5 μm and a weight of 10-15 parts. It fills the gaps between large particles, increases the packing density, and reduces the viscosity. Nanoparticles are α-phase nano-silicon nitride (Si3N4) particles, which are dispersed in the matrix. They have high surface activity and form strong chemical bonds with the matrix, thereby improving the interface strength.

[0142] (3) Additives: For defoaming agents, choose a highly efficient silicone defoaming agent that can quickly eliminate bubbles generated during mixing and potting. For leveling agents, choose an acrylic leveling agent that can improve fluidity and reduce surface defects.

[0143] (4) Curing agent: Use a low-viscosity, highly reactive modified amine curing agent. This curing agent can cure quickly at a lower temperature, reducing shrinkage and stress during the curing process.

[0144] (5) After curing, the molding compound forms a multi-phase composite structure:

[0145] Continuous phase: polymer network formed by cross-linking of epoxy resin, reactive diluent and curing agent.

[0146] Dispersed phase: Large, spherical silica particles are evenly distributed throughout the matrix. Smaller silica particles fill the gaps between the larger particles. Core-shell nanoparticles are dispersed throughout the matrix and form strong chemical bonds with it.

[0147] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A method for preparing a multi-chip connection structure, characterized in that: The steps include: coating a release layer on the substrate, and coating an adhesive layer on the release layer; The chip includes SOC Die and HBM Die. There are copper pillar bumps on the chip. The chip is temporarily bonded to the adhesive layer, and the copper pillar bumps of the control part are embedded in the adhesive layer. forming a plastic encapsulation layer on the adhesive layer, the plastic encapsulation layer encapsulating the chip and the remaining copper pillar bumps, the chip and the plastic encapsulation layer together constituting module one; The adhesive layer is peeled off, and the copper pillar bumps embedded in the adhesive layer are exposed. A non-metallic dielectric material is deposited on the side of the module with the copper pillar bumps to modify the copper pillar bumps so that both sides of the copper pillar bumps are no longer exposed. The remaining exposed surface of the copper pillar bumps is then copper-copper bonded to the TSV interposer. Remove excess silicon substrate from the TSV interposer to obtain module 2, build a complete RDL layer at the bottom of module 2, and make bumps on the surface of the complete RDL layer; The method for preparing the TSV interposer includes the following steps: Anisotropic etching is used to form horizontal and vertical deep holes on a silicon substrate, and the vertical deep holes are connected by horizontal deep holes. An insulating layer is deposited in the deep hole of the silicon substrate, a barrier layer is deposited on the insulating layer, and then a seed layer is deposited or not deposited, and a metal material is electroplated in the deep hole to remove excess metal material on the surface of the silicon substrate; then the RDL process is used on the surface of the silicon substrate, specifically, insulating material is deposited on the surface of the silicon substrate, and then photoresist is coated on the insulating material, exposed and developed to form an RDL circuit pattern, and metal copper is sputter-deposited and / or electroplated in the RDL circuit pattern to form an interconnection line to form an intermediate connection layer, and the photoresist is stripped off to obtain a TSV interposer.

2. The method for preparing a multi-chip connection structure according to claim 1, wherein: The temporary bonding steps include: using a bonding machine to symmetrically arrange every two HBM Dies on both sides of a SOC Die, bonding the copper pillar bumps of the HBM Die and SOC Die to the adhesive layer with the surface facing down, and controlling the depth of the copper pillar bumps embedded in the adhesive layer to be 2-3μm; wherein, the total number of HBM Dies is ≥2, and the total number of SOC Dies is ≥1.

3. The method for preparing a multi-chip connection structure according to claim 1, wherein: There are copper pillar bumps on the metal pads of SOC Die, with a height of 4-8μm and a width of 5-25μm; there are copper pillar bumps on the metal pads of HBM Die, with a height of 4-8μm and a width of 5-25μm.

4. The method for preparing a multi-chip connection structure according to claim 1, wherein: When the deep hole is electroplated with a metal material, the metal material includes copper; when the remaining exposed surface of the copper pillar bump is copper-copper bonded to the TSV interposer, the exposed surface is copper-copper bonded to the intermediate connection layer.

5. The method for preparing a multi-chip connection structure according to claim 1, wherein: Removing excess silicon substrate from the TSV interposer includes the following steps: Use a grinder to reduce the excess silicon substrate thickness d1 to 3-10μm, then use an etching process to etch the bottom of the silicon substrate to expose a portion of the deep hole wrapped by the silicon substrate. The exposed thickness of the deep hole is 1-5μm. Then use a PECVD process to deposit non-metallic dielectric material on both sides of the exposed deep hole, and then use a CMP process to flatten the bottom of the silicon substrate.

6. The method for preparing a multi-chip connection structure according to claim 1 or claim 5, characterized in that: The non-metallic dielectric material includes at least one of silicon nitride and silicon dioxide.

7. The method for preparing a multi-chip connection structure according to claim 1, wherein: Building a complete RDL layer at the bottom of module 2 involves the following steps: A passivation layer is formed on the bottom of module 2. A mask is used to cover the passivation layer, and the passivation layer outside the mask is exposed and dissolved, leaving a designed pattern on module 2. Titanium and copper layers are sputtered on the designed pattern to form a PVD layer. The PVD layer and the remaining passivation layer constitute the first RDL layer. A photoresist layer is formed on the first RDL layer, a mask is used to cover the photoresist layer, and the photoresist layer outside the mask is exposed to light. The photoresist layer is dissolved, leaving a designed pattern on the first RDL layer. Copper is electroplated on the designed pattern to form a conductive circuit; Remove the remaining photoresist and retain the conductive circuit formed by electroplating; Etching removes unnecessary conductive lines, leaving only the conductive lines connected to the PVD layer. After etching, vacant gaps are generated, and a protective layer is formed in the gaps. The conductive lines and the protective layer constitute the second RDL layer; The first RDL layer and the second RDL layer together constitute a complete RDL layer.

8. The method for preparing a multi-chip connection structure according to claim 1, wherein: Temporary bonding parameters include: initial contact pressure of 0.5-1.0 MPa, the copper pillar bump contacts the adhesive layer but is not embedded; embedding stage pressure of 2.5-3.5 MPa, a controlled portion of the copper pillar bump is embedded in the adhesive layer; and holding time of 8-15 seconds.

9. The method for preparing a multi-chip connection structure according to claim 1, wherein: Plastic encapsulation uses molding compound, and the preparation of molding compound includes the following steps: Bisphenol F epoxy resin and reactive diluent are mixed evenly to obtain a resin mixture. Large-sized silica, small-sized silica and nanoparticles are uniformly mixed to obtain a mixed powder; Slowly add the resin mixture into the mixed powder and stir to obtain a mixture; Add defoaming agent and leveling agent to the mixture, stir to obtain a mixed solution; Slowly add the curing agent into the mixed solution, stir, and vacuum degas to obtain a molding compound; The particle size of the large-sized silicon dioxide is 10-20 μm, the particle size of the small-sized silicon dioxide is 0.1-0.5 μm, and the active diluent includes siloxane oligomer.

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