Calibration method for annealing parameters of wafer structure and epitaxial growth equipment for temperature measurement

Abstract

The present application provides a wafer structure for temperature measurement and a method for calibrating annealing parameters of an epitaxial growth device. The wafer structure comprises a plurality of wafer units arranged in an array, each of the wafer units comprising a plurality of grooves, namely a first groove, a second groove, and a third groove. Each groove comprises a body portion and a doping portion, the body portion having a recess, the doping portion being located on the bottom surface of the body portion. The first groove is located in the center region of the wafer unit, a plurality of second grooves are sequentially spaced around the periphery of the first groove in a direction away from the first groove, and a third groove connects the first groove and the plurality of second grooves, such that the doping portion of the first groove contacts the doping portion of the second groove, and the aspect ratio of the grooves is greater than 2. The wafer structure for temperature measurement disclosed in the present application solves the problem that the wafer structure cannot reflect the temperature distribution in the reaction chamber of the epitaxial growth device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a method for calibrating annealing parameters of a wafer structure and epitaxial growth equipment for temperature measurement. Background Art

[0002] When growing a silicon carbide epitaxial layer on a wafer, the uniformity of the wafer surface temperature distribution significantly affects the doping concentration, film thickness distribution, defect types, and defect count of the epitaxial layer grown on the wafer. Furthermore, during the silicon carbide growth process, 3C-SiC byproducts are deposited on the surface of the graphite parts within the chamber. This byproduct directly affects the quality of epitaxial growth. Therefore, during actual production, the reaction chamber is regularly opened to clean the byproducts from the graphite parts. After the cleaned graphite parts are reinstalled, epitaxial growth on the wafer may cause changes in the temperature field, affecting the stability of the epitaxial process. Therefore, a uniform temperature distribution within the reaction chamber is crucial to maintaining a stable epitaxial process.

[0003] Existing high-temperature testing technologies are divided into contact measurement and non-contact measurement. Among them, non-contact measurement is difficult to reflect the surface temperature distribution of epitaxial wafers due to limited temperature measurement points in SiC epitaxial furnaces; contact measurement usually extends the detector into the reaction chamber for detection, but this will introduce impurities into the reaction chamber, and the existing temperature measuring wafers cannot reflect the temperature distribution of the reaction chamber, which makes it difficult to accurately control the temperature distribution of the reaction chamber, easily leading to uneven surface temperature distribution of the wafer, making the thickness and doping concentration of the generated epitaxial layer uneven, and generating temperature-related defects such as stacking faults, triangular defects and micro-pits, which are difficult to effectively control.

[0004] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country to those skilled in the art. Summary of the Invention

[0005] The main purpose of this application is to provide a method for calibrating the annealing parameters of a wafer structure and an epitaxial growth device for temperature measurement, so as to solve the problem in the prior art that the wafer structure cannot reflect the temperature distribution in the reaction chamber of the epitaxial growth device.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a wafer structure for temperature measurement is provided, comprising a plurality of wafer units arranged in an array, the wafer unit comprising a plurality of grooves, the plurality of grooves being respectively a first groove, a second groove and a third groove, each of the grooves comprising a main body and a doping part, the main body having a groove, the doping part being located on the bottom surface of the main body, the first groove being located in the central area of ​​the wafer unit, a plurality of the second grooves being arranged in sequence and spaced around the periphery of the first groove in a direction away from the first groove, the third groove connecting the first groove and the plurality of the second grooves, so that the doping part of the first groove is connected to the doping part of the second groove, and the aspect ratio of the groove is greater than 2.

[0007] Optionally, the wafer structure further includes a fourth trench, wherein the fourth trench connects the first trench and the second trench, and the aspect ratio of the fourth trench is greater than the aspect ratio of the third trench.

[0008] Optionally, in a direction away from the first trench, intervals between adjacent second trenches increase gradually, and the wafer structure further includes a conductive layer, wherein the conductive layer is in contact with the doped portion.

[0009] Optionally, part of the conductive layer is located on the first surface of the wafer unit.

[0010] Optionally, the doping elements of the doping part include any one or more of P, N, Al, Li, Ga, Be and Ge.

[0011] Optionally, a minimum distance between the second groove farthest from the first groove and the first groove is greater than or equal to 0.5 mm.

[0012] According to another aspect of the present application, a method for correcting annealing parameters of an epitaxial growth device is provided, the correction method comprising: annealing a wafer structure, the wafer structure being the wafer structure for temperature measurement; after the annealing, selecting a plurality of wafer units from the wafer structure, and detecting the wafer units using a detection device to obtain a plurality of resistivities of the plurality of wafer units; determining a plurality of actual temperatures of the plurality of wafer units based on a preset relationship and the resistivity, the preset relationship being the relationship between the resistivity and the temperature of the annealing treatment, and adjusting the annealing parameters of each region of the epitaxial growth device based on the target temperature of the annealing treatment and the plurality of actual temperatures, so that the plurality of actual temperatures of the plurality of wafer units after the annealing treatment all reach the target temperature.

[0013] Optionally, the step of obtaining the preset relationship includes: performing the annealing treatment with different temperatures on the multiple wafer structures; after the annealing treatment, selecting multiple wafer units in each wafer structure respectively, and using the detection equipment to detect the multiple wafer units to obtain the resistivity of the multiple wafer units; according to the temperature of the annealing treatment and the resistivity, obtaining the preset relationship between the temperature and the resistivity.

[0014] Optionally, the step of using a detection device to detect the wafer unit to obtain the resistivity of multiple wafer units includes: using a contact resistance testing device to detect the wafer unit to obtain the square resistance of the doped part of the wafer unit; and obtaining the resistivity of the wafer unit based on the square resistance and the length of the detection line used by the contact resistance testing device.

[0015] Optionally, the step of using a detection device to detect the wafer unit to obtain the resistivity of the plurality of wafer units includes: using a single-column dielectric resonant cavity to detect the wafer unit to obtain the resistivity of the wafer unit.

[0016] The technical solution of the present application is applied to a wafer unit, wherein the plurality of grooves include a first groove, a second groove, and a third groove. The grooves include a main body and a doping portion. The doping portion is located at the bottom of the groove of the main body, and the depth-to-width ratio of the groove is greater than or equal to 2. This can prevent the gas in the epitaxial process conditions in the reaction chamber from diffusing to the bottom of the groove to a certain extent, and protect the doping portion in the groove from being etched by the high-temperature gas therein under the epitaxial process conditions. The first groove is located in the central area of ​​the wafer, the second grooves are spaced around the periphery of the first groove, and there is a gap between adjacent second grooves. The third groove connects the first groove and the second groove, so that the plurality of grooves are interconnected, the doping portion of the first groove contacts the doping portion of the second groove, and the doping portion is conductive, so that a current loop is formed in the wafer unit. When there is current in the wafer unit, its resistivity can be obtained. Since there is a preset relationship between the resistivity and the annealing temperature of the reaction chamber, the annealing temperature of each area in the reaction chamber can be obtained based on the resistivity, and thus the temperature distribution in the reaction chamber can be obtained. The above wafer structure solves the problem in the prior art that the wafer structure cannot reflect the temperature distribution in the reaction chamber of the epitaxial growth equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0018] Figure 1A schematic diagram of a top view of a wafer structure for temperature measurement proposed in an embodiment of the present application is shown;

[0019] Figure 2 A schematic diagram of a top view of a wafer unit proposed in an embodiment of the present application is shown;

[0020] Figure 3 A schematic cross-sectional structure diagram of a wafer unit proposed in an embodiment of the present application is shown;

[0021] Figure 4 A schematic diagram of a top view of another wafer unit proposed in an embodiment of the present application is shown;

[0022] Figure 5 A schematic cross-sectional structure diagram of another wafer unit proposed in an embodiment of the present application is shown;

[0023] Figure 6 FIG2 shows a schematic diagram of a top view of another wafer unit proposed in an embodiment of the present application;

[0024] Figure 7 A flow chart of a method for correcting annealing parameters of an epitaxial growth device proposed in an embodiment of the present application is shown.

[0025] The above drawings include the following reference numerals:

[0026] 1. Wafer structure; 2. Wafer unit; 3. First trench; 4. Second trench; 5. Third trench; 6. Main body; 7. Doped part; 8. Conductive layer; 9. Fourth trench. DETAILED DESCRIPTION

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0028] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0029] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "include" and "have," as well as any synonyms of "include" and "have," are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0031] As described in the background technology, in the prior art, a detector is usually inserted into the reaction chamber for detection. However, this will introduce impurities into the reaction chamber, and the existing temperature measurement wafer cannot reflect the temperature distribution of the reaction chamber, which makes it difficult to accurately control the temperature distribution of the reaction chamber. This can easily lead to uneven surface temperature distribution of the wafer, resulting in uneven thickness and doping concentration of the generated epitaxial layer, and thus more defects in the epitaxial layer. To solve the problem that the wafer structure in the prior art cannot reflect the temperature distribution in the reaction chamber of the epitaxial growth equipment, the embodiments of the present application provide a wafer structure for temperature measurement and a method for calibrating the annealing parameters of the epitaxial growth equipment.

[0032] According to one aspect of this application, Figures 1 to 3 As shown, a wafer structure 1 for temperature measurement is provided, comprising a plurality of wafer units 2 arranged in an array, the wafer unit 2 including a plurality of grooves, namely a first groove 3, a second groove 4, and a third groove 5. Each groove includes a body portion 6 and a doping portion 7. The body portion 6 has a recess, and the doping portion 7 is located on the bottom surface of the body portion 6. The first groove 3 is located in the center region of the wafer unit 2; a plurality of second grooves 4 are sequentially and spaced apart around the periphery of the first groove 3 in a direction away from the first groove 3; and a third groove 5 connects the first groove 3 and the plurality of second grooves 4. The third groove 5 penetrates the first groove 3 and the plurality of second grooves 4, such that the doping portion 7 of the first groove 3 and the doping portion 7 of the second groove 4 are interconnected, and the aspect ratio of the grooves is greater than 2. The body portion 6 and the doping portion 7 can be an integral structure or two separate structures.

[0033] Since the existing temperature measuring wafer is etched by the gas for cleaning the surface of the temperature measuring wafer under epitaxial conditions when detecting the annealing temperature under epitaxial conditions in the reaction chamber, due to the stability of the temperature measuring wafer material, the thickness of the conductive layer formed by injection / diffusion in the temperature measuring wafer is relatively small, and it will be completely etched away under epitaxial conditions, and thus the conductive layer of the wafer cannot be used to reflect the annealing temperature of the reaction chamber, and it is difficult to directly obtain the temperature distribution of the reaction chamber through the temperature measuring wafer, and thus it is difficult to adjust the temperature distribution of the reaction chamber. The present application connects the third groove of the wafer unit to the first groove and the second groove, so that the multiple grooves are interconnected. The groove includes a main body and a doping part, and the doping part is located at the bottom of the groove of the main body. Since the multiple grooves are interconnected, the doping parts on the bottom surface of the main body groove of different grooves are also in contact with each other, and the doping part forms a closed loop structure connected end to end, and the doping part can be conductive, so that the wafer unit has a current loop, and the resistivity of the wafer unit can be known when there is current in the wafer unit. Because resistivity has a predetermined relationship with the annealing temperature of the reaction chamber, the annealing temperature of each region within the reaction chamber, and thus the temperature distribution within the reaction chamber, can be determined based on the resistivity. This wafer structure solves the problem in existing technologies where wafer structures cannot accurately reflect the temperature distribution within the reaction chamber of epitaxial growth equipment.

[0034] Figure 1 The x and y in the figure are two coordinate axes set for setting the wafer units arranged in an array, wherein the marking form of the coordinate axes is not limited thereto.

[0035] Typically, epitaxial growth conditions in the reaction chamber are performed under simulated growth conditions, typically at temperatures of 1500°C to 1700°C, reaction pressures of 60 to 200 mbar, and annealing atmospheres of H2 (or HCl), Ar, or a mixture of both, with an H2 (or HCl) flow rate of 20 to 200 SLM. At high temperatures, H2 (or HCl) reacts with the doped regions, consuming them. When the doped regions are produced by ion implantation / diffusion, the thickness of the doped regions formed by ion implantation / diffusion is relatively small (approximately 100 nm to 2 μm) due to the stable material properties of the SiC wafer. Furthermore, H2 (or HCl) at high temperatures has a strong etching effect on SiC wafers. If the doped regions are formed directly on the wafer surface by ion implantation and then annealed in a high-temperature H2 (or HCl) environment, the high-temperature H2 (or HCl) will directly etch away the relatively thin doped regions, destroying the doped regions and causing distortion in the temperature measurement data. Consequently, the resistivity reading of the doped regions cannot be read, making it impossible to match the annealing temperature. To alleviate the aforementioned issues, the present application limits the trench's aspect ratio to a range of greater than or equal to 2. This makes it more difficult for H2 (or HCl) to diffuse to the trench bottom, resulting in less H2 (or HCl) at the bottom and reducing the etching effect on the doped portion. For example, when the trench is wide, the depth will be sufficiently deep. Thus, even if the trench is wide, H2 (or HCl) can easily diffuse into the trench. However, due to the deep depth, the amount of H2 (or HCl) that diffuses to the trench bottom will be relatively small, thus minimizing the impact on the doped portion. Limiting the trench's aspect ratio to this range allows the trench to be narrow enough when the depth is small. Due to the narrow width, very little H2 (or HCl) diffuses to the trench bottom and contacts the doped portion. Even at a shallow depth, the concentration of H2 (or HCl) that contacts the doped portion will be relatively low, thus minimizing the impact on the doped portion.

[0036] Furthermore, the low H2 (or HCl) concentration at the bottom of the bulk makes it more difficult for the substances produced by the reaction between H2 (or HCl) and the doped portion to be removed, further reducing the reactive etching rate. On a normal flat SiC wafer surface, the H2 (or HCl) etching rate for the doped portion is approximately 50nm / min. At the bottom of the trench, the doped portion is etched at a rate of approximately 2nm / h, essentially leaving the doped portion unaffected.

[0037] In some optional embodiments, the doping elements of the doping part include any one or more of P, N, Al, Li, Ga, Be and Ge. The diffusion rate of the above-mentioned doping elements after being injected into the wafer structure is slow, and it is difficult to diffuse out of the wafer structure, which can prevent the elements from diffusing out and causing pollution to the chamber during the annealing process. When the epitaxial process temperature is 1500~1800℃, the diffusion rate of the above-mentioned doping elements is slow, and the resistivity will not be inaccurate due to diffusion, and it is suitable to use resistivity to reflect temperature changes. The diffusion range of the above-mentioned doping elements at a high temperature of 1800℃ is 10 -17 ~10 -15 cm 2 / s.

[0038] In some embodiments, the wafer structure may be a semi-insulating silicon carbide wafer, and the crystal orientation may be <0001> 4H-SiC, or crystal orientation <0001> 6H-SiC, the resistivity of the wafer structure is greater than 10 12 Ωcm.

[0039] In some embodiments, the doped portion can be prepared by ion implantation (implantation temperature ≤ 500°C) or diffusion process. The thickness of the doped portion can be 50nm~2000nm. This allows the wafer unit to be made thicker if the manufacturing process allows. A thicker thickness can make the doped portion more stable, and even if part of the doped portion is consumed, it will not affect the overall doped portion. The doping concentration can be 1×10 18 ~5×10 20 cm -3 , such as 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm - 3.3×10 20 cm -3 SiC wafers are wide-bandgap semiconductor materials whose resistivity depends on the concentration of carriers (free electrons or holes). Introducing dopant ions into SiC wafers can change the wafer's conductivity. As the doping concentration increases, the carrier concentration also increases, and the resistivity of the material decreases. Using high-concentration doping within the above range in the doped portion makes the effect of temperature on the carrier concentration in the doped portion more sensitive. Even small changes in temperature can cause large changes in carrier concentration, leading to significant changes in resistivity. This can better reflect small changes in temperature and more accurately reflect the temperature distribution in the reaction chamber.

[0040] In some optional embodiments, such as Figure 4 and Figure 5 As shown, in the direction away from the first trench 3, the intervals between adjacent second trenches 4 increase, and the wafer structure further includes a conductive layer 8, which is in contact with the doped portion 7. Figure 4 As shown in the dashed box, the spacing between adjacent second trenches 4 gradually increases as they move away from the first trench 3. This allows for data measurement points with varying spacing between adjacent second trenches 4. Based on more data measurement points, the resistivity of the wafer unit within the wafer structure can be more accurately determined. This improved resistivity accuracy can also further enhance the precision of the temperature reflected by the resistivity, thereby improving the accuracy of the resulting temperature distribution.

[0041] In some optional embodiments, such as Figure 6 As shown, the wafer structure also includes a fourth trench 9, which connects the first trench 3 and the second trench 4. More resistivity measurement points can be added to the wafer structure at the fourth trench 9. Based on more data measurement points, the resistivity of the wafer units in the wafer structure can be more accurately obtained. On the basis of improved resistivity accuracy, the accuracy of the temperature reflected by the resistivity can also be further improved, thereby improving the accuracy of the final temperature distribution. The aspect ratio of the fourth trench 9 is greater than that of the third trench 5. The introduction of the fourth trench 9 with a doped portion and a larger aspect ratio can effectively block gas diffusion to the bottom of the trench by increasing the trench's aspect ratio, reducing the contact between H2 or (HCl) and the doped portion 7, thereby significantly reducing the etching rate of H2 or (HCl) on the doped portion at high temperatures and protecting the integrity of the doped portion 7.

[0042] In some optional embodiments, such as Figure 2 、 Figure 4 and Figure 6 As shown, the minimum distance between the second groove 4 farthest from the first groove 3 and the first groove 3 is greater than or equal to 0.5 mm, that is, the diameter D of the second groove 4 farthest from the first groove 3 is greater than or equal to 1 mm. Setting the diameter of the overall structure formed by the grooves of the wafer unit 2 to be greater than or equal to 1 mm not only generates a current loop with a large current to facilitate resistivity calculation, but also ensures that the number of wafer units 2 in the wafer structure is sufficient to reflect the temperature distribution on the surface of the wafer structure. The overall size of the grooves in each wafer unit 2 is large enough to meet the requirements of various non-contact testing technologies, including single-column dielectric resonance testing, thereby increasing the flexibility and applicability of the temperature measurement solution.

[0043] In some embodiments, microfluidic cooling channels are added to the back or side of the wafer structure and filled with cooling liquid or gas. If there are slight errors in the calibration of the epitaxial growth equipment, the overall temperature of the wafer structure can be adjusted by circulating the liquid or gas, thereby minimizing the uneven surface temperature distribution caused by such errors. The microfluidic cooling channels can actively control the wafer temperature, reducing temperature unevenness caused by heat accumulation, and further improving the temperature controllability of epitaxial growth on the wafer structure.

[0044] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0045] Figure 7 FIG. 1 is a flow chart of a method for correcting annealing parameters of an epitaxial growth device according to an embodiment of the present application. Figure 7 As shown, the method includes the following steps:

[0046] Step S201, performing annealing treatment on the wafer structure, the wafer structure being the wafer structure used for temperature measurement;

[0047] Specifically, the wafer structure can be a semi-insulating silicon carbide wafer with a crystal orientation of <0001> 4H-SiC, or crystal orientation <0001> 6H-SiC, the resistivity of the wafer structure is greater than 10 12 This wafer structure is used to test the annealing parameters at various locations in the epitaxial growth equipment, and the annealing temperature of the above annealing process is a known temperature.

[0048] Step S202, after the annealing process, selecting a plurality of wafer units in the wafer structure, and testing the wafer units using a testing device to obtain a plurality of resistivities of the plurality of wafer units;

[0049] Specifically, multiple wafer units in a square array or a 'P-shaped' array can be selected from the wafer structure as test units, and the doped portions of these test units are tested to obtain the resistivity of the doped portions. The testing equipment can be non-contact, such as the single-post dielectric resonator (SiPDR) method, or contact, such as the transmission length method.

[0050] In step S203, a plurality of actual temperatures of a plurality of wafer units are determined according to a preset relationship and resistivity, wherein the preset relationship is the relationship between resistivity and the temperature of the annealing treatment, and the annealing parameters of each area of ​​the epitaxial growth equipment are adjusted according to the target temperature of the annealing treatment and the plurality of actual temperatures, so that the plurality of actual temperatures of the plurality of wafer units after the annealing treatment all reach the target temperature.

[0051] Specifically, prior to the aforementioned tests, multiple sets of measurements were performed on the epitaxial growth equipment's annealing conditions using multiple wafer structures, yielding a pre-determined relationship between resistivity and annealing temperature. This pre-determined relationship was then matched with the previously determined resistivity to determine the actual surface temperature of each wafer unit, reflecting the actual annealing temperature of the reaction chamber within that wafer unit. The actual annealing temperature was then adjusted based on the target temperature to calibrate the annealing parameters of the epitaxial growth equipment's reaction chamber.

[0052] Through this embodiment, the resistivity of the doped parts of multiple wafer units is detected, and combined with the preset relationship, the temperature of each area on the surface of the wafer structure can be reflected, which is equivalent to directly reflecting the actual temperature distribution of the reaction chamber (or the surface of the wafer structure). According to the actual temperature distribution, the annealing temperature of the areas in the reaction chamber that exceed or fall below the target temperature can be regulated, thereby ensuring the uniformity of the annealing temperature in each area of ​​the reaction chamber. When the regulated reaction chamber performs epitaxial growth on a wafer structure that needs to be epitaxially grown, the surface of the wafer structure can be heated evenly, thereby obtaining a uniform surface temperature distribution, and an epitaxial layer with uniform epitaxial thickness and doping concentration can be formed on the wafer structure. On the other hand, after replacing the internal graphite parts of the epitaxial growth equipment, the epitaxial growth equipment with the new graphite parts can be tested, and the temperature field can be regulated based on the preset relationship between the resistivity and the annealing temperature of the test results. In this way, after replacing the graphite parts, the annealing temperature of each area in the reaction chamber of the epitaxial growth equipment can be made uniform. When epitaxial growth is performed on the wafer structure, a uniform temperature distribution can be achieved on the surface of the wafer structure, making the thickness and doping concentration of the generated epitaxial layer more uniform and having fewer defects. The above-mentioned correction method using the wafer structure can obtain the resistivity of the wafer structure, and then realize the application of the wafer structure to the detection of the annealing temperature distribution of the reaction chamber of the epitaxial processing equipment, and further adjust it, thereby solving the problem in the prior art that the wafer structure cannot reflect the temperature distribution in the reaction chamber of the epitaxial growth equipment.

[0053] In a specific implementation, before step S201, the method further includes: performing annealing treatments at different temperatures on the multiple wafer structures; after the annealing treatments, selecting multiple wafer units from each wafer structure and testing the multiple wafer units using a testing device to obtain the resistivity of the multiple wafer units; and obtaining a preset relationship between temperature and resistivity based on the annealing temperature and resistivity. This provides a basis for subsequently adjusting epitaxial growth equipment using the wafer structure.

[0054] In the above implementation process, each set of resistivity-temperature relationship tests requires a new temperature measurement unit. The temperature measurement unit is not necessarily the entire wafer structure, but can also be multiple wafer units (with doped parts). The wafer unit is formed after the entire wafer structure is laser cut.

[0055] In some embodiments, multiple wafer structures are placed in an epitaxial growth apparatus for annealing. The annealing temperature is known, and the annealing temperature of each wafer structure is different. After the annealing process is completed, the resistivity of the doped portions of multiple wafer units in each wafer structure can be calculated using a resistance testing method and the current in the above-mentioned current loop. A preset relationship is then established between the above-mentioned resistivity and temperature. Using the same wafer structure to establish the preset relationship can make the subsequent matching of resistivity and annealing temperature more accurate.

[0056] In order to provide a more accurate detection of the preset relationship between resistivity and temperature, the above-mentioned step S202 of the present application can be implemented by the following steps: using a detection device to detect the wafer unit to obtain the resistivity of multiple wafer units, including: using a contact resistance test device to detect the wafer unit to obtain the square resistance of the doped part of the wafer unit; and obtaining the resistivity of the wafer unit based on the square resistance and the length of the detection line used by the contact resistance test device. The contact detection method is more accurate than the non-contact detection method, so that the preset relationship between resistivity and temperature can be more accurately established.

[0057] The detection method adopted by the above-mentioned contact resistance testing equipment may be a transmission length method. The transmission length method can establish a linear relationship between the total resistance and the spacing (total resistance = contact resistance + bulk resistance × spacing) by measuring the total resistance between the electrodes in contact with the doped part at different spacings in the wafer unit, wherein the total resistance, contact resistance and spacing can all be obtained by measurement, and then calculated by the expression of the linear relationship to obtain the bulk resistance of the doped part (unit volume resistance, also called block resistance). The resistivity of the doped part is then calculated based on the bulk resistance and the length of the transmission line adopted by the transmission length method. The spacing between adjacent second grooves in the wafer unit of the present application increases, and combined with the conductive layer, multiple measurement points can be provided to establish the above-mentioned linear relationship. Moreover, the resistivity detection of the wafer unit of the present application can adopt non-contact detection methods and contact detection methods, which has strong flexibility.

[0058] The linear relationship between total resistance and spacing is expressed as:

[0059] R t =2R c +(R sh / W)d,

[0060] Among them, R t is the total resistance between the two conductive layers, R c is the contact resistance between the conductive layer and the doped part, R sh is the sheet resistance (unit volume resistance) of the doped part, d is the distance between the two conductive layers, and W is the width of the contact portion between the conductive layer and the doped part.

[0061] Rsh can be calculated using the above expression, and the resistivity can be calculated using the following expression:

[0062] ,

[0063] in, is the resistivity, L T is the length of the transmission line used in the transmission line length method.

[0064] The resistivity of the doped portion is obtained using the transmission line length method or the single-pillar dielectric resonant cavity testing method, and then a preset relationship between the resistivity and the annealing temperature is established based on the annealing temperature. Alternatively, after obtaining the resistivity, the activation rate of the doped portion of the wafer unit at that location can be further inferred, thereby obtaining a preset relationship between the activation rate and the annealing temperature information. The temperature of various locations in the reaction chamber of the subsequent epitaxial growth equipment is adjusted based on this preset relationship. The above technical solution also allows the wafer structure to be tested using both the single-pillar dielectric resonant cavity testing method and the transmission line testing method, making the use of the wafer structure more flexible.

[0065] In some embodiments, the above-mentioned step S203 can be specifically implemented by the following steps: the step of using a detection device to detect the wafer unit to obtain the resistivity of multiple wafer units includes: using a single-column dielectric resonant cavity to detect the wafer unit to obtain the resistivity of the wafer unit. The non-contact detection method using a single-column dielectric resonant cavity can reduce manual operation. After selecting the wafer unit to be detected, the mobile device is controlled to move the wafer unit to the top of the single-column dielectric resonant cavity for detection. The operation process of this method is simpler.

[0066] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for correcting the annealing parameters of the epitaxial growth equipment of the present application will be described in detail below with reference to specific embodiments.

[0067] This embodiment relates to a specific method for calibrating annealing parameters of epitaxial growth equipment, comprising the following steps:

[0068] Step S1: performing annealing treatments at different temperatures on multiple wafer structures.

[0069] Step S2: After the annealing treatment, a plurality of wafer units are selected from each wafer structure, and a detection device is used to detect the plurality of wafer units to obtain the resistivity of the plurality of wafer units.

[0070] Step S3: obtaining a preset relationship between temperature and resistivity according to the temperature and resistivity of the annealing treatment.

[0071] Step S4: performing annealing treatment on the wafer structure, where the wafer structure is the wafer structure used for temperature measurement.

[0072] Step S5: After the annealing process, a plurality of wafer units are selected from the wafer structure, and the wafer units are tested using a testing device to obtain a plurality of resistivities of the plurality of wafer units.

[0073] Step S6: Determine multiple actual temperatures of multiple wafer units based on a preset relationship and resistivity, where the preset relationship is the relationship between resistivity and the temperature of the annealing treatment, and adjust the annealing parameters of each area of ​​the epitaxial growth equipment based on the target temperature of the annealing treatment and the multiple actual temperatures so that the multiple actual temperatures of the multiple wafer units after the annealing treatment all reach the target temperature.

[0074] From the above description, it can be seen that the method for calibrating the annealing parameters of the wafer structure and epitaxial growth equipment for temperature measurement provided by the present application achieves the following technical effects:

[0075] 1) The multiple wafer units in the wafer structure for temperature measurement in the present application can be used as temperature measurement units for temperature measurement. The wafer structure is placed in an epitaxial growth device that requires adjusting the temperature of the reaction chamber, the wafer structure is annealed, and the resistivity of the doped portions of the multiple wafer units of the wafer structure is tested. The temperatures corresponding to the multiple wafer units are obtained based on the obtained resistivity and the preset relationship between the resistivity and the annealing temperature, thereby obtaining the temperature distribution of the surface of the wafer structure and the reaction chamber of the epitaxial growth device. Since the resistivity of the doped portion is not detected inside the reaction chamber, impurities will not be introduced into the reaction chamber. The bottom of the above-mentioned groove is deeper than the first surface of the wafer structure, which makes it more difficult for the gas used in the epitaxial growth device to remove impurities on the surface of the wafer structure to diffuse to the bottom of the groove, so that the doped portion and the gas basically do not react, ensuring the integrity of the doped portion, and then the resistivity test of the doped portion can be smoothly performed. The wafer structure for temperature measurement in the present application solves the problem of detecting the temperature distribution of the reaction chamber and the wafer surface without introducing impurities.

[0076] 2) The wafer structure of the present application is used to establish a preset relationship between resistivity and annealing temperature, which can make the subsequent adjustment of the epitaxial growth equipment more accurate.

[0077] 3) In the present method for calibrating annealing parameters for epitaxial growth equipment, resistivity measurements of the doped portions of multiple wafer units, combined with a pre-defined relationship, can reflect the temperature of various regions on the surface of the wafer structure, directly reflecting the actual temperature distribution within the reaction chamber and on the surface of the wafer structure. Based on this actual temperature distribution, the annealing temperature of regions within the reaction chamber that exceed or fall below the target temperature can be regulated, thereby ensuring uniform annealing temperature across all regions of the reaction chamber.

[0078] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A wafer structure for temperature measurement, comprising a plurality of wafer units arranged in an array, characterized in that: The wafer unit includes a plurality of grooves, which are respectively a first groove, a second groove and a third groove, each of the grooves including a main body and a doping part, the main body having a groove, and the doping part being located on the bottom surface of the main body; the first groove is located in the central area of ​​the wafer unit, and a plurality of second grooves are sequentially and spaced apart around the periphery of the first groove in a direction away from the first groove; the third groove connects the first groove and the plurality of second grooves so that the doping part of the first groove contacts the doping part of the second groove, and the aspect ratio of the groove is greater than 2; the wafer structure also includes a conductive layer, which contacts the doping part, and part of the conductive layer is located on the first surface of the wafer unit.

2. The wafer structure for temperature measurement according to claim 1, wherein: The wafer structure further includes a fourth trench connecting the first trench and the second trench, and a depth-to-width ratio of the fourth trench is greater than a depth-to-width ratio of the third trench.

3. The wafer structure for temperature measurement according to claim 1, wherein: In a direction away from the first groove, intervals between adjacent second grooves increase.

4. The wafer structure for temperature measurement according to claim 1, wherein: The doping elements of the doping part include any one or more of P, N, Al, Li, Ga, Be and Ge.

5. The wafer structure for temperature measurement according to claim 1, wherein: The minimum distance between the second groove farthest from the first groove and the first groove is greater than or equal to 0.5 mm.

6. A method for calibrating annealing parameters of epitaxial growth equipment, characterized in that: The correction method comprises: Annealing the wafer structure, wherein the wafer structure is the wafer structure for temperature measurement according to any one of claims 1 to 5; After the annealing treatment, a plurality of wafer units are selected from the wafer structure, and the wafer units are tested using a testing device to obtain a plurality of resistivities of the plurality of wafer units; Based on the preset relationship and the resistivity, multiple actual temperatures of the multiple wafer units are determined, wherein the preset relationship is the relationship between the resistivity and the temperature of the annealing treatment, and based on the target temperature of the annealing treatment and the multiple actual temperatures, the annealing parameters of each area of ​​the epitaxial growth equipment are adjusted so that the multiple actual temperatures of the multiple wafer units after the annealing treatment all reach the target temperature.

7. The calibration method according to claim 6, wherein: The step of obtaining the preset relationship includes: performing the annealing process with different temperatures on a plurality of the wafer structures; After the annealing treatment, a plurality of the wafer units are selected from each of the wafer structures, and the plurality of wafer units are tested using the testing equipment to obtain the resistivity of the plurality of wafer units; The preset relationship between the temperature and the resistivity is obtained according to the temperature of the annealing treatment and the resistivity.

8. The calibration method according to claim 6, wherein: The step of using a detection device to detect the wafer units to obtain the resistivity of a plurality of the wafer units includes: Using a contact resistance tester to test the wafer unit to obtain the sheet resistance of the doped portion of the wafer unit; The resistivity of the wafer unit is obtained according to the sheet resistance and the length of the detection line used by the contact resistance testing equipment.

9. The calibration method according to claim 6, wherein: The step of using a detection device to detect the wafer units to obtain the resistivity of a plurality of the wafer units includes: The wafer unit is tested using a single-column dielectric resonant cavity to obtain the resistivity of the wafer unit.

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