A high-power, low-stray SiC MOSFET module

Abstract

The present invention discloses a high-power, low-stray SiC MOSFET module, comprising a bottom ceramic substrate, a top ceramic substrate, and a plurality of bridge arms, each comprising a first SiC MOSFET chip and a second SiC MOSFET chip. The first and second SiC MOSFET chips in odd-numbered bridge arms are symmetrically arranged on the bottom ceramic substrate, with the corresponding DC+ copper-clad area, gate copper-clad area, and source copper-clad area also arranged on the bottom ceramic substrate. The first and second SiC MOSFET chips in even-numbered bridge arms are symmetrically arranged on the top ceramic substrate, with the corresponding DC+ copper-clad area, gate copper-clad area, and source copper-clad area also arranged on the top ceramic substrate. The present invention utilizes the mutual coupling relationship between the inductances of the branches to reduce the parasitic inductance of each branch.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor packaging, and in particular relates to a high-power, low-stray SiC MOSFET module. Background Art

[0002] Wide-bandgap semiconductor power devices, such as silicon carbide (SiC) MOSFETs, offer advantages such as high-frequency switching, high-temperature operation, and low losses. They are gradually replacing Si IGBTs and are widely used in electric traction, photovoltaic power generation, and smart grids. In high-power applications, the demand for high-capacity power modules is increasing, requiring the use of multiple SiC MOSFET chips in parallel. Lower capacitance allows SiC MOSFETs to achieve higher switching speeds, making them sensitive to package parasitic inductance. High parasitic inductance can lead to increased voltage peaks between devices during switching transients, reducing system efficiency and causing electromagnetic interference issues. When the power loop design within a multi-chip power module is asymmetrical, the parasitic inductance of the parallel-connected chips may vary, resulting in current imbalance between the chips. This phenomenon is even more severe because SiC devices have significantly faster switching speeds than Si IGBTs. Chips subjected to high currents will experience greater switching losses, leading to higher junction temperatures and stagnation.

[0003] Therefore, for parallel multi-chip SiC MOSFET modules, low loop inductance and balanced parasitic inductance of parallel branches are crucial issues, which help to fully utilize the high switching speed advantages of SiC power devices. Summary of the Invention

[0004] The object of the present invention is to provide a high-power, low-stray SiC MOSFET module to solve the problem of current imbalance between chips caused by module stray and parasitic inductance.

[0005] The present invention solves the above technical problems through the following technical solutions: a high-power, low-stray SiC MOSFET module, comprising a bottom ceramic substrate, a top ceramic substrate, and a first SiC MOSFET chip and a second SiC MOSFET chip for a plurality of bridge arms; the first SiC MOSFET chip for each bridge arm is the power chip for its upper bridge arm, and the second SiC MOSFET chip for each bridge arm is the power chip for its lower bridge arm;

[0006] Each first SiC MOSFET chip corresponds to a group of DC+ copper clad area, gate copper clad area, source copper clad area, DC+ wiring terminal, gate wiring terminal and source wiring terminal, the drain of the first SiC MOSFET chip is connected to the corresponding DC+ copper clad area, its gate is connected to the corresponding gate copper clad area, and its source is connected to the corresponding source copper clad area, and the DC+ wiring terminal, gate wiring terminal and source wiring terminal are respectively provided on the corresponding DC+ copper clad area, gate copper clad area and source copper clad area;

[0007] Each second SiC MOSFET chip corresponds to a group of DC-copper clad area, gate copper clad area, source copper clad area, DC-connecting terminal, gate connecting terminal and source connecting terminal. The gate of the second SiC MOSFET chip is connected to the corresponding gate copper clad area, and the source thereof is connected to the corresponding source copper clad area and DC-copper clad area. The DC-connecting terminal, gate connecting terminal and source connecting terminal are respectively provided on the corresponding DC-copper clad area, gate copper clad area and source copper clad area.

[0008] For each bridge arm numbered sequentially, the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm numbered with an odd number are symmetrically arranged on the bottom ceramic substrate, and the DC+ copper clad area, the gate copper clad area, and the source copper clad area corresponding to the first SiC MOSFET chip, and the gate copper clad area and the source copper clad area corresponding to the second SiC MOSFET chip are arranged on the bottom ceramic substrate; the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm numbered with an even number are symmetrically arranged on the top ceramic substrate, and the DC+ copper clad area, the gate copper clad area, and the source copper clad area corresponding to the first SiC MOSFET chip, and the gate copper clad area and the source copper clad area corresponding to the second SiC MOSFET chip are arranged on the top ceramic substrate; the (i+1)th bridge arm is located between the (i+2)th bridge arm;

[0009] A first AC copper clad area is provided on the bottom ceramic substrate, and a first AC terminal is provided on the first AC copper clad area; a second AC copper clad area is provided on the top ceramic substrate, and a second AC terminal is provided on the second AC copper clad area; the source of the first SiC MOSFET chip of the odd-numbered bridge arm is also connected to the second AC copper clad area, and the drain of the second SiC MOSFET chip of the odd-numbered bridge arm is also connected to the first AC copper clad area; the source of the first SiC MOSFET chip of the even-numbered bridge arm is also connected to the first AC copper clad area, and the drain of the second SiC MOSFET chip of the even-numbered bridge arm is also connected to the second AC copper clad area; the DC-copper clad area corresponding to the second SiC MOSFET chip of the odd-numbered bridge arm is provided on the top ceramic substrate, and the DC-copper clad area corresponding to the second SiC MOSFET chip of the even-numbered bridge arm is provided on the bottom ceramic substrate;

[0010] All DC+ copper clad areas are connected together, all DC- copper clad areas are connected together, and the first AC copper clad area is connected to the second AC copper clad area.

[0011] First, the present invention optimizes the multi-dimensional packaging structure of the module's internal layout, thereby improving the electromagnetic distribution of each SiCMOSFET chip, thereby suppressing the module's parasitic effects and curbing the influence of spatial distribution parameters on the SiC MOSFET's high-speed switching performance. Second, in order to address the problem of uneven on-current distribution in parallel SiC MOSFET chips caused by inconsistent internal parasitic resistance and inductance parameters of parallel SiC MOSFET chips, the present invention achieves balanced on-current distribution in parallel SiC MOSFET chips by adjusting the copper cladding area layout.

[0012] Furthermore, the drain of each first SiC MOSFET chip is fixedly connected to the corresponding DC+ copper clad area by welding or sintering; the source of each first SiC MOSFET chip is fixedly connected to the corresponding first AC copper clad area or the second AC copper clad area by welding or sintering;

[0013] The gate of each first SiC MOSFET chip is connected to the corresponding gate copper clad area through a metal bonding wire, and the source of each first SiC MOSFET chip is connected to the corresponding source copper clad area through a metal bonding wire.

[0014] Furthermore, the drain of each second SiC MOSFET chip is fixedly connected to the corresponding first AC copper clad area or the second AC copper clad area by welding or sintering; the source of each second SiC MOSFET chip is fixedly connected to the corresponding DC-copper clad area by welding or sintering;

[0015] The gate of each second SiC MOSFET chip is connected to the corresponding gate copper clad area through a metal bonding wire, and the source of each second SiC MOSFET chip is connected to the corresponding source copper clad area through a metal bonding wire.

[0016] Furthermore, the DC+ terminal is welded to the corresponding DC+ copper clad area, the DC- terminal is welded to the corresponding DC- copper clad area, the gate terminal is welded to the corresponding gate copper clad area, the source terminal is welded to the corresponding source copper clad area, the first AC terminal is welded to the first AC copper clad area, and the second AC terminal is welded to the second AC copper clad area.

[0017] Furthermore, all DC+ copper clad areas are connected together through a molybdenum sheet, all DC- copper clad areas are connected together through a molybdenum sheet, and the first AC copper clad area is connected to the second AC copper clad area through a molybdenum sheet.

[0018] Furthermore, the drain of the first SiC MOSFET chip is provided on the lower surface of the first SiC MOSFET chip, and the gate and source are provided on the upper surface of the first SiC MOSFET chip;

[0019] The drain of the second SiC MOSFET chip is arranged on the lower surface of the second SiC MOSFET chip, and the gate and source are arranged on the upper surface of the second SiC MOSFET chip.

[0020] Furthermore, the bottom ceramic substrate and the top ceramic substrate are both DBC ceramic substrates.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The SiC MOSFET module of the present invention adopts a double-layer structure. The power loop starts from the DC+ terminal, is led to the SiC MOSFET chip of the upper bridge arm (i.e., the first SiC MOSFET chip) through the DC+ copper clad area, is then led to the SiC MOSFET chip of the lower bridge arm (i.e., the second SiC MOSFET chip) and the DC- copper clad area through the AC copper clad area, and finally reaches the DC- terminal. This achieves multi-dimensional interleaving of power loops between SiC MOSFET chips and reduces loop inductance. Because the current directions of the branches containing adjacent parallel SiC MOSFET chips are opposite, the mutual coupling relationship of the inductances between the branches is utilized to reduce the parasitic inductance of each branch and improve the current imbalance problem.

[0023] The SiC MOSFET module of the present invention has a double-sided heat dissipation capability, improves the power density of the module, and has the advantages of compact space and simple assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 1 is a circuit schematic diagram of a high-power, low-stray SiC MOSFET module according to an embodiment of the present invention;

[0026] Figure 2 1 is a package structure diagram of a high-power, low-stray SiC MOSFET module according to an embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of the layout of the bottom ceramic substrate in an embodiment of the present invention;

[0028] Figure 4 FIG. 4 is a schematic diagram of the layout of the top ceramic substrate in an embodiment of the present invention.

[0029] Explanation of the reference numerals: 1-bottom ceramic substrate, 2-top ceramic substrate, 3-first AC copper clad area, 4-first DC+ copper clad area, 5-G1 copper clad area, 6-S1 copper clad area, 7-G4 copper clad area, 8-S4 copper clad area, 9-third DC+ copper clad area, 10-G3 copper clad area, 11-S3 copper clad area, 12-G6 copper clad area, 13-S6 copper clad area, 14-second DC-copper clad area, 15-first DC+ wiring terminal, 16-G1 wiring terminal, 17-G4 wiring terminal, 18-S4 wiring terminal, 19-third DC+ wiring terminal, 20-G3 wiring terminal, 21-S3 wiring terminal, 22 -G6 terminal, 23-S6 terminal, 24-second DC- terminal, 25-first AC terminal, 26-S1 terminal, 27-second AC copper clad area, 28-second DC+ copper clad area, 29-S2 copper clad area, 30-G2 copper clad area, 31-first DC- copper clad area, 32-S5 copper clad area, 33-G5 copper clad area, 34-third DC- copper clad area, 35-third DC- terminal, 36-S2 terminal, 37-G2 terminal, 38-second DC+ terminal, 39-first DC- terminal, 40-S5 terminal, 41-G5 terminal. DETAILED DESCRIPTION

[0030] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of protection of the present invention.

[0031] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0032] like Figure 1 As shown, the high-power, low-stray SiC MOSFET module of this embodiment includes three bridge arms, each consisting of two SiC MOSFET chips connected in series. The three bridge arms are numbered sequentially: the first bridge arm includes SiC MOSFET chip Q1 and SiC MOSFET chip Q4; the second bridge arm includes SiC MOSFET chip Q2 and SiC MOSFET chip Q5; and the third bridge arm includes SiC MOSFET chip Q3 and SiC MOSFET chip Q6. SiC MOSFET chip Q1, SiC MOSFET chip Q2, and SiC MOSFET chip Q3 are the power chips of the upper bridge arm, i.e., the first SiC MOSFET chip corresponding to the bridge arm; SiC MOSFET chip Q4, SiC MOSFET chip Q5, and SiC MOSFET chip Q6 are the power chips of the lower bridge arm, i.e., the second SiC MOSFET chip corresponding to the bridge arm.

[0033] like Figures 2 to 4 As shown, the high-power low-stray SiC MOSFET module provided by the present invention includes a bottom ceramic substrate 1, a top ceramic substrate 2, a SiC MOSFET chip Q1, a SiC MOSFET chip Q4, a SiC MOSFET chip Q2, a SiC MOSFET chip Q5, a SiC MOSFET chip Q3 and a SiC MOSFET chip Q6.

[0034] The SiC MOSFET chip Q1 has a gate and source on its top surface and a drain on its bottom surface. The SiC MOSFET chip Q1 corresponds to the first DC+ copper region 4, the G1 copper region 5 (i.e., the gate copper region), the S1 copper region 6 (i.e., the source copper region), the first DC+ terminal 15, the G1 terminal 16 (i.e., the gate terminal), and the S1 terminal 26 (i.e., the source terminal). The drain of the SiC MOSFET chip Q1 is connected to the first DC+ copper region 4, its gate is connected to the G1 copper region 5, and its source is connected to the S1 copper region 6. The first DC+ terminal 15, G1 terminal 16, and S1 terminal 26 are located on the first DC+ copper region 4, the G1 copper region 5, and the S1 copper region 6, respectively.

[0035] The SiC MOSFET chip Q2 has a gate and source on its top surface and a drain on its bottom surface. The SiC MOSFET chip Q2 corresponds to the second DC+ copper clad area 28, the G2 copper clad area 30, the S2 copper clad area 29, the second DC+ terminal 38, the G2 terminal 37, and the S2 terminal 36. The drain of the SiC MOSFET chip Q2 is connected to the second DC+ copper clad area 28, its gate is connected to the G2 copper clad area 30, and its source is connected to the S2 copper clad area 29. The second DC+ terminal 38, the G2 terminal 37, and the S2 terminal 36 are respectively located on the second DC+ copper clad area 28, the G2 copper clad area 30, and the S2 copper clad area 29.

[0036] The SiC MOSFET chip Q3 has a gate and source on its top surface, and a drain on its bottom surface. SiC MOSFET chip Q3 corresponds to the third DC+ copper region 9, the G3 copper region 10, the S3 copper region 11, the third DC+ terminal 19, the G3 terminal 20, and the S3 terminal 21. The drain of SiC MOSFET chip Q3 is connected to the third DC+ copper region 9, its gate is connected to the G3 copper region 10, and its source is connected to the S3 copper region 11. The third DC+ terminal 19, the G3 terminal 20, and the S3 terminal 21 are located on the third DC+ copper region 9, the G3 copper region 10, and the S3 copper region 11, respectively.

[0037] The SiC MOSFET chip Q4 has a gate and source electrode on its top surface and a drain electrode on its bottom surface. The SiC MOSFET chip Q4 corresponds to the first DC-copper clad area 31, the G4 copper clad area 7, the S4 copper clad area 8, the first DC-connecting terminal 39, the G4 connecting terminal 17, and the S4 connecting terminal 18. The gate of the SiC MOSFET chip Q4 is connected to the G4 copper clad area 7, and its source is connected to the S4 copper clad area 8 and the first DC-copper clad area 31. The first DC-connecting terminal 39, the G4 connecting terminal 17, and the S4 connecting terminal 18 are respectively located on the first DC-copper clad area 31, the G4 copper clad area 7, and the S4 copper clad area 8.

[0038] The SiC MOSFET chip Q5 has a gate and source electrode on its top surface and a drain electrode on its bottom surface. The SiC MOSFET chip Q5 corresponds to the second DC-copper clad area 14, the G5 copper clad area 33, the S5 copper clad area 32, the second DC-connecting terminal 24, the G5 connecting terminal 41, and the S5 connecting terminal 40. The gate of the SiC MOSFET chip Q5 is connected to the G5 copper clad area 33, and its source is connected to the S5 copper clad area 32 and the second DC-copper clad area 14. The second DC-connecting terminal 24, the G5 connecting terminal 41, and the S5 connecting terminal 40 are respectively located on the second DC-copper clad area 14, the G5 copper clad area 33, and the S5 copper clad area 32.

[0039] The SiC MOSFET chip Q6 has a gate and source electrode on its top surface and a drain electrode on its bottom surface. SiC MOSFET chip Q6 corresponds to the third DC-copper clad area 34, the G6 copper clad area 12, the S6 copper clad area 13, the third DC-connecting terminal 35, the G6 connecting terminal 22, and the S6 connecting terminal 23. The gate of SiC MOSFET chip Q6 is connected to the G6 copper clad area 12, and its source is connected to the S6 copper clad area 13 and the third DC-copper clad area 34. The third DC-connecting terminal 35, the G6 connecting terminal 22, and the S6 connecting terminal 23 are respectively located on the third DC-copper clad area 34, the G6 copper clad area 12, and the S6 copper clad area 13.

[0040] like Figure 3 As shown, the SiC MOSFET chip Q1 and SiC MOSFET chip Q4 of the first bridge arm are symmetrically arranged on the bottom ceramic substrate 1, and the first DC+ copper clad area 4, G1 copper clad area 5, S1 copper clad area 6, G4 copper clad area 7, and S4 copper clad area 8 are also arranged on the bottom ceramic substrate 1. The SiC MOSFET chip Q3 and SiC MOSFET chip Q6 of the third bridge arm are symmetrically arranged on the bottom ceramic substrate 1, and the third DC+ copper clad area 9, G3 copper clad area 10, S3 copper clad area 11, G6 copper clad area 12, and S6 copper clad area 13 are also arranged on the bottom ceramic substrate 1.

[0041] like Figure 4 As shown, the SiC MOSFET chip Q2 and the SiC MOSFET chip Q5 of the second bridge arm are symmetrically arranged on the top ceramic substrate 2, and the second DC+ copper clad area 28, the G2 copper clad area 30, the S2 copper clad area 29, the G5 copper clad area 33, and the S5 copper clad area 32 are arranged on the top ceramic substrate 2.

[0042] like Figure 3 and Figure 4 As shown, the second bridge arm is located between the first bridge arm and the third bridge arm.

[0043] like Figure 3As shown, a first AC copper clad area 3 is provided on the bottom ceramic substrate 1, and a first AC connection terminal 25 is provided on the first AC copper clad area 3. Figure 4 As shown, a second AC copper clad area 27 is provided on the top ceramic substrate 2, and a second AC terminal is provided on the second AC copper clad area 27. The sources of SiC MOSFET chips Q1 and Q3 are also connected to the second AC copper clad area 27. The drains of SiC MOSFET chips Q4 and Q6 are also connected to the first AC copper clad area 3. The source of SiC MOSFET chip Q2 is connected to the first AC copper clad area 3, and the drain of SiC MOSFET chip Q5 is connected to the second AC copper clad area 27. The first DC copper clad area 31 and the third DC copper clad area 34 are provided on the top ceramic substrate 2, and the second DC copper clad area 14 is provided on the bottom ceramic substrate 1.

[0044] The first DC+ copper clad area 4, the second DC+ copper clad area 28 and the third DC+ copper clad area 9 are connected together to realize the parallel connection of SiC MOSFET chip Q1, SiC MOSFET chip Q2 and SiC MOSFET chip Q3, forming the upper bridge arm of the half-bridge circuit; the first DC- copper clad area 31, the second DC- copper clad area 14 and the third DC- copper clad area 34 are connected together to realize the parallel connection of SiC MOSFET chip Q4, SiC MOSFET chip Q5 and SiC MOSFET chip Q6, forming the lower bridge arm of the half-bridge circuit; the first AC copper clad area 3 is connected to the second AC copper clad area 27 to realize the series connection of the upper bridge arm and the lower bridge arm.

[0045] In a SiC MOSFET module, the power loop originates from the DC+ terminal, passes through the DC+ copper clad area to the SiC MOSFET chip in the upper bridge arm, then passes through the AC copper clad area to the SiC MOSFET chip and DC- copper clad area in the lower bridge arm, and finally reaches the DC- terminal. From the perspective of parasitic inductance, the double-layer three-dimensional packaging structure composed of the bottom ceramic substrate 1 and the top ceramic substrate 2 enables the power loop of the entire module to overlap, achieving multi-dimensional interleaving of power loops between SiC MOSFET chips and reducing loop inductance. Because the current directions of the branches containing adjacent parallel SiC MOSFET chips are opposite, the mutual coupling relationship between the inductances of the branches is utilized to reduce the parasitic inductance of each branch, thereby improving the current imbalance problem.

[0046] Compared with traditional packaging structures, the present invention improves the electromagnetic distribution of each SiC MOSFET chip by optimizing the internal layout of the module in multiple dimensions, thereby suppressing the module parasitic effects and curbing the impact of spatial distribution parameters on the high-speed switching performance of SiC MOSFET. Secondly, for the problem of uneven on-current distribution of parallel SiC MOSFET chips caused by inconsistent internal parasitic resistance and inductance parameters of parallel SiC MOSFET chips, the present invention achieves balanced on-current distribution of parallel SiC MOSFET chips by adjusting the layout of the copper cladding area. The packaging structure provided by the present invention can achieve better performance at a lower cost, has double-sided heat dissipation capabilities, improves the power density of the module, and has the characteristics of compact space and simple assembly.

[0047] In a specific embodiment of the present invention, the drain of the SiC MOSFET chip Q1 is fixedly connected to the first DC+ copper clad area 4 by welding or sintering, and the source of the SiC MOSFET chip Q1 is fixedly connected to the second AC copper clad area 27 by welding or sintering; the gate of the SiC MOSFET chip Q1 is connected to the G1 copper clad area 5 by a metal bonding wire, and the source of the SiC MOSFET chip Q1 is connected to the S1 copper clad area 6 by a metal bonding wire.

[0048] The drain of the SiC MOSFET chip Q2 is fixedly connected to the second DC+ copper clad area 28 by welding or sintering, and the source of the SiC MOSFET chip Q2 is fixedly connected to the first AC copper clad area 3 by welding or sintering; the gate of the SiC MOSFET chip Q2 is connected to the G2 copper clad area 30 by a metal bonding wire, and the source of the SiC MOSFET chip Q2 is connected to the S2 copper clad area 29 by a metal bonding wire.

[0049] The drain of the SiC MOSFET chip Q3 is fixedly connected to the third DC+ copper clad area 9 by welding or sintering, and the source of the SiC MOSFET chip Q3 is fixedly connected to the second AC copper clad area 27 by welding or sintering; the gate of the SiC MOSFET chip Q3 is connected to the G3 copper clad area 10 by a metal bonding wire, and the source of the SiC MOSFET chip Q3 is connected to the S3 copper clad area 11 by a metal bonding wire.

[0050] The drain of the SiC MOSFET chip Q4 is fixedly connected to the first AC copper clad area 3 by welding or sintering, and the source of the SiC MOSFET chip Q4 is fixedly connected to the first DC-copper clad area 31 by welding or sintering; the gate of the SiC MOSFET chip Q4 is connected to the G4 copper clad area 7 by a metal bonding wire, and the source of the SiC MOSFET chip Q4 is connected to the S4 copper clad area 8 by a metal bonding wire.

[0051] The drain of the SiC MOSFET chip Q5 is fixedly connected to the second AC copper clad area 27 by welding or sintering, and the source of the SiC MOSFET chip Q5 is fixedly connected to the second DC-copper clad area 14 by welding or sintering; the gate of the SiC MOSFET chip Q5 is connected to the G5 copper clad area 33 by a metal bonding wire, and the source of the SiC MOSFET chip Q5 is connected to the S5 copper clad area 32 by a metal bonding wire.

[0052] The drain of the SiC MOSFET chip Q6 is fixedly connected to the first AC copper clad area 3 by welding or sintering, and the source of the SiC MOSFET chip Q6 is fixedly connected to the third DC-copper clad area 34 by welding or sintering; the gate of the SiC MOSFET chip Q6 is connected to the G6 copper clad area 12 by a metal bonding wire, and the source of the SiC MOSFET chip Q6 is connected to the S6 copper clad area 13 by a metal bonding wire.

[0053] In a specific embodiment of the present invention, the first DC+ terminal 15 is welded to the first DC+ copper clad area 4 , the second DC+ terminal 38 is welded to the second DC+ copper clad area 28 , and the third DC+ terminal 19 is welded to the third DC+ copper clad area 9 .

[0054] The first DC-connecting terminal 39 is soldered to the first DC-copper cladding area 31 , the second DC-connecting terminal 24 is soldered to the second DC-copper cladding area 14 , and the third DC-connecting terminal 35 is soldered to the third DC-copper cladding area 34 .

[0055] G1 terminal 16 is soldered to G1 copper clad area 5, S1 terminal 26 is soldered to S1 copper clad area 6; G2 terminal 37 is soldered to G2 copper clad area 30, S2 terminal 36 is soldered to S2 copper clad area 29; G3 terminal 20 is soldered to G3 copper clad area 10, S3 terminal 21 is soldered to S3 copper clad area 11; G4 terminal 17 is soldered to G4 copper clad area 7, S4 terminal 18 is soldered to S4 copper clad area 8; G5 terminal 41 is soldered to G5 copper clad area 33, S5 terminal 40 is soldered to S5 copper clad area 32; G6 terminal 22 is soldered to G6 copper clad area 12, S6 terminal 23 is soldered to S6 copper clad area 13.

[0056] The first AC terminal 25 is soldered to the first AC copper clad area 3 , and the second AC terminal is soldered to the second AC copper clad area 27 .

[0057] In a specific embodiment of the present invention, the first DC+ copper clad area 4, the second DC+ copper clad area 28 and the third DC+ copper clad area 9 are connected together through a molybdenum sheet; the first DC- copper clad area 31, the second DC- copper clad area 14 and the third DC- copper clad area 34 are connected together through a molybdenum sheet; the first AC copper clad area 3 and the second AC copper clad area 27 are connected through a molybdenum sheet.

[0058] In a specific embodiment of the present invention, both the bottom ceramic substrate 1 and the top ceramic substrate 2 are DBC ceramic substrates.

[0059] For a high-power, low-stray SiC MOSFET module with four bridge arms, the two SiC MOSFET chips of the first and third bridge arms are symmetrically arranged on the bottom ceramic substrate, and the two SiC MOSFET chips of the second and fourth bridge arms are symmetrically arranged on the top ceramic substrate. The second bridge arm is located between the first and third bridge arms, and the third bridge arm is located between the second and fourth bridge arms.

[0060] The above disclosure is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, and they should all be covered by the scope of protection of the present invention.

Claims

1. A high-power, low-stray SiC MOSFET module, characterized by: The module includes a bottom ceramic substrate, a top ceramic substrate, and a first SiC MOSFET chip and a second SiC MOSFET chip for a plurality of bridge arms; the first SiC MOSFET chip for each bridge arm is a power chip for its upper bridge arm, and the second SiC MOSFET chip for each bridge arm is a power chip for its lower bridge arm; Each first SiC MOSFET chip corresponds to a group of DC+ copper clad area, gate copper clad area, source copper clad area, DC+ wiring terminal, gate wiring terminal and source wiring terminal, the drain of the first SiC MOSFET chip is connected to the corresponding DC+ copper clad area, its gate is connected to the corresponding gate copper clad area, and its source is connected to the corresponding source copper clad area, and the DC+ wiring terminal, gate wiring terminal and source wiring terminal are respectively provided on the corresponding DC+ copper clad area, gate copper clad area and source copper clad area; Each second SiC MOSFET chip corresponds to a group of DC-copper clad area, gate copper clad area, source copper clad area, DC-connecting terminal, gate connecting terminal and source connecting terminal. The gate of the second SiC MOSFET chip is connected to the corresponding gate copper clad area, and the source thereof is connected to the corresponding source copper clad area and DC-copper clad area. The DC-connecting terminal, gate connecting terminal and source connecting terminal are respectively provided on the corresponding DC-copper clad area, gate copper clad area and source copper clad area. For each bridge arm numbered sequentially, the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm numbered with an odd number are symmetrically arranged on the bottom ceramic substrate, and the DC+ copper clad area, the gate copper clad area, and the source copper clad area corresponding to the first SiC MOSFET chip, and the gate copper clad area and the source copper clad area corresponding to the second SiC MOSFET chip are arranged on the bottom ceramic substrate; the first SiC MOSFET chip and the second SiC MOSFET chip of the bridge arm numbered with an even number are symmetrically arranged on the top ceramic substrate, and the DC+ copper clad area, the gate copper clad area, and the source copper clad area corresponding to the first SiC MOSFET chip, and the gate copper clad area and the source copper clad area corresponding to the second SiC MOSFET chip are arranged on the top ceramic substrate; the (i+1)th bridge arm is located between the (i+2)th bridge arm; A first AC copper clad area is provided on the bottom ceramic substrate, and a first AC terminal is provided on the first AC copper clad area; a second AC copper clad area is provided on the top ceramic substrate, and a second AC terminal is provided on the second AC copper clad area; the source of the first SiC MOSFET chip of the odd-numbered bridge arm is also connected to the second AC copper clad area, and the drain of the second SiC MOSFET chip of the odd-numbered bridge arm is also connected to the first AC copper clad area; the source of the first SiC MOSFET chip of the even-numbered bridge arm is also connected to the first AC copper clad area, and the drain of the second SiC MOSFET chip of the even-numbered bridge arm is also connected to the second AC copper clad area; the DC-copper clad area corresponding to the second SiC MOSFET chip of the odd-numbered bridge arm is provided on the top ceramic substrate, and the DC-copper clad area corresponding to the second SiC MOSFET chip of the even-numbered bridge arm is provided on the bottom ceramic substrate; All DC+ copper clad areas are connected together, all DC- copper clad areas are connected together, and the first AC copper clad area is connected to the second AC copper clad area.

2. The high-power, low-stray SiC MOSFET module according to claim 1, characterized in that: The drain of each first SiC MOSFET chip is fixedly connected to the corresponding DC+ copper clad area by welding or sintering; the source of each first SiC MOSFET chip is fixedly connected to the corresponding first AC copper clad area or second AC copper clad area by welding or sintering; The gate of each first SiC MOSFET chip is connected to the corresponding gate copper clad area through a metal bonding wire, and the source of each first SiC MOSFET chip is connected to the corresponding source copper clad area through a metal bonding wire.

3. The high-power, low-stray SiC MOSFET module according to claim 1, characterized in that: The drain of each second SiC MOSFET chip is fixedly connected to the corresponding first AC copper clad area or the second AC copper clad area by welding or sintering; the source of each second SiC MOSFET chip is fixedly connected to the corresponding DC-copper clad area by welding or sintering; The gate of each second SiC MOSFET chip is connected to the corresponding gate copper clad area through a metal bonding wire, and the source of each second SiC MOSFET chip is connected to the corresponding source copper clad area through a metal bonding wire.

4. The high-power, low-stray SiC MOSFET module according to claim 1, characterized in that: The DC+ terminal is welded to the corresponding DC+ copper clad area, the DC- terminal is welded to the corresponding DC- copper clad area, the gate terminal is welded to the corresponding gate copper clad area, the source terminal is welded to the corresponding source copper clad area, the first AC terminal is welded to the first AC copper clad area, and the second AC terminal is welded to the second AC copper clad area.

5. The high-power, low-stray SiC MOSFET module according to claim 1, characterized in that: All DC+ copper clad areas are connected together through molybdenum sheets, all DC- copper clad areas are connected together through molybdenum sheets, and the first AC copper clad area is connected to the second AC copper clad area through a molybdenum sheet.

6. The high-power, low-stray SiC MOSFET module according to claim 1, characterized in that: The drain of the first SiC MOSFET chip is arranged on the lower surface of the first SiC MOSFET chip, and the gate and source are arranged on the upper surface of the first SiC MOSFET chip; The drain of the second SiC MOSFET chip is arranged on the lower surface of the second SiC MOSFET chip, and the gate and source are arranged on the upper surface of the second SiC MOSFET chip.

7. The high-power, low-stray SiC MOSFET module according to any one of claims 1 to 6, characterized in that: The bottom ceramic substrate and the top ceramic substrate are both DBC ceramic substrates.

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