Charging and discharging circuit of standby power circuit and storage server

Abstract

The invention provides a charging and discharging circuit of a standby power circuit and a storage server, the charging and discharging circuit comprises a main control circuit and a power conversion circuit, and the main control circuit comprises four PWM signal output pins; the power conversion circuit comprises four MOS (Metal Oxide Semiconductor) tubes and a first inductor; the four MOS tubes comprise a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the fourth MOS tube, and the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube through a first inductor and a current sampling resistor; grid electrodes of the four MOS tubes are respectively connected with output signals of the four PWM signal output pins; according to the scheme, the circuit is simplified, the safety of the circuit is ensured, the circuit cost is reduced, and the PCB layout area is reduced; in addition, electronic components forming the circuit are all universal devices, and the material supply risk is eliminated.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to a charge-discharge circuit for a backup power circuit and a storage server. Background Art

[0002] Currently, the charge-discharge circuit of the backup power circuit of a storage server is composed of two unidirectional circuits, a forward circuit and a reverse circuit. The forward circuit is a BUCK-BOOST circuit built with an MCU and peripheral circuits such as MOS, and the PSU (Power Supply Unit) charges the BBU (Battery Backup Unit). The reverse circuit is a buck circuit built with a dual-channel buck chip and is used for the BBU to discharge reversely to supply power to the system. The above implementation scheme not only has a large number of components, reduces the reliability of the circuit operation, and increases the cost, but also the BUCK chip used for reverse discharge is an imported chip and is not a general device, so there is a great risk of out-of-stock. Summary of the Invention

[0003] The present disclosure provides a charge-discharge circuit for a backup power circuit and a storage server, which can simplify the circuit, reduce the cost, and eliminate the risk of out-of-stock.

[0004] To solve the above technical problems, the present disclosure provides a charge-discharge circuit for a backup power circuit, including: A main control circuit, the main control circuit including four PWM signal output pins; A power conversion circuit, the power conversion circuit including four MOS transistors and a first inductor. The four MOS transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, the drain of the first MOS transistor is connected to the drain of the third MOS transistor through the first inductor and a current sampling resistor. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and is grounded. The gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins.

[0005] An embodiment of the present disclosure further provides a storage server, which includes the above circuit to charge and discharge the backup power circuit of the storage server.

[0006] A charge and discharge circuit of a backup power supply circuit provided by the present disclosure includes: a main control circuit and a power conversion circuit. The main control circuit includes four PWM signal output pins; the power conversion circuit includes four MOS transistors and a first inductor. The four MOS transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor is connected to the drain of the third MOS transistor through the first inductor and a current sampling resistor; the drains of the second MOS transistor and the fourth MOS transistor are connected and both are grounded; the gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins. The power conversion circuit built by the four MOS transistors realizes a four-switch bidirectional buck-boost circuit. By controlling the working modes of the MOS transistors in the power conversion circuit through the main control circuit, the bidirectional flow of energy is realized, thereby realizing the charge and discharge circuit of the BBU. Through the analog plus digital drive protection strategy, the circuit can be simplified and the safety of the circuit is ensured, the circuit cost is reduced, and the PCB layout area is reduced; moreover, the electronic components constituting the circuit are all general components, eliminating the risk of material supply; the circuit of this solution is applicable to any product that requires battery energy storage for backup power supply.

[0007] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them: Figure 1 It is a structural block diagram of a charge and discharge circuit of a backup power supply circuit provided by an embodiment of the present disclosure; Figure 2 It is a circuit schematic diagram of a main control circuit provided by an embodiment of the present disclosure; Figure 3 It is a circuit schematic diagram of a power conversion circuit provided by an embodiment of the present disclosure; Figure 4 It is a schematic flow diagram of charge and discharge switching provided by an embodiment of the present disclosure; Figure 5 It is a circuit schematic diagram of a current sampling and protection circuit provided by an embodiment of the present disclosure; Figure 6 It is a circuit schematic diagram of a reference voltage circuit provided by an embodiment of the present disclosure; Figure 7 It is a circuit schematic diagram of a drive circuit provided by an embodiment of the present disclosure; Figure 8The circuit schematic diagram of a voltage sampling circuit provided by an embodiment of the present disclosure; Figure 9 The circuit schematic diagram of a working power supply circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0009] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist in understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted below for clarity and conciseness.

[0010] Term explanations: MCU, Micro Control Unit, microcontroller; MOS, Metal Oxide Semiconductor, metal oxide semiconductor; PSU, Power Supply Unit, power supply unit; BBU, Battery Backup Unit, battery backup unit; PWM, Pulse-width modulation, pulse width modulation; BUCK-BOOST, buck-boost; LED, Light-Emitting Diode, light-emitting diode; PCB (Printed Circuit Board), printed circuit board, also known as printed wiring board.

[0011] The charge and discharge circuit and storage server of the backup power supply circuit of the embodiment of the present disclosure are described below with reference to the accompanying drawings.

[0012] In the first aspect of the embodiments of the present application, an embodiment of a charge and discharge circuit of a backup power supply circuit is proposed.

[0013] As Figure 1 shown, the charge and discharge circuit 100 of the backup power supply circuit includes a main control circuit 101 and a power conversion circuit 102. The main control circuit 101 controls the power conversion circuit 102 to charge and discharge the backup power supply circuit 103: The main control circuit 101 includes four PWM signal output pins; The power conversion circuit 102 includes four MOS transistors and a first inductor. The four MOS transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. The drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the first MOS transistor is connected to the drain of the third MOS transistor through the first inductor and a current sampling resistor. The drains of the second MOS transistor and the fourth MOS transistor are connected and both are grounded. The gates of the four MOS transistors are respectively connected to the output signals of four PWM signal output pins.

[0014] As an example, as Figure 2 shown, the main control circuit 101 includes a main control chip MCU of model STM32F446RCT6TR. The 42#, 43#, 26#, and 27# pins of the MCU output four PWM signals to control the working modes of the four MOS transistors in the power conversion circuit 102, that is, the four PWM signal output pins output two complementary PWM signals to control the four MOS transistors in the power conversion circuit, realizing bidirectional energy flow and completing the functions of charging and discharging the BBU. The main control circuit 101 also includes an 8 MHz crystal oscillator X1, a working power status indicator LED1, a main control chip working status indicator LED2, a working alarm indicator LED3, a reset button SW1, a J1 - UART interface, a J2 - IIC interface, a J4 - programming interface, etc. The main control chip U7 is the control core of the entire charge - discharge circuit and is responsible for the normal operation of the entire circuit. The 52# pin of the main control chip U7 is a fault input pin, receiving the POWER_FAULT signal. When a circuit fault signal is detected at this pin, the power output is immediately stopped. The 57# pin is the control pin of the main control chip working status indicator LED2. When the system works in the forward state, this pin controls the main control chip working status indicator LED2 to be constantly on. When the system works in the reverse state, this pin controls the main control chip working status indicator LED2 to flash at a low frequency. The 33# pin is the control pin of the working alarm indicator LED3. When the circuit is working normally, this pin controls the working alarm indicator LED3 to flash at a low frequency. When a fault occurs in the system circuit, this pin controls the working alarm indicator LED3 to flash at a high frequency. As Figure 3 shown, the four MOS transistors are respectively a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, and a fourth MOS transistor Q4. The drain of the first MOS transistor Q1 is connected to the drain of the third MOS transistor Q3 through the first inductor L1 and a resistor R82. The gates of the first MOS transistor Q1 to the fourth MOS transistor Q4 are connected to the PWM signals output by the four PWM signal output pins.

[0015] Thus, the PWM signals output from the four PWM signal output pins of the main control circuit 101 respectively control the working states of the four MOS transistors of the power conversion circuit 102 to control the energy flow direction, and complete the functions of charging and discharging the BBU.

[0016] Through the technical solution of the embodiment of the present application, the power conversion circuit 102 built by four MOS transistors realizes a four-switch bidirectional buck-boost circuit. The main control circuit 101 controls the working modes of the MOS transistors in the power conversion circuit 102 to realize the bidirectional flow of energy, thereby realizing the charging and discharging circuit of the BBU. Through the analog plus digital drive protection strategy, the circuit can be simplified and the safety of the circuit can be ensured, the circuit cost can be reduced, and the PCB layout area can be reduced. Moreover, the electronic components that make up the circuit are all common devices, eliminating the risk of material supply. The circuit of this solution is applicable to any product that requires battery energy storage and backup power.

[0017] In one embodiment, a series of a capacitor and a resistor are connected in parallel between the source and the drain of each of the four MOS transistors, and a clamping diode is connected in parallel to the gates of the four MOS transistors. As Figure 3 shown, the capacitor and the resistor connected in parallel across the drain and source of each MOS transistor are used to absorb the spike voltage when the MOS transistor switches, such as capacitor C3 and resistor R13; the clamping diode connected in parallel to the gate of each MOS transistor is to prevent the driving voltage from being too high and breaking down the MOS transistor, such as clamping diode D5.

[0018] Through the technical solution of the embodiment of the present application, by connecting a series of a capacitor and a resistor in parallel between the source and the drain of the MOS transistor, the spike voltage when the MOS transistor switches is absorbed; by connecting a clamping diode in parallel to the gate of the MOS transistor, the driving voltage is prevented from being too high and breaking down the MOS transistor, further improving the safety of the circuit.

[0019] In one embodiment, the main control circuit 101 is configured to: in response to the normal operation of the PSU, control the power conversion circuit 102 to work in the charging mode, and the main control circuit 101 works in the current discontinuous control mode; in response to the abnormal operation of the PSU, control the power conversion circuit 102 to enter the discharging mode at the beginning of the next switching cycle, and the discharging mode is the BUCK-BOOST mode. Exemplarily, as Figure 4 shown, it is detected whether a PSU fault occurs. In the case where no PSU fault occurs, the charging and discharging circuit works in the BBU charging mode, and the circuit working mode in the charging mode is the current discontinuous control mode to ensure that the current of the first inductor drops to 0A within one cycle, preparing for the current reversal; in response to the occurrence of a PSU fault, enter the BBU discharging mode in the next switching cycle, and the discharging mode is the BUCK-BOOST mode.

[0020] Through the technical solution of the embodiment of the present application, when the BBU is charging, the current discontinuous control mode is utilized to ensure that the inductor current of the power change circuit can be quickly reversed, so as to ensure the timeliness of the BBU discharging, be able to seamlessly switch the energy flow direction, that is, there is no time delay when the energy flow direction changes, enable the BBU to always be in the hot standby state, and also reduce the current impact, improving the reliability of the standby power supply switching. When the BBU is discharging, it also works in the BUCK - BOOST mode, which can either step down or step up the voltage, thus expanding the working voltage range during the BBU discharging and indirectly improving the standby power supply capacity of the BBU.

[0021] In one embodiment, the charge - discharge circuit further includes a current sampling and protection circuit. The current sampling and protection circuit includes multiple groups of operational amplifier circuits. The operational amplifier circuit includes a differential amplification circuit and a comparison circuit. The output end of the differential amplification circuit is connected to the first input end of the comparison circuit. The second input end of the comparison circuit is connected to the reference voltage terminal. The output end of the comparison circuit is connected to the fault input pin of the main control circuit 101; the input ends of multiple differential amplification circuits are respectively connected to multiple current acquisition terminals of the power conversion circuit 102; the output ends of multiple differential amplification circuits are respectively connected to multiple AD sampling pins of the main control circuit 101. As an example, as Figure 5 shown, the current sampling and protection circuit includes three groups of operational amplifier circuits. Each group of operational amplifier circuits includes a differential amplification circuit composed of an operational amplifier chip with the model number LM358A - SR and a comparison circuit composed of an operational amplifier chip with the model number LM358A - SR. The output pins of three operational amplifier chips U14.1, U15.1, and U20.1 are all connected to an input pin of the corresponding comparison circuit and an AD sampling pin of the main control circuit 101 at the same time; multiple current acquisition terminals of the power conversion circuit 102 include a PSU - end current acquisition terminal, a BBU - end current acquisition terminal, and a first inductor current acquisition terminal. One input end of three operational amplifier chips U14.1, U15.1, and U20.1 is respectively connected to the PSU - end current acquisition terminal, the BBU - end current acquisition terminal, and the first inductor current acquisition terminal; taking the circuit for collecting the current at the PSU end as an example for detailed description, PWR_D and PSU_P12V, as differential signals, pass through the differential amplification circuit composed of the operational amplifier chip U14.1 and peripheral resistors and capacitors, amplify this pair of signals by 10 times and send them to the AD sampling pin of the main control chip of the main control circuit 101. Then, through the conversion of the internal algorithm of the main control chip, the PSU current value can be obtained. The amplified signal also enters the 6# pin of U14.2 to be compared with the reference voltage of the 5# pin of U14.2. If it is greater than the voltage value of the 5# pin, the 7# pin of U14.2 outputs a low level. D17 is a clamping diode to prevent the signal voltage from being too large and breaking down the main control chip. The other two paths are the same and will not be elaborated. As Figure 3As shown, the voltage drops generated when current flows through current sampling resistors R17, R18, and R82 are collected by the current sampling and protection circuit and sent to the AD sampling pins (pins 8#, 11#, and 20#) of the main control chip to obtain the current values at corresponding positions for circuit control.

[0022] Through the technical solution of the embodiment of the present application, the three differential amplification circuits of the three operational amplifier circuits are respectively used to collect the current values of the PSU end, BBU end, and the first inductor in the power conversion circuit 102. These current values are not only used in control operations but also for overcurrent protection through a comparison circuit, improving the reliability of the circuit.

[0023] In one embodiment, the charge and discharge circuit further includes a reference voltage circuit. The reference voltage circuit includes a voltage regulator source and a second operational amplifier. The output terminal of the voltage regulator source is connected to an input pin of the second operational amplifier, and the output pin of the second operational amplifier is connected to the reference voltage terminal of the current sampling and protection circuit. As an example, as Figure 6 shown, the voltage regulator source includes a power chip with the model number TL431AIDBZR, and the second operational amplifier is composed of an operational amplifier chip U18 with the model number OPA2188AID and its peripheral circuits. The output pin DRV_UVP of the operational amplifier chip U18 outputs a stable 1.5V reference voltage for use as the reference voltage for other circuits. For example, it is used as the reference voltage for the differential amplification circuit of the current sampling and protection circuit. The current sampling and protection circuit uses 1.5V as the reference voltage, and without using a negative power supply, it realizes the sampling function of bidirectional current, simplifying the circuit.

[0024] Through the technical solution of the embodiment of the present application, a stable reference voltage is provided for the chips in the circuit, improving the reliability of the circuit.

[0025] In one embodiment, the charge and discharge circuit further includes a driving circuit 103. The driving circuit includes a first driving unit, a second driving unit, and an AND logic protection unit, where: the two input pins of the first driving unit and the two input pins of the second driving unit are respectively connected to the output signals of the four PWM signal output pins through resistors. The two output pins of the first driving unit are respectively connected to the gates of the first MOS transistor and the second MOS transistor; the two output pins of the second driving unit are respectively connected to the gates of the third MOS transistor and the fourth MOS transistor; the AND logic protection unit includes a four-way AND logic chip. The first input terminals of the four AND gates of the four-way AND logic chip are respectively connected to the PWM signals output by the four PWM signal output pins of the main control circuit 101, and the second input terminals of the four AND gates are all connected to the fault input pin of the main control circuit 101; the output terminals of the multiple comparison circuits of the current sampling and protection circuit and the output terminal of the reference voltage circuit are both connected to the fault input pin of the main control circuit 101 after being connected in series with resistors and diodes. The fault input pin is connected to an RC charging circuit composed of a resistor and a capacitor; the four output terminals of the four-way AND logic chip are respectively connected to the input pins of the first driving unit and the second driving unit.

[0026] As an example, such as Figure 7As shown in the figure, the circuit structures of the first driving unit and the second driving unit are the same, and both include a dual-channel driving chip (U9 / U10) of model SQ55664SXD. This dual-channel driving chip is used to amplify the PWM signal output by the main control circuit 101 and drive the four MOS transistors of the power conversion circuit 102. The AND gate logic protection unit includes a driving protection circuit composed of a four-channel AND gate logic chip U13 of model 74LVC08APW. When the charge and discharge circuit works normally, the four-channel AND gate logic chip U13 normally outputs the PWM signal from the main control circuit 101; when a fault occurs in the charge and discharge circuit, the four-channel AND gate logic chip U13 pulls down all output signals, causing the MOS transistors in the power conversion circuit 102 to stop working. The main function of the four-channel AND gate logic chip U13 is to timely turn off the driving signal from the main control circuit 101 when overcurrent and driving undervoltage occur, so as to protect the MOS transistors from further damage; its protection principle is: diodes D16 / D15 / D14 / D20 form an OR gate circuit. When the four signals of the multiple current sampling signals PWR_OCP, BAT_OCP, L_OCP output by the current sampling and protection circuit and the DRV_UVP output by the reference voltage circuit are all high levels, the fault input pin POWER_FAULT is at a high level, and the PWM signal from the main control circuit 101 is normally output. When any one of PWR_OCP, BAT_OCP, L_OCP, and DRV_UVP becomes a low level, the fault input pin POWER_FAULT is at a low level, then the PWM driving signal from the main control circuit 101 is locked at a low level, and at the same time, the POWER_FAULT signal will be sent to the main control circuit 101 for alarm. This protection method is to utilize the fast response speed of the analog circuit to perform protection quickly; sending the alarm signal to the main control circuit 101 is to enable the main control circuit 101 to obtain the alarm information and stop the power conversion work from the program. In addition, the resistor R58 and the capacitor C72 form an RC charging circuit. The main function of this RC charging circuit is to delay the speed of POWER_FAULT changing from low to high, so that enough reaction time can be provided for the main control circuit 101 to perform alarm and control at the software level.

[0027] Through the technical solution of the embodiment of the present application, adding an AND gate logic protection unit in the driving circuit can quickly respond to fault signals and prevent the occurrence of larger faults.

[0028] In one embodiment, the charge and discharge circuit further includes a voltage sampling circuit. The voltage sampling circuit includes a plurality of first operational amplifiers. The input ends of the plurality of first operational amplifiers are respectively connected to a plurality of voltage acquisition ends of the power conversion circuit 102 through voltage dividing resistors, and the output ends of the plurality of first operational amplifiers are respectively connected to a plurality of AD sampling pins of the main control circuit 101. As an example, Figure 8As shown in the figure, the voltage sampling circuit includes two first operational amplifiers, which are respectively used to collect the PSU terminal voltage and the BBU terminal voltage for use in control operations. Both of the two first operational amplifiers include an operational amplifier chip with the model number LM358A-SR, clamping diodes, and other resistive and capacitive components. For example, a voltage signal is obtained by dividing the voltage through resistor R62 and resistor R68 as the input of operational amplifier chip U19.1. The 2# pin and the 1# pin of U19.1 are short-circuited to form a voltage follower circuit. The signal output by operational amplifier chip U19.1 is sent to the main control circuit 101 for PSU voltage acquisition, and the actual PSU voltage value can be obtained through calculation by the main control circuit 101. The BBU voltage sampling is the same. As Figure 2 As shown in the figure, the 9# and 10# pins of the main control chip are respectively used to collect the PSU terminal voltage and the BBU terminal voltage.

[0029] Through the technical solution of the embodiment of the present application, the PSU terminal voltage and the BBU terminal voltage are collected through the above circuit for use in control operations, improving the safety of the circuit.

[0030] In one embodiment, the working power supply circuit of the charge and discharge circuit is as Figure 9 shown, and includes a power supply voltage regulator chip U11 with the model number AMS117-3.3. The working power supply circuit composed of the power supply voltage regulator chip U11 and the peripheral circuit provides 12V and 3.3V working voltages for the entire circuit, and 3.3V is mainly used to supply power to other chips.

[0031] Based on any of the above embodiments, the embodiment of the present disclosure further provides a storage server, which includes the charge and discharge circuit of any of the above embodiments to charge and discharge the backup power supply circuit of the storage server.

[0032] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present disclosure.

[0033] The above has introduced in detail a target detection method provided by the present disclosure. Specific examples are used in this article to elaborate on the principle and implementation manner of the present disclosure. The description of the above embodiments is only used to help understand the circuit and its core idea of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present disclosure, several improvements and modifications can be made to the present disclosure, and these improvements and modifications also fall within the protection scope of the claims of the present disclosure.

Claims

1. A charge and discharge circuit of a backup power supply circuit, characterized in that, The charge and discharge circuit includes: A main control circuit, the main control circuit including four PWM signal output pins; A power conversion circuit, the power conversion circuit including four MOS transistors and a first inductor, the four MOS transistors including a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; the drain of the first MOS transistor is connected to the source of the second MOS transistor, the drain of the third MOS transistor is connected to the source of the fourth MOS transistor, the drain of the first MOS transistor is connected to the drain of the third MOS transistor through the first inductor and a current sampling resistor; the drains of the second MOS transistor and the fourth MOS transistor are connected and both grounded; the gates of the four MOS transistors are respectively connected to the output signals of the four PWM signal output pins.

2. The circuit according to claim 1, wherein The main control circuit is configured to: In response to the PSU operating normally, control the power conversion circuit to operate in the charging mode, and the main control circuit to operate in the discontinuous current control mode; In response to the PSU operating abnormally, control the power conversion circuit to enter the discharge mode at the start of the next switching cycle, and the discharge mode is the BUCK-BOOST mode.

3. The circuit according to claim 1 or 2, characterized in that, The charge and discharge circuit further includes a current sampling and protection circuit, the current sampling and protection circuit including multiple operational amplifier circuits, the operational amplifier circuit including a differential amplification circuit and a comparison circuit, the output end of the differential amplification circuit is connected to the first input end of the comparison circuit, the second input end of the comparison circuit is connected to a reference voltage terminal, and the output end of the comparison circuit is connected to the fault input pin of the main control circuit; the input ends of multiple differential amplification circuits are respectively connected to multiple current acquisition terminals of the power conversion circuit; the output ends of multiple differential amplification circuits are respectively connected to multiple AD sampling pins of the main control circuit.

4. The circuit according to claim 3, characterized in that, The charge and discharge circuit further includes a reference voltage circuit, the reference voltage circuit including a voltage stabilizer and a second operational amplifier, the output end of the voltage stabilizer is connected to an input pin of the second operational amplifier, and the output pin of the second operational amplifier is connected to the reference voltage terminal of the current sampling and protection circuit.

5. The circuit according to claim 3, wherein, The multiple current acquisition terminals of the power conversion circuit include a PSU terminal current acquisition terminal, a BBU terminal current acquisition terminal, and a first inductor current acquisition terminal.

6. The circuit according to claim 4, characterized in that, The charge and discharge circuit further includes a drive circuit, the drive circuit including a first drive unit and a second drive unit, the two input pins of the first drive unit and the two input pins of the second drive unit are respectively connected to the output signals of the four PWM signal output pins through resistors, the two output pins of the first drive unit are respectively connected to the gates of the first MOS transistor and the second MOS transistor; the two output pins of the second drive unit are respectively connected to the gates of the third MOS transistor and the fourth MOS transistor.

7. The circuit according to claim 6, wherein The driving circuit further includes an AND logic protection unit, and the AND logic protection unit includes a four-way AND logic chip. The first input ends of the four AND gates of the four-way AND logic chip are respectively connected to the PWM signals output by the four PWM signal output pins of the main control circuit, and the second input ends of the four AND gates are all connected to the fault input pin of the main control circuit. The output ends of the multiple comparison circuits of the current sampling and protection circuit and the output end of the reference voltage circuit are all connected to the fault input pin of the main control circuit after being connected in series with a resistor and a diode, and the fault input pin is connected to an RC charging circuit composed of a resistor and a capacitor. The four output ends of the four-way AND logic chip are respectively connected to the input pins of the first driving unit and the second driving unit.

8. The circuit according to claim 1, characterized in that, The charge and discharge circuit further includes a voltage sampling circuit, and the voltage sampling circuit includes multiple first operational amplifiers. The input ends of the multiple first operational amplifiers are all connected to the multiple voltage acquisition ends of the power conversion circuit through voltage dividing resistors, and the output ends of the multiple first operational amplifiers are respectively connected to the multiple AD sampling pins of the main control circuit.

9. The circuit according to claim 1, characterized in that, A capacitor and a resistor connected in series are connected in parallel between the source and the drain of each of the four MOS transistors, and clamping diodes are connected in parallel to the gates of the four MOS transistors.

10. A storage server, characterized in that, The storage server includes the circuit according to any one of claims 1 to 9 to charge and discharge the backup power circuit of the storage server.

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