A switch control method and device for an AC solid-state power controller

Abstract

The present invention discloses a switch control method and device for an AC solid-state power controller, which belongs to the fields of power electronics technology and electrical engineering technology. The control method of the present invention samples and processes the AC power supply voltage and the current of the current-limiting branch, obtains a positive / negative half-cycle judgment signal of the AC power supply voltage, a positive / negative half-cycle judgment signal of the current-limiting branch current, and a double frequency signal of the AC power supply voltage frequency, and logically combines the above signals and the external switch signal to obtain a control signal of the current-limiting branch power tube, and further obtains a control signal of the main power branch power tube. The current-limiting branch power tube can achieve "zero voltage turn-on, zero current turn-off", and the main power branch power tube can achieve "zero current turn-on". The switch control method of the present invention can efficiently suppress the impact current generated in the process of turning on the capacitive load, and has the advantages of high reliability and low complexity.

Description

Technical Field

[0001] The present invention relates to a switch control method and device of an AC solid-state power controller, belonging to the fields of power electronics technology and electrical engineering technology. Background Art

[0002] Solid-State Power Controllers (SSPCs) use power semiconductor devices as switches, integrating the switching control functions of relays and the protection functions of circuit breakers. They have the advantages of fast response, no arcing, no mechanical contacts, low on-state power consumption, strong load adaptability, and high reliability. They are the key core of advanced solid-state power distribution systems.

[0003] To reduce the current surge when capacitive loads are switched on, DC SSPCs primarily employ slow-turn-on control strategies or current-limiting branches. For AC SSPCs, the current stress issue at the turn-on moment can theoretically be addressed by adding a current-limiting branch. However, because AC SSPCs utilize a control method that switches the upper and lower power transistors on and off in a specific sequence, independent of zero-point detection, the switching process itself is inherently complex. Adding a current-limiting branch to this approach presents new technical challenges, such as control timing coordination and branch switching. A mature solution currently lacks a solution.

[0004] Therefore, for AC SSPCs with parallel current-limiting branches, an innovative control method is urgently needed that can not only effectively suppress the inrush current when the capacitive load is turned on, but also significantly improve the reliability of the system, thereby further enhancing the performance and application scope of the AC SSPC. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the defects and shortcomings in the aforementioned background and provide a switching control method and device for an AC solid-state power controller suitable for a parallel current limiting branch. This method can not only effectively suppress the impact current during the capacitive load opening process, but also accurately coordinate the switching timing between the main power branch and the current limiting branch, thereby improving the stability and reliability of the system.

[0006] In order to solve the above technical problems, the present invention specifically adopts the following technical solutions:

[0007] A switch control method for an AC solid-state power controller, wherein the AC solid-state power controller includes a main power branch and a current limiting branch connected in parallel, characterized by comprising:

[0008] Sampling and processing the AC power supply voltage and the current of the current limiting branch to obtain a positive / negative half-cycle judgment signal of the AC power supply voltage, a positive / negative half-cycle judgment signal of the current limiting branch current, and a double frequency signal of the AC power supply voltage frequency;

[0009] The above signals and the external switch signal are logically combined to obtain the control signal of the current limiting branch power tube; the control signal of the current limiting branch power tube, the voltage across the current limiting branch detection resistor, the threshold voltage corresponding to the rated steady-state current peak, the current limiting branch current positive / negative half-cycle judgment signal and the external switch signal are logically combined to obtain the control signal of the main power branch power tube, so that when the AC solid-state power controller is turned on, the current limiting branch is first turned on at zero voltage, and when the current peak is detected to be lower than the rated current peak, the main power branch is turned on at the current zero point; when the AC solid-state power controller is turned off, the main power branch is first turned off, and the current limiting branch is turned off after the current crosses the zero point.

[0010] Preferably, the current limiting branch includes a current limiting resistor, a power tube on the current limiting branch, a first detection resistor, a second detection resistor, and a power tube under the current limiting branch connected in series in sequence, and the gates of the power tube on the current limiting branch and the power tube under the current limiting branch are connected to different control signals.

[0011] Further preferably, the switch control method of the AC solid-state power controller is characterized by comprising:

[0012] When the current limiting branch is opened, when the power supply voltage is in the positive half cycle, the power tube of the current limiting branch is opened first, and the power tube of the current limiting branch is opened after the voltage crosses zero; when the power supply voltage is in the negative half cycle, the power tube of the current limiting branch is opened first, and the power tube of the current limiting branch is opened after the voltage crosses zero;

[0013] When shutting down the current limiting branch, when the current of the current limiting branch is in the positive half cycle, the power tube of the current limiting branch is shut down first, and the power tube of the current limiting branch is shut down after the current passes through zero; when the current of the current limiting branch is in the negative half cycle, the power tube of the current limiting branch is shut down first, and the power tube of the current limiting branch is shut down after the current passes through zero.

[0014] The present invention also provides an electronic device comprising a processor and a memory, wherein the memory stores a program that can be run on the processor, and is characterized in that when the program is executed by the processor, the steps of the switching control method of the above-mentioned AC solid-state power controller are implemented.

[0015] The beneficial effects brought about by the technical solution of the present invention are as follows:

[0016] 1) The power tube of the current-limiting branch can achieve "zero voltage turn-on and zero current turn-off", and the power tube of the main power branch can achieve "zero current turn-on", and the power tube loss during the turn-on and turn-off process is low;

[0017] 2) Efficiently suppress the inrush current generated during the turn-on of capacitive loads;

[0018] 3) It can accurately coordinate the switching timing of the main power branch and the current limiting branch, and has the advantages of high reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a circuit diagram of an AC solid-state power controller with a parallel current limiting branch;

[0020] Figure 2 It is the power supply voltage detection circuit and the positive and negative half-cycle judgment circuit and the corresponding working timing diagram;

[0021] Figure 3 It is the current detection and positive and negative half-cycle judgment circuit of the current limiting branch and the corresponding working timing diagram;

[0022] Figure 4 This is the power supply voltage frequency doubling detection circuit and the corresponding working timing diagram;

[0023] Figure 5 It is a current limiting branch control logic combination circuit diagram;

[0024] Figure 6 This is the working timing diagram of the current limiting branch control logic combination circuit under capacitive load;

[0025] Figure 7 It is the main power branch control logic combination circuit diagram;

[0026] Figure 8 It is the overall working timing diagram of the AC solid-state power controller. DETAILED DESCRIPTION

[0027] The following describes in detail some key technologies involved in the present invention in conjunction with the accompanying drawings to support the claims. In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention is further described in detail in conjunction with the accompanying drawings and embodiments.

[0028] Example 1

[0029] This embodiment provides a switch control method for an AC solid-state power controller, wherein the AC solid-state power controller includes a main power branch and a current limiting branch connected in parallel. The switch control method includes:

[0030] When the AC solid-state power controller is turned on, the current limiting branch is first turned on at zero voltage. When the current peak is detected to be lower than the rated current peak, the main power branch is turned on at the current zero point.

[0031] When shutting down the AC solid-state power controller, the main power branch is shut down first, and then the current limiting branch is shut down after the current passes through zero.

[0032] Figure 1 FIG. 1 is a circuit diagram of the AC solid-state power controller of this embodiment. Figure 1 As shown, the AC solid-state power controller is connected to the AC power supply V sBetween the load, the AC power supply is 115V AC source, Figure 1 PGND is the power ground. The AC SSPC includes a main power branch, a current-limiting branch, a power supply voltage detection circuit, a power supply voltage positive-negative half-cycle judgment circuit, a power supply voltage double frequency detection circuit, a current-limiting branch current detection circuit, a current-limiting branch current positive-negative half-cycle judgment circuit, a current-limiting branch control logic combination circuit, and a main power branch control logic combination circuit.

[0033] The main power branch of the AC SSPC consists of two identical N-channel enhancement-mode Si MOSFETs (the first power tube S upp and the second power tube S low ) are connected in anti-series, and the gates of the two power tubes are connected to the same control signal CMD m , CMD m From the main power branch control logic combination circuit. The current limiting branch of the AC SSPC is the current limiting resistor R lim、 Two identical N-channel enhancement-mode Si MOSFETs (power tube S on the current limiting branch) u and the power tube S under the current limiting branch l ), the first detection resistor R sense1 , the second detection resistor R sense2 The first detection resistor is connected in series. R sense1 , the second detection resistor R sense2 Connect the analog ground terminal AGND1. U sense+ The first detection resistor R sense1 The voltage across the terminals, U sense- The second sense resistor R sense2 Voltage at both ends. Power tube S on the current limiting branch u The gate is connected to the power tube control signal CMD on the current limiting branch u , the power tube S in the current limiting branch l The gate is connected to the power tube control signal CMD under the current limiting branch l The power tube control signal CMD on the current limiting branch u , power tube control signal CMD under the current limiting branch l From the current limiting branch control logic combination circuit.

[0034] Specifically, the switch control method of the AC solid-state power controller of this embodiment includes:

[0035] When the current limiting branch is turned on, when the power supply voltage is in the positive half cycle, the power tube S under the current limiting branch is turned on first. l , after the voltage passes through zero, the power tube S on the current limiting branch is turned on u When the power supply voltage is in the negative half cycle, the power tube S on the current limiting branch is turned on first. u , after the voltage passes through zero, the power tube S in the current limiting branch is turned on l ;

[0036] When the current limiting branch is turned off, when the current limiting branch current is in the positive half cycle, the power tube S of the current limiting branch is turned off first. l , after the current passes through zero, the power tube S on the current limiting branch is turned off u When the current in the current limiting branch is in the negative half cycle, the power tube S on the current limiting branch is turned off first. u , after the current passes through zero, the power tube S in the current limiting branch is turned off l .

[0037] like Figure 2 , where (a) shows the power supply voltage detection circuit and the positive and negative half-cycle judgment circuit, and (b) shows the working sequence of the power supply voltage detection circuit and the positive and negative half-cycle judgment circuit. The power supply voltage detection circuit is implemented using a differential proportional operation circuit. The voltage at both ends of the AC power supply is input into the differential proportional operation circuit, and the output signal of the operational amplifier OP is u op , the value is U S * R 2 / R 1. The power supply voltage positive and negative half-cycle judgment circuit includes an RC low-pass filter circuit and two comparators. u op The positive and negative half-cycle judgment circuit of the input power supply voltage is processed by the RC low-pass filter circuit and compared with the high threshold voltage through two comparators. U TH + and low threshold voltage U TH -Compare and get the power supply voltage positive / negative half cycle judgment signal U + / U -Signal.

[0038] like Figure 3 , where (a) shows the current detection circuit of the current limiting branch and the positive and negative half-cycle judgment circuit, and (b) shows the working sequence of the current detection circuit of the current limiting branch and the positive and negative half-cycle judgment circuit. The current detection circuit of the current limiting branch is realized by a differential proportional operation circuit. The first and second detection resistors are connected. R sense1 、 R sense2 The voltage at both ends is input into the differential proportional operation circuit, and the operational amplifier OP outputs the signal i opThe current limiting branch current positive and negative half-cycle judgment circuit includes RC low-pass filter and two comparators. i op The positive and negative half-cycle judgment circuit of the input current limiting branch is processed by the RC low-pass filter circuit and is respectively compared with the high threshold voltage through two comparators. I TH + and low threshold voltage I TH -Compare and get the current limiting branch current positive / negative half cycle judgment signal I + / I -Signal.

[0039] like Figure 4 , where (a) shows the power supply voltage frequency doubling detection circuit, and (b) shows the working sequence of the power supply voltage frequency doubling detection circuit. The power supply voltage frequency doubling detection circuit is implemented by an OR gate, which converts the power supply voltage positive / negative half-cycle judgment signal U + and U -The signal undergoes OR logic operation, because U + and U - are the positive and negative half-cycle signals of the power supply voltage, and their phase difference is 180°, so their OR logic operation result will generate a signal with a frequency twice the power supply voltage frequency, that is, the AC power supply voltage frequency doubled signal Fre signal.

[0040] Figure 5 This is the current limiting branch control logic combination circuit diagram. I + / I -For the current limiting branch current positive / negative half cycle judgment signal, U + / U - is the power supply voltage positive / negative half cycle judgment signal, CMD is the external switch signal, CMD u It is the power tube control signal on the current limiting branch, CMD l is the power tube control signal under the current limiting branch, Fre is the AC power supply voltage frequency doubled signal, After1 is the power tube auxiliary shutdown signal under the current limiting branch, and After2 is the power tube auxiliary shutdown signal on the current limiting branch. I + / I -、 U + / U -, CMD, and Fre are processed by the logic circuit to obtain CMD u 、CMD l .

[0041] like Figure 5As shown, the current-limiting branch control logic combination circuit includes a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a first OR gate OR1, a second OR gate OR2, a first NAND gate NAND1, a second NAND gate NAND2, a first D flip-flop D1, a second D flip-flop D2, a first flip-flop RS1, and a second RS flip-flop RS2. The first and second NOR gates NOR1 and NOR2, the first D flip-flop D1, the first OR gate OR1, the first NAND gate NAND1, and the first RS flip-flop RS1 constitute the power tube control logic circuit on the current-limiting branch; the third and fourth NOR gates NOR3 and NOR4, the second D flip-flop D2, the second OR gate OR2, the second NAND gate NAND2, and the second RS flip-flop RS2 constitute the power tube control logic circuit on the lower current-limiting branch.

[0042] The input end of the first NOR gate NOR1 is connected to the external switch signal CMD and the power tube control signal CMD on the current limiting branch. u And the current limiting branch current negative half cycle judgment signal I -. The input end of the second NOR gate NOR2 is connected to the Q-end output signal After2 of the second D flip-flop D2 and the current limiting branch current negative half cycle judgment signal I -, signal After2 is the auxiliary shutdown signal of the power tube on the current limiting branch. The D terminal of the first D flip-flop D1 is connected to the output terminal of the first NOR gate NOR1, and the CLK terminal is connected to the AC power supply voltage frequency doubled signal Fre signal. The input terminal of the first OR gate OR1 is connected to the output terminal signal of the second NOR gate NOR2 and the external switch signal CMD. The input terminal of the first NAND gate NAND1 is connected to the power supply voltage negative half cycle judgment signal U - and external switch signal CMD; the input end of the second NAND gate NAND2 is connected to the power supply voltage positive half cycle judgment signal U + and external switch signal CMD. The R terminal of the first RS trigger RS1 is connected to the output terminal of the first OR gate OR1, the S terminal is connected to the output terminal of the first NAND gate NAND1, and the Q terminal outputs the power tube control signal CMD on the current limiting branch. u The input end of the third NOR gate NOR3 is connected to the Q-end output signal After1 of the first D flip-flop D1 and the current limiting branch current positive half cycle judgment signal I +, signal After1 is the auxiliary shutdown signal of the power tube under the current limiting branch. The input end of the second OR gate OR2 is connected to the output signal of the third NOR gate NOR3 and the external switch signal CMD. The input end of the fourth NOR gate NOR4 is connected to the power tube control signal CMD1 under the current limiting branch and the current positive half cycle judgment signal of the current limiting branch. I+ and external switch signal CMD. The D terminal of the second D flip-flop D2 is connected to the output terminal of the fourth NOR gate NOR4, and the CLK terminal is connected to the AC power supply voltage frequency doubled signal Fre signal; the R terminal of the second RS flip-flop RS2 is connected to the output terminal of the second NAND gate NAND2, the S terminal is connected to the output terminal of the second OR gate OR2, and the Q terminal outputs the power tube control signal CMD of the current limiting branch. l .

[0043] Figure 7 This is the main power branch control logic combination circuit diagram, where: U sense The first and second current detection resistors R sense1 、 R sense2 The voltage across the terminals, U sense = U sense+ - U sense- . U TH is the threshold voltage corresponding to the rated steady-state current peak, CMD u It is the power tube control signal on the current limiting branch, CMD l It is the power tube control signal of the current limiting branch. I + / I - is the current limiting branch current positive / negative half cycle judgment signal, CMD is the external switch signal, CMD m For the main power branch power tube (S upp 、S low ) control signal.

[0044] like Figure 7 As shown, the main power branch control logic combination circuit includes: a conditioning amplifier circuit, a full-wave rectifier filter circuit, a peak detection circuit, a comparator CMP, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fifth NOR gate NOR5, and a third D flip-flop D3. The input end of the conditioning amplifier circuit is connected to the voltage across the current limiting branch detection resistor. U sense After conditioning, it is input into the peak detection circuit through the full-wave rectifier filter circuit, where the conditioning amplification factor is set to K 1. The output of the peak detection circuit is connected to the negative input of the comparator CMP, and the positive input of the comparator CMP is connected to the threshold voltage corresponding to the rated steady-state current peak. U TH , U TH = KI p , K for K 1*(R sense1 + R sense2 ), I p The output of the first AND gate is connected to one input of the second AND gate AND2; the two inputs of the first AND gate are connected to the upper and lower power tube control signals respectively, and the output of the first AND gate is connected to the other input of the second AND gate AND2; the output of the second AND gate AND2 is connected to the D terminal of the third D flip-flop D3; the two inputs of the fifth NOR gate NOR5 are connected to the positive and negative half-cycle judgment signals of the current limiting branch respectively I + and I -, its output end is connected to the CLK end of the third D flip-flop D3, the Q end of the third D flip-flop D3 is connected to one input end of the third AND gate AND3, the other input end of the third AND gate AND3 is connected to the external switch signal CMD, and its output end outputs the main power branch power tube control signal CMD m .

[0045] Figure 6 The working sequence diagram of the current limiting branch control logic combination circuit under capacitive load is shown in the figure. In the control sequence, the power supply voltage u s In the negative half cycle, the current limiting branch receives the opening instruction, and the current limiting branch current i limit In the positive half cycle, the current limiting branch receives the shutdown command, t 0~ t 2 corresponds to the opening process of the current limiting branch, t 3~ t 5 corresponds to the shutdown process of the current limiting branch.

[0046] (1) Opening process

[0047] t 0: The current limiting branch receives the opening instruction (CMD is set to high level), and detects that the power supply voltage is u s In the negative half cycle, CMD u Set high level, the power tube on the current limiting branch S u Immediately open, power tube down S l Still keep the cut-off state (CMD l Keep low level), the current limiting branch is in the reverse cut-off state;

[0048] t 1: Power supply voltage u s When crossing the zero point, the current in the current-limiting branch slowly rises from zero;

[0049] t 2: CMD l Set to high level to turn on the power tube under the current limiting branch S l , the current limiting branch is fully conductive;

[0050] (2) Shutdown process

[0051] t 3: The current limiting branch receives the shutdown command (CMD is set to low level), and the current of the current limiting branch is detected at this time i limit In the positive half cycle, CMD l Set to low level, the power tube of the current limiting branch S l Shut down immediately and put on the power tube S u Still keep conducting state (CMD u Maintain high level), the current path is: lower power tube conductive channel-upper power tube body diode;

[0052] t 4: The current of the current limiting branch passes through zero, because the power tube under the current limiting branch S l is turned off, so the current in the current-limiting branch is then 0;

[0053] t 5: Signal After2 is set to high level, CMD u Set to low level, the current limiting branch switches to a bidirectional cut-off state.

[0054] The control logic of the current limiting branch is summarized in Table 1:

[0055] Table 1 Current limiting branch zero-crossing switch control logic

[0056]

[0057] Figure 8 This is the overall working sequence diagram of the AC solid-state power controller. In the control sequence, the power supply voltage u s When the AC SSPC receives the opening instruction in the negative half cycle, the load current i L In the positive half cycle, the AC SSPC receives the shutdown command, t 0~ t 4 corresponds to the opening process of the AC SSPC main power branch, t 5~ t 7 corresponds to the shutdown process of the AC SSPC main power branch. u s is the power supply voltage, U + / U- is the power supply voltage positive / negative half cycle judgment signal, CMD is the external switch signal, i L is the load current, I + / I - is the current limiting branch current positive / negative half cycle judgment signal, i limit is the current limiting branch current, i main Main power branch current, CMD u CMD is the power tube control signal on the current limiting branch. l is the power tube control signal under the current limiting branch, After2 is the auxiliary shutdown signal of the power tube on the current limiting branch, CMD m It is the control signal of the power tube of the main power branch.

[0058] (1) Opening process

[0059] t 0: AC SSPC receives the opening command (CMD is set to 1) and determines the power supply voltage at this time u s In the negative half cycle, the power tube on the current limiting branch S u Activate now (CMD u Set to 1), the lower power tube S l Still keep the cut-off state (CMD l Keep 0), the AC SSPC is in the reverse cutoff state;

[0060] t 1: The power supply voltage passes through zero, and the SSPC current starts to rise slowly from zero;

[0061] t 2: Turn on the power tube under the current limiting branch S l (CMD l Set to 1), the current limiting branch is fully conductive;

[0062] t 3: It is detected that the current peak of the current limiting branch is close to the rated current peak;

[0063] t 4: When the current crosses zero, turn on the main power branch power tube (CMD m Set to 1) to ensure smooth current commutation to the main power branch.

[0064] (2) Shutdown process

[0065] t 5: AC SSPC receives the shutdown command (CMD is set to 0), and the main power branch power tube is slowly shut down (CMDm Set to 0) so that the current is smoothly commutated to the current limiting branch;

[0066] t 6: Determine that the current of the current limiting branch is in the positive half cycle, and the power tube of the current limiting branch S l Immediate shutdown (CMD l Set to 0), the power tube on the current limiting branch S u Still keep conducting state (CMD u Maintain 1), at this time the SSPC current flows through the upper power tube conductive channel - the lower power tube body diode;

[0067] t 7: The auxiliary shutdown signal After2 of the upper power tube is set to a high level, turning off the power tube on the current limiting branch S u (CMD u Set to 0), the AC SSPC switches to the bidirectional cutoff state.

[0068] The control logic of the AC SSPC switch with current limiting branch is summarized in Table 2:

[0069] Table 2 AC SSPC switch control logic with current limiting branch

[0070]

[0071] Example 2

[0072] This embodiment provides an electronic device, including a processor and a memory communicatively connected to the processor, wherein the memory stores a program that can be run on the processor, and when the program is executed by the processor, the steps of the switch control method of the AC solid-state power controller provided in the above embodiment are implemented.

[0073] The program may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server.

[0074] The switching control method of the AC solid-state power controller of the present invention samples and processes the AC power supply voltage and the current of the current-limiting branch to obtain a positive / negative half-cycle judgment signal for the AC power supply voltage, a positive / negative half-cycle judgment signal for the current-limiting branch current, and a double frequency signal for the AC power supply voltage. The above signals and an external switch signal are logically combined to obtain a control signal for the current-limiting branch power tube. The control signal for the current-limiting branch power tube, the voltage across the current-limiting branch detection resistor, the threshold voltage corresponding to the rated steady-state current peak, the positive / negative half-cycle judgment signal for the current-limiting branch current, and the external switch signal are logically combined to obtain a control signal for the main power branch power tube. The current-limiting branch power tube can achieve "zero voltage turn-on and zero current turn-off," and the main power branch power tube can achieve "zero current turn-on." This switching control method can effectively suppress the inrush current generated during the turn-on of a capacitive load and has the advantages of high reliability and low complexity.

[0075] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A switch control method for an AC solid-state power controller, wherein the AC solid-state power controller comprises a main power branch and a current limiting branch connected in parallel, characterized in that: include: Sampling and processing the AC power supply voltage and the current of the current limiting branch to obtain a positive / negative half-cycle judgment signal of the AC power supply voltage, a positive / negative half-cycle judgment signal of the current limiting branch current, and a double frequency signal of the AC power supply voltage frequency; The above signals and the external switch signal are logically combined to obtain the control signal of the current limiting branch power tube; the control signal of the current limiting branch power tube, the voltage across the current limiting branch detection resistor, the threshold voltage corresponding to the rated steady-state current peak, the current limiting branch current positive / negative half-cycle judgment signal and the external switch signal are logically combined to obtain the control signal of the main power branch power tube, so that when the AC solid-state power controller is turned on, the current limiting branch is first turned on at zero voltage, and when the current peak is detected to be lower than the rated current peak, the main power branch is turned on at the current zero point; when the AC solid-state power controller is turned off, the main power branch is first turned off, and the current limiting branch is turned off after the current crosses zero point; The current limiting branch includes a current limiting resistor, a power tube on the current limiting branch, a first detection resistor, a second detection resistor, and a power tube under the current limiting branch connected in series in sequence, and the gates of the power tube on the current limiting branch and the power tube under the current limiting branch are connected to different control signals; The AC solid-state power controller includes a current limiting branch control logic combination circuit, which includes a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first OR gate, a second OR gate, a first NAND gate, a second NAND gate, a first D flip-flop, a second D flip-flop, a first RS flip-flop, and a second RS flip-flop; the input end of the first NOR gate is connected to an external switch signal, a power tube control signal on the current limiting branch, and a current limiting branch current negative half-cycle judgment signal; the input end of the second NOR gate is connected to the Q-end output signal of the second D flip-flop and the current limiting branch current negative half-cycle judgment signal; the D end of the first D flip-flop is connected to the output end of the first NOR gate, and the CLK end is connected to a double frequency signal of the AC power supply voltage frequency; the input end of the first OR gate is connected to the output end signal of the second NOR gate and the external switch signal; the input end of the first NAND gate is connected to the power supply voltage negative half-cycle judgment signal and the external switch signal; the input end of the second NAND gate is connected to the power supply voltage positive half-cycle judgment signal and the external switch signal; The R terminal of the first RS flip-flop is connected to the output terminal of the first OR gate, the S terminal is connected to the output terminal of the first NAND gate, and the Q terminal outputs the power tube control signal on the current limiting branch; the input terminal of the third NOR gate is connected to the Q terminal output signal of the first D flip-flop and the current limiting branch current positive half-cycle judgment signal; the input terminal of the second OR gate is connected to the output terminal signal of the third NOR gate and the external switch signal; the input terminal of the fourth NOR gate is connected to the power tube control signal under the current limiting branch, the current limiting branch current positive half-cycle judgment signal and the external switch signal; the D terminal of the second D flip-flop is connected to the output terminal of the fourth NOR gate, and the CLK terminal is connected to the AC power supply voltage frequency doubled signal; The R terminal of the second RS trigger is connected to the output terminal of the second NAND gate, the S terminal is connected to the output terminal of the second OR gate, and the Q terminal outputs the power tube control signal of the current limiting branch; The AC solid-state power controller includes a main power branch control logic combination circuit, which includes: a conditioning amplifier circuit, a full-wave rectifier filter circuit, a peak detection circuit, a comparator, a first AND gate, a second AND gate, a third AND gate, a fifth NOR gate, and a third D flip-flop; The input end of the conditioning amplifier circuit is connected to the voltage across the current limiting branch detection resistor, and the output end is connected to the input end of the peak detection circuit through the full-wave rectifier filter circuit. The output end of the peak detection circuit is connected to the negative phase input end of the comparator, the positive phase input end of the comparator is connected to the threshold voltage corresponding to the rated steady-state current peak, and the output end is connected to one of the input ends of the second AND gate; the two input ends of the first AND gate are respectively connected to the upper and lower power tube control signals of the current limiting branch, and the output end is connected to the other input end of the second AND gate; the output end of the second AND gate is connected to the D end of the third D flip-flop; the two input ends of the fifth OR-NON gate are respectively connected to the positive and negative half-cycle judgment signals of the current limiting branch, the output end is connected to the CLK end of the third D flip-flop, the Q end is connected to one input end of the third AND gate, the other input end of the third AND gate is connected to the external switch signal, and the output end outputs the control signal of the power tube of the main power branch.

2. The switch control method of the AC solid-state power controller according to claim 1, characterized in that: The main power branch is composed of two power tubes connected in reverse series, and the gates of the two power tubes are connected to the same control signal.

3. The switch control method of the AC solid-state power controller according to claim 1, characterized in that: include: When the current limiting branch is opened, when the power supply voltage is in the positive half cycle, the power tube of the current limiting branch is opened first, and the power tube of the current limiting branch is opened after the voltage crosses zero; when the power supply voltage is in the negative half cycle, the power tube of the current limiting branch is opened first, and the power tube of the current limiting branch is opened after the voltage crosses zero; When shutting down the current limiting branch, when the current of the current limiting branch is in the positive half cycle, the power tube of the current limiting branch is shut down first, and the power tube of the current limiting branch is shut down after the current passes through zero; when the current of the current limiting branch is in the negative half cycle, the power tube of the current limiting branch is shut down first, and the power tube of the current limiting branch is shut down after the current passes through zero.

4. An electronic device comprising a processor and a memory, wherein the memory stores a program that can be run on the processor, characterized in that: When the program is executed by the processor, the steps of the switch control method of the AC solid-state power controller according to any one of claims 1 to 3 are implemented.

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