Circuit structure for realizing power-on and power-off timing control

Abstract

The present invention relates to a circuit structure for implementing power-on and power-off timing control of a power supply, comprising a double-edge ramp voltage generator and an n-stage output driver circuit. The input ends of the n-stage output driver circuit are both connected to the output ends of the double-edge ramp voltage generator. The double-edge ramp voltage generator converts the rising edge and falling edge of an input power-on and power-off control signal into a rising ramp voltage signal and a falling ramp voltage signal with controllable slopes, respectively. The output driver circuit compares the ramp voltage signal with an input threshold set by the circuit and converts the comparison result into a high-level and low-level output signal. The output signal of the output driver circuit serves as an enable signal for each power converter. The circuit structure for implementing power-on and power-off timing control of the present invention generates multiple power supply enable control signals, can control the power-on and power-off timing of multiple power supplies, has an adjustable time delay between the power-on and power-off moments of each power supply, and can easily expand the number of supported power supplies. The cost is low and the design is simple.

Description

Technical Field

[0001] The present invention relates to the field of power supply control technology, in particular to the field of power-on and power-off timing of integrated circuits, and specifically refers to a circuit structure for realizing power-on and power-off timing control. Background Art

[0002] With the advancement of integrated circuit technology, the system functionality of modern electronic devices is becoming increasingly powerful. The powerful functions provided by these devices are naturally inseparable from complex and powerful chips such as SOCs, CPUs, GPUs, and FPGAs. These complex chips often require multiple power supplies, and strict power-up and power-down sequencing requirements are imposed on these power supplies to avoid malfunction or even damage. Therefore, careful power-up and power-down sequencing is required when powering these chips.

[0003] On the other hand, an electronic device system usually contains multiple mutually coupled circuit modules, and the power-on and power-off timing between the modules needs to be strictly controlled to avoid power backflow and cause circuit malfunction.

[0004] Figure 1 This diagram shows a typical power-on and power-off sequence for a system with n power supplies. t1 to t(n-2) represent the power-on and power-off delays between each power supply. In practice, different circuit systems have different requirements for these delays.

[0005] Currently, common power sequencing solutions typically utilize MCUs, programmable logic chips, and dedicated timing chips. When the system is connected to an external power source, a single power source is generated to power these chips. Upon receiving the power-on signal, these chips then generate control signals according to a preset sequence to activate the remaining power supplies. Upon receiving the power-off signal, they then generate control signals according to a preset sequence to deactivate the remaining power supplies. These solutions easily achieve precise power-on and power-off sequencing, but MCUs or programmable logic chips require program development and a pre-reserved programming interface, resulting in high costs. Dedicated timing chips, such as TI's LM3880 / LM3881, generally support a limited number of power supplies and have non-adjustable delay values, making them applicable only to scenarios with fewer than three power supplies. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a circuit structure for realizing power-on and power-off timing control which has the advantages of low cost, simple design and wide application range.

[0007] In order to achieve the above-mentioned purpose, the circuit structure of the present invention for realizing power-on and power-off timing control is as follows:

[0008] The circuit structure for implementing power-on and power-off timing control has the following main features: the circuit structure includes a double-edge ramp voltage generator and an n-level output drive circuit, the input ends of the n-level output drive circuit are both connected to the output ends of the double-edge ramp voltage generator, the double-edge ramp voltage generator is used to convert the rising edge and falling edge of the input power-on and power-off control signal into a rising ramp voltage signal and a falling ramp voltage signal with controllable slopes, respectively, the output drive circuit is used to compare the ramp voltage signal with an input threshold set by the output drive circuit, and convert the comparison result into a high-level and low-level output signal, the output signal of the output drive circuit serves as the enable signal of each power converter; the n-level output drive circuit is set with different thresholds, if the ramp voltage is higher than the threshold set by the output drive circuit, the output drive circuit outputs a high level, otherwise, it outputs a low level.

[0009] Preferably, the double-edge ramp voltage generator includes a switching circuit, a constant current source circuit and an IV conversion circuit, the input end of the constant current source circuit is connected to the switching circuit, the input end of the IV conversion circuit is connected to the constant current source circuit, and the output end of the IV conversion circuit is connected to the input end of the n-stage output drive circuit; the switching circuit is used to control the charging and discharging of the constant current source circuit, the constant current source circuit charges or discharges the IV conversion circuit according to the state of the switching circuit, and the IV conversion circuit converts the charging current of the constant current source circuit into a ramp voltage signal with a rising edge, and converts the discharge current of the constant current source circuit into a ramp voltage signal with a falling edge.

[0010] Preferably, the switching circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, a first NMOS transistor, and a second PMOS transistor. One end of the first resistor is connected to the power supply VDD, and the other end is connected to the gate of the second PMOS transistor. One end of the first capacitor is connected to the power supply VDD, and the other end is connected to the gate of the second PMOS transistor. One end of the third resistor is connected to the gate of the second PMOS transistor, and the other end is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to a power-up and power-down control signal. One end of the second resistor is connected to the power-up and power-down control signal, and the other end is grounded. The source of the second PMOS transistor is connected to the power supply VDD, and the drain of the second PMOS transistor is connected to the constant current source circuit. The second resistor is used to turn off the first NMOS transistor in an initial state. The first NMOS transistor is used to control the on and off state of the second PMOS transistor. The first resistor, the third resistor, and the first capacitor form an RC network for controlling the on and off time of the second PMOS transistor.

[0011] Preferably, the constant current source circuit includes a first PNP transistor, a second PNP transistor, a third PNP transistor and a fourth adjustable resistor, the emitter of the first PNP transistor is connected to the drain of the second PMOS transistor of the switching circuit, the collector of the first PNP transistor is connected to the fourth adjustable resistor, the other end of the fourth adjustable resistor is grounded, the emitter of the second PNP transistor is connected to the emitter of the first PNP transistor, the base and collector of the second PNP transistor are both connected to the base of the first PNP transistor, the base of the third PNP transistor is connected to the collector of the first PNP transistor, the emitter of the third PNP transistor is connected to the collector of the second PNP transistor, and the collector of the third PNP transistor is connected to the IV conversion circuit; the fourth adjustable resistor is used to determine the size of the charging and discharging current.

[0012] Preferably, the IV conversion circuit includes a second capacitor and an operational amplifier, one end of the second capacitor is connected to the collector of the third PNP transistor of the constant current source circuit, the other end of the second capacitor is grounded, the V+ pin of the operational amplifier is connected to the collector of the third PNP transistor, the V- pin and VO pin of the operational amplifier are both connected to the input end of the n-level output drive circuit, the VCC pin of the operational amplifier is connected to the power supply VDD, and the VSS pin is grounded.

[0013] Preferably, the n-stage output drive circuit in the n-stage output drive circuit includes a fifth resistor, a sixth resistor, a third NMOS transistor, a fourth NMOS transistor, a seventh resistor, and an eighth resistor. One end of the fifth resistor is connected to the output end of the IV conversion circuit, and the other end is connected to the gate of the third NMOS transistor. One end of the sixth resistor is connected to the gate of the third NMOS transistor, and the other end of the sixth resistor is grounded. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the output end. One end of the seventh resistor is connected to the power supply VDD, and the other end is connected to the drain of the third NMOS transistor. One end of the eighth resistor is connected to the power supply VDD, and the other end is connected to the output end. The fifth and sixth resistors form a voltage divider network for dividing the ramp voltage signal to drive the third NMOS transistor. The third NMOS transistor and the seventh resistor are used to control the on and off of the fourth NMOS transistor. The fourth NMOS transistor is used to reverse the output signal of the third NMOS transistor so that the output signal is in the same direction as the input signal.

[0014] The circuit structure of the present invention is used to realize power-on and power-off timing control of the power supply. A simple circuit constructed by an operational amplifier, a MOS tube, a transistor, a resistor, and a capacitor generates a multi-channel power supply enable control signal, which can control the power-on and power-off timing of the multiple power supplies. The delay value between the power-on and power-off moments of each power supply is adjustable, and the number of supported power supplies can be easily expanded. The cost is low and the design is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a typical power-on and power-off timing diagram in a system with n power supplies in the prior art.

[0016] Figure 2 This is a structural block diagram of the circuit structure for realizing power-on and power-off timing control of the present invention.

[0017] Figure 3 The figure is a circuit structure diagram of an embodiment of a circuit structure for realizing power-on and power-off timing control of a power supply according to the present invention.

[0018] Figure 4 The figure is a schematic diagram of an equivalent circuit of a double-edge ramp voltage generator after receiving a power-on signal in a circuit structure for realizing power-on and power-off timing control of the present invention.

[0019] Figure 5 This is a schematic diagram of an equivalent circuit of a double-edge ramp voltage generator after receiving a power-off signal in a circuit structure for realizing power-on and power-off timing control of the present invention.

[0020] Figure 6 This is a circuit simulation result diagram of an embodiment of the circuit structure for realizing power-on and power-off timing control of the present invention. DETAILED DESCRIPTION

[0021] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0022] The circuit structure of the present invention for implementing power-on and power-off timing control includes a double-edge ramp voltage generator and an n-level output drive circuit. The input ends of the n-level output drive circuit are both connected to the output ends of the double-edge ramp voltage generator. The double-edge ramp voltage generator is used to convert the rising edge and falling edge of the input power-on and power-off control signal into a rising ramp voltage signal and a falling ramp voltage signal with controllable slopes, respectively. The output drive circuit is used to compare the ramp voltage signal with an input threshold set by the output drive circuit and convert the comparison result into a high-level and low-level output signal. The output signal of the output drive circuit serves as an enable signal for each power converter. The n-level output drive circuit is set with different thresholds. If the ramp voltage is higher than the threshold set by the output drive circuit, the output drive circuit outputs a high level; otherwise, it outputs a low level.

[0023] As a preferred embodiment of the present invention, the double-edge ramp voltage generator includes a switching circuit, a constant current source circuit and an IV conversion circuit, the input end of the constant current source circuit is connected to the switching circuit, the input end of the IV conversion circuit is connected to the constant current source circuit, and the output end of the IV conversion circuit is connected to the input end of the n-level output drive circuit; the switching circuit is used to control the charging and discharging of the constant current source circuit, the constant current source circuit charges or discharges the IV conversion circuit according to the state of the switching circuit, and the IV conversion circuit converts the charging current of the constant current source circuit into a ramp voltage signal with a rising edge, and converts the discharge current of the constant current source circuit into a ramp voltage signal with a falling edge.

[0024] As a preferred embodiment of the present invention, the switching circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first NMOS transistor M1 and a second PMOS transistor M2, one end of the first resistor R1 is connected to the power supply VDD, and the other end is connected to the gate of the second PMOS transistor M2, one end of the first capacitor C1 is connected to the power supply VDD, and the other end is connected to the gate of the second PMOS transistor M2, one end of the third resistor R3 is connected to the gate of the second PMOS transistor M2, and the other end is connected to the drain of the first NMOS transistor M1, and the source of the first NMOS transistor M1 is connected to The gate of the first NMOS transistor M1 is connected to the power-on and power-off control signals, one end of the second resistor R2 is connected to the power-on and power-off control signals, and the other end is grounded, the source of the second PMOS transistor M2 is connected to the power supply VDD, and the drain of the second PMOS transistor M2 is connected to the constant current source circuit; the second resistor R2 is used to turn off the first NMOS transistor M1 in the initial state, and the first NMOS transistor M1 is used to control the on and off of the second PMOS transistor M2. The first resistor R1, the third resistor R3 and the first capacitor C1 form an RC network for controlling the on and off time of the second PMOS transistor M2.

[0025] As a preferred embodiment of the present invention, the constant current source circuit includes a first PNP transistor Q1, a second PNP transistor Q2, a third PNP transistor Q3 and a fourth adjustable resistor R4, the emitter of the first PNP transistor Q1 is connected to the drain of the second PMOS transistor M2 of the switching circuit, the collector of the first PNP transistor Q1 is connected to the fourth adjustable resistor R4, the other end of the fourth adjustable resistor R4 is grounded, the emitter of the second PNP transistor Q2 is connected to the emitter of the first PNP transistor Q1, the base and collector of the second PNP transistor Q2 are both connected to the base of the first PNP transistor Q1, the base of the third PNP transistor Q3 is connected to the collector of the first PNP transistor Q1, the emitter of the third PNP transistor Q3 is connected to the collector of the second PNP transistor Q2, and the collector of the third PNP transistor Q3 is connected to the IV conversion circuit; the fourth adjustable resistor R4 is used to determine the size of the charging and discharging current.

[0026] As a preferred embodiment of the present invention, the IV conversion circuit includes a second capacitor C2 and an operational amplifier U1, one end of the second capacitor C2 is connected to the collector of the third PNP transistor Q3 of the constant current source circuit, the other end of the second capacitor C2 is grounded, the V+ pin of the operational amplifier U1 is connected to the collector of the third PNP transistor Q3, the V- pin and VO pin of the operational amplifier U1 are both connected to the input end of the n-level output drive circuit, the VCC pin of the operational amplifier U1 is connected to the power supply VDD, and the VSS pin is grounded.

[0027] As a preferred embodiment of the present invention, the n-stage output drive circuit in the n-stage output drive circuit includes a fifth resistor R5n, a sixth resistor R6n, a third NMOS transistor M3n, a fourth NMOS transistor M4n, a seventh resistor R7n, and an eighth resistor R8n. One end of the fifth resistor R5n is connected to the output end of the IV conversion circuit, and the other end is connected to the gate of the third NMOS transistor M3n. One end of the sixth resistor R6n is connected to the gate of the third NMOS transistor M3n, and the other end of the sixth resistor R6n is grounded. The source of the third NMOS transistor M3n is grounded, the drain of the third NMOS transistor M3n is connected to the gate of the fourth NMOS transistor M4n, and the fourth NMOS transistor M4n is connected to the gate of the fourth NMOS transistor M4n. The source of the OS transistor M4n is grounded, the drain of the fourth NMOS transistor M4n is connected to the output terminal, one end of the seventh resistor R7n is connected to the power supply VDD, and the other end is connected to the drain of the third NMOS transistor M3n. One end of the eighth resistor R8n is connected to the power supply VDD, and the other end is connected to the output terminal. The fifth resistor R5n and the sixth resistor R6n form a voltage divider network for dividing the ramp voltage signal to drive the third NMOS transistor M3n. The third NMOS transistor M3n and the seventh resistor R7n are used to control the on and off of the fourth NMOS transistor M4n. The fourth NMOS transistor M4n is used to reverse the output signal of the third NMOS transistor M3n so that the output signal is in the same direction as the input signal.

[0028] The present invention realizes power-on and power-off timing control of multiple power supplies in a simple and low-cost manner. The time delay value between the power-on and power-off moments of each power supply is adjustable, and the number of supported power supplies can be easily expanded.

[0029] The power on and off timing control circuit of the present invention has a block diagram as shown in FIG. Figure 2 As shown, it includes a double-edge ramp voltage generator and multiple output drive circuits. The double-edge ramp voltage generator is responsible for converting the rising edge and falling edge of the input power-on and power-off control signal into a rising ramp voltage signal and a falling ramp voltage signal with controllable slope respectively; the output drive circuit compares the ramp voltage signal with the input threshold set by the output drive circuit and converts the comparison result into a high-level and low-level output signal. A power supply power-on and power-off timing control circuit, the circuit diagram of which is shown in FIG. Figure 3 shown.

[0030] In the double-edge ramp voltage generator, one end of the first resistor R1 is connected to the power supply VDD, and the other end is connected to the node A; one end of the second resistor R2 is connected to the power-up and power-down control signal IN, and the other end is grounded; one end of the third resistor R3 is connected to the node A, and the other end is connected to the node K; one end of the first capacitor C1 is connected to the power supply VDD, and the other end is connected to the node A; the gate of the first NMOS transistor M1 is connected to the power-up and power-down control signal IN, the source is grounded, and the drain is connected to the node K; the gate of the second PMOS transistor M2 is connected to the node A, the source is connected to VDD, and the drain is connected to the node B; the first The base of the PNP transistor Q1 is connected to node C, the emitter is connected to node B, and the collector is connected to node D; the base and collector of the second PNP transistor Q2 are connected to node C, and the emitter is connected to node B; the base of the third PNP transistor Q3 is connected to node D, the emitter is connected to node C, and the collector is connected to node E; one end of the fourth adjustable resistor R4 is connected to node D, and the other end is grounded; one end of the second capacitor C2 is connected to node E, and the other end is grounded; the V+ pin of the operational amplifier U1 is connected to node E, the V- pin and the VO pin are connected to node F, the VCC pin is connected to VDD, and the VSS pin is grounded.

[0031] The first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the first NMOS transistor M1, and the second PMOS transistor M2 form a switching circuit; the second resistor R2 is used to ensure that the first NMOS transistor M1 is in the off state in the initial state; the first NMOS transistor M1 acts as a switch to control the on and off of the second PMOS transistor M2; the first resistor R1, the third resistor R3, and the first capacitor C1 form an RC network to control the on and off time of the second PMOS transistor M2 to avoid circuit instability caused by excessively fast on or off of the second PMOS transistor M2; the switching circuit is used to control the charging and discharging of the constant current source circuit.

[0032] The first PNP transistor Q1, the second PNP transistor Q2, the third PNP transistor Q3 and the fourth adjustable resistor R4 form a constant current source circuit, which charges or discharges the IV conversion circuit according to the state of the switch circuit. The fourth adjustable resistor R4 determines the size of the charging and discharging current.

[0033] The second capacitor C2 and operational amplifier U1 form an IV conversion circuit, which converts the charging current of the constant current source circuit into a ramp voltage signal with a rising edge, and converts the discharge current of the constant current source circuit into a ramp voltage signal with a falling edge. The slope of the rising-edge ramp voltage signal depends on the charging current, that is, the resistance value of the fourth adjustable resistor R4; the slope of the falling-edge ramp voltage signal depends on the discharge current, that is, the resistance value of the fourth adjustable resistor R4 and the capacitance value of the second capacitor C2. By fine-tuning the resistance value of the fourth adjustable resistor R4, the capacitance value error of the second capacitor C2 can be compensated.

[0034] In the n-th stage output drive circuit, one end of the fifth resistor R5n is connected to the node F and the other end is connected to the node G; one end of the sixth resistor R6n is connected to the node G and the other end is grounded; the gate of the third NMOS transistor M3n is connected to the node G, the source is grounded, and the drain is connected to the node H; the gate of the fourth NMOS transistor M4n is connected to the node H, the source is grounded, and the drain is connected to OUTn; one end of the seventh resistor R7n is connected to VDD and the other end is connected to the node H; and one end of the eighth resistor R8n is connected to VDD and the other end is connected to OUTn.

[0035] The fifth resistor R5n and the sixth resistor R6n form a voltage divider network that divides the ramp voltage signal and drives the third NMOS transistor M3n. The third NMOS transistor M3n and the seventh resistor R7n are used to control the on and off of the fourth NMOS transistor M4n. The fourth NMOS transistor M4n is used to reverse the output signal of the third NMOS transistor M3n to ensure that OUTn and the input signal at the power-on and power-off control signal IN terminal are in the same direction.

[0036] From the description of the above technical solution, it can be seen that the power supply power-on and power-off timing control circuit of the present invention realizes the power-on and power-off timing control of multiple power supplies in a simple and low-cost manner. The delay value between the power-on and power-off moments of each power supply is adjustable, and the number of supported power supplies can be easily expanded.

[0037] Combine Figures 2 to 6 In the specific embodiment of the present invention, Figure 2 This is a block diagram of a power supply power-on and power-off timing control circuit in the present invention. The double-edge ramp voltage generator is responsible for converting the rising edge and falling edge of the input power-on and power-off control signal into a rising ramp voltage signal and a falling ramp voltage signal with controllable slopes, respectively. When the ramp voltage is higher than the input threshold set by the output drive circuit resistor sampling network, the output drive circuit outputs a high level, otherwise it outputs a low level. The output signal of the output drive circuit serves as the enable signal of each power converter. Different thresholds are set for each level of the output drive circuit. Combined with the known rising or falling slope of the ramp voltage signal, accurate power-on and power-off timing control of each power supply can be achieved.

[0038] Attachment Figure 3 This is a specific embodiment of a power supply power-on and power-off timing control circuit in the present invention. This embodiment can complete the power-on and power-off timing control of two power supplies. The following uses this embodiment to further illustrate the working principle of the technical solution of the present invention.

[0039] In this embodiment, the PNP transistor model is 2N2907, the PMOS transistor model is Si1013, and the NMOS transistor model is 2N7002.

[0040] When the IN node receives the power-on and power-off control signal and jumps from a low level to a high level, the first NMOS transistor M1 is turned on and the node K is grounded.

[0041] The voltage at node A decreases slowly through the RC network composed of the first resistor R1, the first capacitor C1, and the third resistor R3, and finally stabilizes at , the second PMOS tube M2 , M2 can be fully turned on.

[0042] The power supply of node B is equal to VDD voltage, i.e. 3.3V. Node B charges the second capacitor C2 through a constant current source power supply composed of the first PNP transistors Q1, Q2, Q3 and the fourth adjustable resistor R4. The charging current formula is as follows:

[0043] .

[0044] The voltage at node E will rise at a slope of K1 until it stabilizes. .

[0045] The operational amplifier U1 forms a voltage follower to enhance the output driving capability of the double-edge ramp voltage generator. The voltage V(f) at node F is equal to the voltage at node E. The voltage rise waveform at node F is as follows: Figure 6 shown.

[0046] Attachment Figure 4 This is the equivalent circuit of the double-edge ramp voltage generator in this process. One end of the current source I1 is connected to VDD, and the other end is connected to node E. One end of the second capacitor C2 is grounded and the other end is connected to node E. The V+ pin of the operational amplifier U1 is connected to node E, the V- pin and the VO pin are connected to node F, the VCC pin is connected to VDD, and the VSS pin is grounded.

[0047] To facilitate understanding of the working principle of this circuit, we now describe Figure 3 and Figure 4 The corresponding relationship of the equivalent circuit.

[0048] Figure 3 The switch circuit composed of the first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the first NMOS transistor M1, and the second PMOS transistor M2 is in the on state during this process. Since the internal resistance of the second PMOS transistor M2 is extremely low in the on state, Figure 4 The equivalent is the power supply VDD; Figure 3 The first PNP transistor Q1, the second PNP transistor Q2, the third PNP transistor Q3 and the fourth adjustable resistor R4 are equivalent to: Figure 4 Medium current source I1; Figure 4 The second capacitor C2 is equivalent to Figure 3 The second capacitor C2 in Figure 4 The operational amplifier U1 in the Figure 3 The operational amplifier U1 in the.

[0049] When the node IN receives the power-on / off control signal and jumps from high level to low level, the first NMOS transistor M1 is turned off, the voltage of the node A is equal to VDD, and the voltage of the second PMOS transistor M2 is , M2 is turned off.

[0050] Node B can no longer charge the second capacitor C2.

[0051] The charge at node E is discharged through the diode formed by the collector and base of the PNP transistor and the fourth adjustable resistor R4. The voltage at node E decreases in the form of an exponential curve. The voltage drop waveform at node F is as follows: Figure 6 shown.

[0052] Attachment Figure 5 This is the equivalent circuit of the double-edge ramp voltage generator in this process. One end of the second resistor R2 is grounded and the other end is connected to node D. The cathode of the diode D1 is connected to node D, and the anode is connected to node E. One end of the second capacitor C2 is grounded and the other end is connected to node E. The V+ pin of the operational amplifier U1 is connected to node E, the V- pin and the VO pin are connected to node F, the VCC pin is connected to VDD, and the VSS pin is grounded.

[0053] To facilitate understanding of the working principle of this circuit, we now describe Figure 3 and Figure 5 The corresponding relationship of the equivalent circuit.

[0054] Figure 3 The switch circuit composed of the first resistor R1, the second resistor R2, the third resistor R3, the first capacitor C1, the first NMOS transistor M1, and the second PMOS transistor M2 is in the off state during this process. Since the internal resistance of M2 is extremely high in the off state, M2 and the node B can be considered disconnected. In addition, since the diodes between the emitter and the base of the first PNP transistor Q1, the second PNP transistor Q2, and the third PNP transistor Q3 are all in the reverse cutoff state, the circuit between the node E and the node D is equivalent to: Figure 5 The diode D1 in the Figure 3 The diode between the collector and base of the third PNP transistor Q3; Figure 5 The second resistor R2 is equivalent to Figure 3 The fourth adjustable resistor R4; Figure 5 The second capacitor C2 is equivalent to Figure 3 The second capacitor C2 in Figure 5 The operational amplifier U1 in the Figure 3 The operational amplifier U1 in the.

[0055] This embodiment includes a two-stage output drive circuit. The NMOS tube with the model number 2N7002 has a conduction voltage of , then the input threshold of the first-stage output driver circuit is as follows:

[0056] ;

[0057] The input threshold of the first-stage output driver circuit is as follows:

[0058] ;

[0059] When the voltage at node F rises at a certain slope Kr, the voltage at node F will first cross , the third NMOS tube M3n is turned on, the node H is grounded, the fourth NMOS tube M4n is turned off, and the OUT1 level is pulled high; after time After that, the voltage at node F will first cross , the fifth NMOS transistor M5 is turned on, the node N is grounded, the sixth NMOS transistor M6 is turned off, and the OUT2 level is pulled high.

[0060] Similarly, when the voltage of F decreases, the voltage of node F will first be lower than , the fifth NMOS tube M5 is turned off, the node N becomes high level, the sixth NMOS tube M6 is turned on, and the OUT2 level is pulled low; After that, the voltage at node F is lower than , the third NMOS transistor M3n is turned off, the node H becomes a high level, the fourth NMOS transistor M4n is turned on, and the OUT1 level is pulled low.

[0061] Attachment Figure 6 2 is the simulation result of the circuit of the above embodiment.

[0062] From the above analysis and simulation results, it can be seen that this embodiment realizes power-on and power-off timing control of two power supplies, and the delay value between the power-on and power-off moments of each power supply is adjustable.

[0063] Furthermore, the output stage of the double-edge ramp voltage generator uses a voltage follower composed of an operational amplifier, which improves the load capacity. By properly selecting the value of the input resistance of the driving circuit, the number of supported power supplies can be easily expanded.

[0064] The main technical principle of the present invention is to form a switching circuit and a constant current source circuit through separate components such as resistors, capacitors, MOS tubes, and triodes. The switching circuit and the constant current source circuit are combined with an operational amplifier and a capacitor to form a double-edge ramp generator circuit with adjustable slope. This circuit, combined with an output drive circuit composed of MOS tubes and resistors, realizes the control of multi-channel power supply timing. The power-on and power-off delay values ​​of different power supplies are adjustable, and the number of supported power supplies can be easily expanded.

[0065] Compared with the existing technology, the circuit structure of the present invention is simple and low-cost. There is no need to write programmable logic code or MCU program. The pure hardware circuit can adjust the delay value between the power on and off moments of the power supply, and the number of supported power supplies can be easily expanded.

[0066] The specific implementation scheme of this embodiment can be found in the relevant descriptions in the above embodiments and will not be repeated here.

[0067] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0068] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is at least two.

[0069] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0070] The circuit structure of the present invention is used to realize power-on and power-off timing control of the power supply. A simple circuit constructed by an operational amplifier, a MOS tube, a transistor, a resistor, and a capacitor generates a multi-channel power supply enable control signal, which can control the power-on and power-off timing of the multiple power supplies. The delay value between the power-on and power-off moments of each power supply is adjustable, and the number of supported power supplies can be easily expanded. The cost is low and the design is simple.

[0071] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A circuit structure for realizing power-on and power-off timing control, characterized in that: The circuit structure includes a double-edge ramp voltage generator and an n-stage output drive circuit. The input ends of the n-stage output drive circuit are both connected to the output ends of the double-edge ramp voltage generator. The double-edge ramp voltage generator is used to convert the rising edge and falling edge of the input power-up and power-down control signals into rising ramp voltage signals and falling ramp voltage signals with controllable slopes, respectively. The output drive circuit is used to compare the ramp voltage signal with the input threshold set by the output drive circuit and convert the comparison result into high-level and low-level output signals. The output signal of the output drive circuit serves as the enable signal of each power converter. The n-stage output drive circuit is set with different thresholds. If the ramp voltage is higher than the threshold set by the output drive circuit, the output drive circuit outputs a high level; otherwise, it outputs a low level. The double-edge ramp voltage generator includes a switching circuit, a constant current source circuit, and an IV conversion circuit. The input end of the constant current source circuit is connected to the switching circuit, the input end of the IV conversion circuit is connected to the constant current source circuit, and the output end of the IV conversion circuit is connected to the input end of the n-stage output drive circuit. The switching circuit is used to control the charging and discharging of the constant current source circuit. The constant current source circuit charges or discharges the IV conversion circuit according to the state of the switching circuit. The IV conversion circuit converts the charging current of the constant current source circuit into a ramp voltage signal with a rising edge, and converts the discharge current of the constant current source circuit into a ramp voltage signal with a falling edge. The switching circuit includes a first resistor, a second resistor, a third resistor, a first capacitor, a first NMOS transistor, and a second PMOS transistor. One end of the first resistor is connected to a power supply VDD, and the other end is connected to a gate of the second PMOS transistor. One end of the first capacitor is connected to the power supply VDD, and the other end is connected to the gate of the second PMOS transistor. One end of the third resistor is connected to the gate of the second PMOS transistor, and the other end is connected to a drain of the first NMOS transistor. The source of the first NMOS transistor is grounded, and the gate of the first NMOS transistor is connected to a power-up and power-down control signal. One end of the second resistor is connected to the power-up and power-down control signal, and the other end is grounded. The source of the second PMOS transistor is connected to the power supply VDD, and the drain of the second PMOS transistor is connected to a constant current source circuit. The second resistor is used to turn off the first NMOS transistor in an initial state. The first NMOS transistor is used to control the on and off state of the second PMOS transistor. The first resistor, the third resistor, and the first capacitor form an RC network for controlling the on and off time of the second PMOS transistor.

2. The circuit structure for realizing power-on and power-off timing control according to claim 1, characterized in that: The constant current source circuit includes a first PNP transistor, a second PNP transistor, a third PNP transistor and a fourth adjustable resistor. The emitter of the first PNP transistor is connected to the drain of the second PMOS transistor of the switching circuit, the collector of the first PNP transistor is connected to the fourth adjustable resistor, the other end of the fourth adjustable resistor is grounded, the emitter of the second PNP transistor is connected to the emitter of the first PNP transistor, the base and collector of the second PNP transistor are both connected to the base of the first PNP transistor, the base of the third PNP transistor is connected to the collector of the first PNP transistor, the emitter of the third PNP transistor is connected to the collector of the second PNP transistor, and the collector of the third PNP transistor is connected to the IV conversion circuit; the fourth adjustable resistor is used to determine the size of the charging and discharging current.

3. The circuit structure for realizing power-on and power-off timing control according to claim 1, characterized in that: The IV conversion circuit includes a second capacitor and an operational amplifier, one end of the second capacitor is connected to the collector of the third PNP transistor of the constant current source circuit, the other end of the second capacitor is grounded, the V+ pin of the operational amplifier is connected to the collector of the third PNP transistor, the V- pin and VO pin of the operational amplifier are both connected to the input end of the n-level output drive circuit, the VCC pin of the operational amplifier is connected to the power supply VDD, and the VSS pin is grounded.

4. The circuit structure for realizing power-on and power-off timing control according to claim 1, characterized in that: The n-stage output drive circuit in the n-stage output drive circuit includes a fifth resistor, a sixth resistor, a third NMOS transistor, a fourth NMOS transistor, a seventh resistor, and an eighth resistor. One end of the fifth resistor is connected to the output end of the IV conversion circuit, and the other end is connected to the gate of the third NMOS transistor. One end of the sixth resistor is connected to the gate of the third NMOS transistor, and the other end of the sixth resistor is grounded. The source of the third NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, and the drain of the fourth NMOS transistor is connected to the output end. One end of the seventh resistor is connected to the power supply VDD, and the other end is connected to the drain of the third NMOS transistor. One end of the eighth resistor is connected to the power supply VDD, and the other end is connected to the output end. The fifth and sixth resistors form a voltage divider network for dividing a ramp voltage signal to drive the third NMOS transistor. The third NMOS transistor and the seventh resistor are used to control the on and off of the fourth NMOS transistor. The fourth NMOS transistor is used to reverse the output signal of the third NMOS transistor so that the output signal is in the same direction as the input signal.

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