Capacitor mismatch calibration method

Abstract

The invention relates to a capacitor mismatch calibration method, which comprises the following steps that: for each to-be-calibrated capacitor in a capacitor array, calibration is carried out successively from a low position to a high position, and the calibration of each to-be-calibrated capacitor is divided into a set high calibration link and a set low calibration link; the setting high calibration link comprises residual error sampling loop reset, capacitor array reset, setting high capacitance calibration, residual error sampling and setting high oversampling noise suppression, and is used for obtaining a setting high weight quantized value; the setting low calibration link comprises residual error sampling loop reset, capacitor array reset, setting low capacitance calibration, reset residual error sampling and setting low oversampling noise suppression, and is used for obtaining a setting low weight quantized value; and subtracting the set high-weight quantized value of the to-be-calibrated bit capacitor from the corresponding set low-weight quantized value, and averaging to obtain a weight quantized value without an offset error. On the basis of traditional foreground calibration, a noise shaping technology is introduced, so that the precision of capacitor weight calibration is higher.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a method for calibrating capacitor mismatch. Background Art

[0002] High-speed and high-precision analog-to-digital converters (ADCs) are the current development goals. In order to improve the overall energy efficiency of ADCs, the noise-shaping successive approximation register ADC (NS-SAR ADC) that combines noise shaping technology with a multi-bit quantizer has become a research hotspot.

[0003] However, the mismatch of the quantizer capacitor array has become the main factor limiting its performance. Due to the limitations of chip manufacturing processes, capacitor mismatch is inevitable. Although there are some solutions, such as foreground calibration, although they consume less resources, the performance improvement brought is limited. Especially after introducing noise shaping technology, the weak harmonic suppression ability limits the dynamic performance of ADCs. Another commonly used technology is dynamic element matching (DEM). This method reduces the impact of capacitor mismatch by dynamically adjusting the usage order of unit capacitors and improves the overall performance of ADCs. However, DEM requires additional digital control circuits, and its power consumption and complexity increase exponentially with the number of bits of the quantizer. Especially when the number of bits of the quantizer is large, the resource consumption is difficult to meet the requirements of on-chip implementation, and the additional delay and high-frequency noise will also affect the speed and accuracy of ADCs. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for calibrating capacitor mismatch, which realizes the suppression of quantization error and comparator noise during the calibration process, makes the accuracy of capacitor weight calibration higher, thereby reducing the bottleneck limitation of capacitor mismatch on the performance of ADCs, and has the advantages of low resource consumption and high harmonic suppression ability.

[0005] To achieve the above purpose, the present invention provides a method for calibrating capacitor mismatch, including:

[0006] For each capacitor to be calibrated in the capacitor array, calibration is performed successively from the low bit to the high bit, and the calibration of each capacitor to be calibrated is divided into a high-set calibration link and a low-set calibration link;

[0007] The high-set calibration link includes residual sampling loop reset, capacitor array reset, high-set capacitor calibration, residual sampling, and high-set oversampling noise suppression, and is used to obtain the high-set weight quantization value of the capacitor to be calibrated;

[0008] The low-set calibration link includes residual sampling loop reset, capacitor array reset, low-set capacitor calibration, reset residual sampling, and low-set oversampling noise suppression, and is used to obtain the low-set weight quantization value of the capacitor to be calibrated;

[0009] Subtract the set high - weight quantization value of the capacitor to be calibrated from the corresponding set low - weight quantization value and take the average to obtain the weight quantization value of the capacitor to be calibrated without offset error.

[0010] Optionally, the step of resetting the residual sampling loop specifically includes: connecting the upper and lower plates of the residual sampling capacitor of the residual sampling loop to the common - mode level simultaneously;

[0011] The step of resetting the capacitor array specifically includes: connecting the upper and lower plates of the capacitor array to the common - mode level simultaneously, making the voltage difference between the upper and lower plates of the capacitor array zero, then disconnecting the switch connecting the upper plate of the capacitor array to the common - mode level, and keeping the switch connecting the lower plate of the capacitor array to the common - mode level connected;

[0012] The step of residual sampling specifically includes: sampling the residual voltage of the upper plate of the capacitor array after the setting conversion is completed, and using the sampling result through the multi - input comparator for the next setting conversion of the capacitor to be calibrated.

[0013] Optionally, the step of setting high - capacitance calibration specifically includes:

[0014] When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated high, and connect the lower plate of the capacitor to be calibrated to the positive reference voltage of the analog - to - digital converter;

[0015] Then keep the capacitors higher than the capacitor to be calibrated unchanged, and gradually convert the capacitors lower than the capacitor to be calibrated from high to low, and output the set high - weight calibration value of the capacitor to be calibrated.

[0016] Optionally, the set high - weight calibration value W i,f1 of the capacitor to be calibrated is expressed as follows:

[0017]

[0018] In the formula, W j is the weight value of the j - th capacitor, B j,f1 is the output code word of the j - th capacitor, and V os is the circuit offset value.

[0019] Optionally, the step of setting high - oversampling noise suppression specifically includes:

[0020] Repeat the steps of resetting the capacitor array, setting high - capacitance calibration, and residual sampling N times, and record the results of each conversion;

[0021] Pass the results through a mean filter to obtain the final set high - weight quantization value of the capacitor to be calibrated.

[0022] Optionally, the set high weight quantization value W i,f1,ns has the following expression:

[0023]

[0024] In the formula, N is the number of repetitions, W j is the weight value of the j-th capacitor, B j,f1,n is the output codeword of the j-th capacitor during the n-th conversion, V os is the circuit offset value.

[0025] Optionally, the steps of the set low capacitor calibration specifically include:

[0026] When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated low, and connect the lower plate of the capacitor to be calibrated to the negative reference voltage of the analog-to-digital converter;

[0027] Then keep the capacitors higher than the capacitor to be calibrated unchanged, and the capacitors lower than the capacitor to be calibrated are sequentially converted from high to low to output the set high weight calibration value of the capacitor to be calibrated.

[0028] Optionally, the set low weight calibration value W i,f0 of the capacitor to be calibrated has the following expression:

[0029]

[0030] In the formula, W j is the weight value of the j-th capacitor, B j,f0 is the output codeword of the j-th capacitor, V os is the circuit offset value.

[0031] Optionally, the steps of the set low oversampling noise suppression specifically include:

[0032] Repeat the steps of resetting the capacitor array, the set low capacitor calibration, and the residual sampling M times, and record the results of each conversion;

[0033] Pass the results through a mean filter to obtain the final set low weight quantization value of the capacitor to be calibrated.

[0034] Optionally, the set low weight quantization value W i,f0,ms has the following expression:

[0035]

[0036] In the formula, M is the number of repetitions, W j is the weight value of the j-th capacitor, B j,f0,n is the output codeword of the j-th capacitor during the m-th conversion, Vos is the circuit offset value.

[0037] In a capacitance mismatch calibration method provided by the present invention, by introducing a noise shaping technique on the basis of traditional front-end calibration, combining the advantages of the noise shaping technique and the traditional front-end calibration algorithm, a new noise shaping capacitance mismatch calibration method is proposed to suppress the quantization error and comparator noise during the calibration process, making the accuracy of capacitance weight calibration higher, thereby reducing the bottleneck limitation of capacitance mismatch on the ADC performance, and having the advantages of low resource consumption and high harmonic suppression ability. At the same time, combined with the circuit structure and timing requirements of the noise shaping successive approximation analog-to-digital converter, and ingeniously combining the working principle of the calibration method in the design of the present invention, the key control timing is designed to enable the calibration process to be achieved with relatively low on-chip resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0039] Figure 1 is a flowchart of the capacitance mismatch calibration method provided by an embodiment of the present invention;

[0040] Figure 2 is a circuit schematic diagram of the set high calibration link provided by an embodiment of the present invention;

[0041] Figure 3 is a circuit schematic diagram of the set low calibration link provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. To make the objectives, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions of the implementation of the present invention. Any modification of the structure, change of the proportional relationship, or adjustment of the size, in the case of being the same or similar to the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention.

[0043] As used in the present invention, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. As used in the present invention, the term "or" is generally used in the sense of including "and / or" unless the context clearly dictates otherwise. As used in the present invention, the term "several" is generally used in the sense of including "at least one" unless the context clearly dictates otherwise. As used in the present invention, the term "at least two" is generally used in the sense of including "two or more" unless the context clearly dictates otherwise.

[0044] Please refer to Figure 1 , an embodiment of the present invention provides a capacitance mismatch calibration method, including:

[0045] For each capacitance to be calibrated in the capacitance array, calibration is performed successively from the low bit to the high bit, and the calibration of each capacitance to be calibrated is divided into a high setting calibration link and a low setting calibration link;

[0046] The high setting calibration link includes residual sampling loop reset, capacitance array reset, high setting capacitance calibration, residual sampling, and high setting oversampling noise suppression, and is used to obtain the high setting weight quantization value of the capacitance to be calibrated;

[0047] The low setting calibration link includes residual sampling loop reset, capacitance array reset, low setting capacitance calibration, reset residual sampling, and low setting oversampling noise suppression, and is used to obtain the low setting weight quantization value of the capacitance to be calibrated;

[0048] Subtract and average the high setting weight quantization value and the corresponding low setting weight quantization value of the capacitance to be calibrated to obtain the weight quantization value without offset error of the capacitance to be calibrated.

[0049] Based on the traditional front-end calibration, the present invention introduces the noise shaping technology, combines the advantages of the noise shaping technology and the traditional front-end calibration algorithm, and proposes a new noise shaping capacitance mismatch calibration method to realize the suppression of quantization error and comparator noise in the calibration process, making the accuracy of capacitance weight calibration higher, thereby reducing the bottleneck limitation of capacitance mismatch on the ADC performance, and having the advantages of low resource consumption and high harmonic suppression ability. At the same time, combined with the circuit structure and timing requirements of the noise shaping successive approximation analog-to-digital converter, the working principle of the calibration method in the design of the present invention is skillfully combined, and the key control timing is designed to enable the calibration process to be realized with relatively low on-chip resource consumption.

[0050] In this embodiment, for each capacitor to be calibrated in the capacitor array, calibration is performed successively from the low bit to the high bit. The calibration of each capacitor to be calibrated is divided into a high setting calibration link and a low setting calibration link. It should be noted that the present invention does not limit the sequence of the high setting calibration link and the low setting calibration link. The high setting calibration link can be performed first, and then the low setting calibration link can be performed. Alternatively, the low setting calibration link can be performed first, and then the high setting calibration link can be performed. Finally, the high setting weight quantization value and the low setting weight quantization value obtained from the two calibration links are subtracted and averaged to obtain the weight quantization value without offset error of the capacitor to be calibrated.

[0051] Specifically, the high setting calibration link includes the following steps:

[0052] S101. Reset the residual sampling loop 100: Connect the upper and lower plates of the residual sampling capacitor of the residual sampling loop 100 to the common mode level simultaneously.

[0053] S102. Reset the capacitor array: Connect the upper and lower plates of the capacitor array to the common mode level simultaneously, so that the voltage difference between the upper and lower plates of the capacitor array is 0. Then, disconnect the switch connecting the upper plate of the capacitor array to the common mode level, and keep the switch connecting the lower plate of the capacitor array to the common mode level connected.

[0054] S103. High setting capacitor calibration: When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated to high, and connect the lower plate of the capacitor to be calibrated to the positive reference voltage of the analog-to-digital converter.

[0055] Then, keep the capacitors higher than the capacitor to be calibrated unchanged, and gradually convert the capacitors lower than the capacitor to be calibrated from high to low, and output the high setting weight calibration value of the capacitor to be calibrated.

[0056] S104. Residual sampling: Sample the residual voltage of the upper plate of the capacitor array after the setting conversion is completed, and use the sampling result through the multi-input comparator 200 for the next setting conversion of the capacitor to be calibrated.

[0057] S105. High setting oversampling noise suppression: Repeat the steps of resetting the capacitor array, high setting capacitor calibration, and residual sampling N times, and record the results of each conversion.

[0058] The results are passed through a mean filter to obtain the final high setting weight quantization value of the capacitor to be calibrated.

[0059] As Figure 2 shown, when calibrating the b i -bit capacitor, first set the capacitor b to be calibrated i, the capacitor b of the position to be calibrated i The lower plate is connected to the positive reference voltage of the ADC, and then, the capacitors higher than b i remain unchanged, and the capacitors lower than the position to be calibrated are successively converted from high to low, and the output result is the set high-weight calibration value of the capacitor b of the position to be calibrated i For example, the weight value of the capacitor b5 to be calibrated is 15.5, and its low-weight distribution is 1, 2, 2, 4, 8, where one of the 2s is a redundant weight. First, determine whether the weight value 15.5 of the capacitor b5 to be calibrated is greater than 0. If it is greater, subtract the weight 8 of the capacitor b4. At this time, the output codeword of the capacitor b4 is 1. If it is less, add the weight 8, and the output codeword of the capacitor b4 is 0; then compare the result with 0 again. If it is greater, subtract the weight 4 of the capacitor b3. At this time, the output codeword of the capacitor b3 is 1. Otherwise, add the weight 4, and the output codeword of the capacitor b3 is 0. Repeat this process until the comparison of the lowest-bit capacitor is completed, and finally output the output codeword corresponding to each capacitor.

[0060] In this embodiment, the set high-weight calibration value W i,f1 of the capacitor of the position to be calibrated is expressed as follows:

[0061]

[0062] In the formula, W j is the weight value of the jth capacitor, B j,f1 is the output codeword of the jth capacitor, and V os is the circuit offset value.

[0063] The set high-weight quantization value W i,f1,ns is expressed as follows:

[0064]

[0065] In the formula, N is the number of repetitions, W j is the weight value of the jth capacitor, B j,f1,n is the output codeword of the jth capacitor at the nth conversion, and V os is the circuit offset value.

[0066] In order to reduce the influence of circuit offset on the error weight, it is also necessary to obtain the set low-weight quantization value of the capacitor b i of the position to be calibrated. Compared with the process of obtaining the set high-weight quantization value, the process of obtaining the set low-weight quantization value only needs to change the above steps of set high-capacitor calibration to set low-capacitor calibration.

[0067] Specifically, the set low-calibration link includes the following steps:

[0068] S201. Reset the residual sampling loop 100: Connect the upper and lower plates of the residual sampling capacitor of the residual sampling loop 100 to the common-mode level simultaneously;

[0069] S202. Reset the capacitor array: Connect the upper and lower plates of the capacitor array to the common-mode level simultaneously, so that the voltage difference between the upper and lower plates of the capacitor array is 0, and then disconnect the switch connecting the upper plate of the capacitor array to the common-mode level, and keep the switch connecting the lower plate of the capacitor array to the common-mode level connected;

[0070] S203. Set low capacitance calibration: When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated low, and connect the lower plate of the capacitor to be calibrated to the negative reference voltage of the analog-to-digital converter;

[0071] Then keep the capacitors higher than the capacitor to be calibrated unchanged, and gradually convert the capacitors lower than the capacitor to be calibrated from high to low, and output the set high weight calibration value of the capacitor to be calibrated;

[0072] S204. Residual sampling: Sample the residual voltage of the upper plate of the capacitor array after the set conversion is completed, and use the sampling result through the multi-input comparator 200 for the next set conversion of the capacitor to be calibrated;

[0073] S205. Set low oversampling noise suppression: Repeat the steps of resetting the capacitor array, setting low capacitance calibration, and residual sampling M times, and record the results of each conversion;

[0074] Pass the results through a mean filter to obtain the final set low weight quantization value of the capacitor to be calibrated;

[0075] In this embodiment, the set low weight calibration value W i,f0 of the capacitor to be calibrated is expressed as follows:

[0076]

[0077] In the formula, W j is the weight value of the jth capacitor, B j,f0 is the output code word of the jth capacitor, and V os is the circuit offset value.

[0078] The set low weight quantization value W i,f0,ms is expressed as follows:

[0079]

[0080] In the formula, M is the number of repetitions, W j is the weight value of the jth capacitor, B j,f0,nis the output code word of the j-th capacitor during the m-th conversion, V os is the circuit offset value.

[0081] Among them, the present invention does not impose any restrictions on the values of M and N, but they must be positive integers greater than 1.

[0082] Finally, subtract the set high-weight quantization value of the to-be-calibrated bit capacitor from the corresponding set low-weight quantization value and take the average to obtain the weight quantization value W without offset error of the to-be-calibrated bit capacitor i , and its expression is as follows:

[0083]

[0084] The reason why the present invention needs to subtract the set high-weight quantization value of the to-be-calibrated bit capacitor from the corresponding set low-weight quantization value and take the average is also to reduce the influence of circuit offset on the error weight and further improve the accuracy of capacitor weight calibration. After the weight calibration of the i-th capacitor is completed, repeat the above operation to calibrate the weight of the i + 1-th capacitor until the calibration of the highest-bit capacitor is completed. When calibrating the weight of the i + 1-th capacitor, during the calculation of the weight quantization value, the weight value of the i-th capacitor should be calculated using the weight quantization value without offset error that has been calibrated.

[0085] In summary, the embodiment of the present invention provides a capacitor mismatch calibration method, which combines the advantages of noise shaping technology and traditional front-end calibration algorithms, realizes the suppression of quantization error and comparator noise during the calibration process, makes the accuracy of capacitor weight calibration higher, thereby reducing the bottleneck limitation of capacitor mismatch on the ADC performance, and has the advantages of low resource consumption and high harmonic suppression ability. At the same time, combined with the circuit structure and timing requirements of the noise shaping successive approximation analog-to-digital converter, the working principle of the calibration method in the design of the present invention is skillfully combined, and the key control timing is designed so that the calibration process can be realized with relatively low on-chip resource consumption.

[0086] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations fall within the scope of the present invention and its equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A capacitance mismatch calibration method, characterized in that Including: For each capacitor to be calibrated in the capacitor array, calibration is performed successively from the low bit to the high bit. The calibration of each capacitor to be calibrated is divided into a high-setting calibration link and a low-setting calibration link; The high-setting calibration link includes residual sampling loop reset, capacitor array reset, high-setting capacitor calibration, residual sampling, and high-setting oversampling noise suppression, which are used to obtain the high-setting weighted quantization value of the capacitor to be calibrated; The low-setting calibration link includes residual sampling loop reset, capacitor array reset, low-setting capacitor calibration, reset residual sampling, and low-setting oversampling noise suppression, which are used to obtain the low-setting weighted quantization value of the capacitor to be calibrated; Subtract the high-setting weighted quantization value of the capacitor to be calibrated from the corresponding low-setting weighted quantization value and take the average to obtain the weighted quantization value without offset error of the capacitor to be calibrated.

2. The capacitance mismatch calibration method according to claim 1, wherein The steps of the residual sampling loop reset specifically include: connecting the upper and lower plates of the residual sampling capacitor of the residual sampling loop to the common mode level at the same time; The steps of the capacitor array reset specifically include: connecting the upper and lower plates of the capacitor array to the common mode level at the same time, so that the voltage difference between the upper and lower plates of the capacitor array is 0, and then disconnecting the switch connecting the upper plate of the capacitor array to the common mode level, and keeping the switch connecting the lower plate of the capacitor array to the common mode level connected; The steps of the residual sampling specifically include: sampling the residual voltage of the upper plate of the capacitor array after the setting conversion is completed, and using the sampling result through the multi-input comparator for the next setting conversion of the capacitor to be calibrated.

3. The capacitance mismatch calibration method according to claim 1, wherein The steps of the high-setting capacitor calibration specifically include: When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated high, and connect the lower plate of the capacitor to be calibrated to the positive reference voltage of the analog-to-digital converter; Then keep the capacitors higher than the capacitor to be calibrated unchanged, and gradually convert the capacitors lower than the capacitor to be calibrated from high to low, and output the high-setting weighted calibration value of the capacitor to be calibrated.

4. The capacitance mismatch calibration method according to claim 3, wherein The set high-weight calibration value W of the capacitance at the position to be calibrated i,f1 has the following expression: Where, W j is the weight value of the j-th capacitor, B j,f1 is the output codeword of the j-th capacitor, and V os is the circuit offset value.

5. The capacitance mismatch calibration method according to claim 1, wherein The steps of the high-setting oversampling noise suppression specifically include: Repeat the steps of the capacitor array reset, the high-setting capacitor calibration, and the residual sampling N times, and record the results of each conversion; Pass the results through a mean filter to obtain the final high-setting weighted quantization value of the capacitor to be calibrated.

6. The capacitance mismatch calibration method according to claim 5, wherein The set high-weight quantization value W i,f1,ns has the following expression: where N is the number of repetitions, W j is the weight value of the j-th capacitor, B j,f1,n is the output codeword of the j-th capacitor at the n-th conversion, V os is the circuit offset value.

7. The capacitance mismatch calibration method according to claim 1, wherein The steps of the low-setting capacitor calibration specifically include: When calibrating the capacitor to be calibrated, first set the capacitor to be calibrated low, and connect the lower plate of the capacitor to be calibrated to the negative reference voltage of the analog-to-digital converter; Then keep the capacitors higher than the capacitor to be calibrated unchanged, and gradually convert the capacitors lower than the capacitor to be calibrated from high to low, and output the high-setting weighted calibration value of the capacitor to be calibrated.

8. The capacitance mismatch calibration method according to claim 7, characterized in that, The set low-weight calibration value W of the capacitance at the position to be calibrated i,f0 has the following expression: Where W j is the weight value of the j-th capacitor, B j,f0 is the output codeword of the j-th capacitor, and V os is the circuit offset value.

9. The capacitance mismatch calibration method according to claim 1, characterized in that The steps of the low-setting oversampling noise suppression specifically include: Repeat the steps of the capacitor array reset, the low-setting capacitor calibration, and the residual sampling M times, and record the results of each conversion; Pass the results through a mean filter to obtain the final low-setting weighted quantization value of the capacitor to be calibrated.

10. The capacitance mismatch calibration method according to claim 9, wherein The set low-weight quantization value W i,f0,ms has the following expression: Where M is the number of repetitions, and W j is the weight value of the j-th capacitor, B j,f0,n is the output codeword of the j-th capacitor at the m-th conversion, and V os is the circuit offset value.

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