NTB cross-host domain verification system and method, computer equipment and medium

Abstract

The invention relates to the technical field of computers, and discloses an NTB cross-host-domain verification system and method, computer equipment and a medium, the NTB cross-host-domain verification system comprises a PCIe system model, an input scheduling module, a cross-domain routing module, a chip implementation module and a comparison module, the PCIe system model is connected with the input scheduling module, and the cross-domain routing module is connected with the chip implementation module. The input scheduling module is connected with the cross-domain routing module and the chip implementation module, the cross-domain routing module and the chip implementation module are connected to the comparison module, and the cross-host-domain function of the NTB chip can be quickly and comprehensively verified.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a verification system, method, computer device, and medium for NTB across host domains. Background Art

[0002] In the field of computer system interconnection, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) technology has become the mainstream bus standard due to its high performance and low latency characteristics. As a special bridging device in the PCIe system, NTB (Non-Transparent Bridge) plays a key role in realizing isolated communication between two independent PCIe domains. Different from traditional transparent bridges, NTB supports two independent systems or subsystems to maintain logical independence while being physically connected via a PCIe link through functions such as address translation, address filtering, and configuration space isolation.

[0003] In a PCIe multi-host scenario, each host is in an access isolation state, and cross-domain access must be achieved through NTB. However, the current PCIe protocol does not make a unified specification for the specific implementation details of NTB, resulting in significant differences in the technical details of NTB implementation solutions on the market. NTBs designed by different manufacturers vary in address translation algorithms, configuration space management logics, data transfer protocols, etc., which pose a huge challenge to the verification work of NTB. Existing NTB module verification is usually based on BT (Bus Functional Model). From this verification perspective, only the address and ID conversion processes can be observed, and it is impossible to deeply judge whether memory access has truly achieved cross-domain success, nor is it easy to verify the actual effect of resource isolation. Summary of the Invention

[0004] Based on this, in view of the problem of poor existing NTB verification effects, a verification system, method, computer device, and medium for NTB across host domains are proposed.

[0005] The first aspect of this application provides a verification system for NTB across host domains, including a PCIe system model, an input scheduling module, a cross-domain routing module, a chip implementation module, and a comparison module. Among them, the PCIe system model is connected to the input scheduling module, the input scheduling module is connected to the cross-domain routing module and the chip implementation module, and the cross-domain routing module and the chip implementation module are connected to the comparison module; The PCIe system model is configured with a number of virtual host modules, each virtual host module is respectively connected to the input scheduling module, the states of the virtual host modules are respectively initialized, test packets are randomly generated or generated according to a preset test rule, and are input into the input scheduling module; The input scheduling module schedules and receives different test packets, and sequentially synchronously sends each test packet to the cross-domain routing module and the chip implementation module; The cross-domain routing module receives the test packet sent by the input scheduling module, performs address conversion on the test packet according to a preset simulation conversion method, outputs a first converted packet, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; The chip implementation module receives the test packet sent by the input scheduling module, performs address conversion on the test packet according to the actual design code of the NTB chip, outputs a second converted packet, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; A plurality of sub-comparison modules configured based on different virtual host modules are preset in the comparison module, the first converted packet and the second converted packet are compared in the sub-comparison module corresponding to the destination virtual host module, and if the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module fails the NTB cross-host domain verification.

[0006] Further, the step of the PCIe system model performing initialization settings on the states of the virtual host modules respectively includes: The PCIe system model receives global configuration parameters through the UVM command line parameter passing mechanism; According to the global configuration parameters, host numbers and corresponding address spaces are allocated to the virtual host modules; An ID domain id_base~id_limit is allocated to each virtual host module, where id_base is the ID of the virtual host module, and id_limit is the upper limit value of the ID of the device attached to the virtual host module; An address domain addr_base ~ addr_limit is allocated to each virtual host module, where addr_base ~addr_limit is the address allocated to the virtual host module and the device attached to the virtual host module; The ID domain and address domain of each virtual host module are saved into the global configuration parameters to obtain updated global configuration parameters; According to the updated global configuration parameters, the mapping configuration of the IDs and addresses between different virtual host modules is performed to obtain address mapping table information; Synchronously update the address mapping table information to the cross-domain routing module and the chip implementation module, where the cross-domain routing module obtains the updated address mapping table information through table entry instances, and the chip implementation module obtains the updated address mapping table information through CSR chain writing tables.

[0007] Furthermore, the step that the PCIe system model performs to allocate host numbers and corresponding address spaces to each virtual host module according to the global configuration parameters further includes: Reserve a hole address space, which is used to test the conversion processing of the hole address carried in the test packet.

[0008] Furthermore, when the test packet is a REQ packet, the step that the PCIe system model performs to randomly generate a test packet includes: The PCIe system model randomly selects an address under a virtual host module as the source address; Randomly select an address under another virtual host module as the destination address; Generate a REQ packet according to the source address and the destination address.

[0009] Furthermore, when the test packet is a CPL packet, the step that the PCIe system model performs to randomly generate a test packet includes: The PCIe system model randomly selects an ID under a virtual host module as the request ID; Randomly select an ID under a virtual host module as the completion ID, where the completion ID is different from the request ID; Generate the CPL packet according to the request ID and the completion ID.

[0010] Furthermore, the step that the input scheduling module schedules to receive different test packets and sequentially synchronously sends each test packet to the cross-domain routing module and the chip implementation module includes: The input scheduling module schedules to receive different test packets and classifies them according to the virtual host module that sends the test packet; For test packets from the same virtual host module, sort different test packets according to the generation order of the test packets; For test packets from different virtual host modules, use a preset fair scheduling strategy for round-robin scheduling.

[0011] Furthermore, the chip implementation module determines whether the idle signal has not been sent to the PCIe system model for a preset duration, where the idle signal is sent by the chip implementation module to the PCIe system model after completing the output of the second conversion packet. If so, send a stop packet sending instruction to the PCIe system model, so that the PCIe system model pauses sending new test packets to the chip implementation module.

[0012] The second aspect of this embodiment provides a method for verifying NTB across host domains. The method for verifying NTB across host domains is applied to the above input scheduling module, and includes: Schedule to receive different test packets. Among them, the test packets are randomly generated by the PCIe system model. A number of virtual host modules are configured in the PCIe system model, and each virtual host module is respectively connected to the input scheduling module, and the states of each virtual host module are respectively initialized. Sequentially synchronously send each test packet to the cross-domain routing module and the chip implementation module, so that the cross-domain routing module receives the test packet sent by the input scheduling module, and performs address conversion on the test packet according to a preset simulation conversion method, outputs a first converted packet, and inputs it to the sub-comparison module corresponding to the destination virtual host module of the first converted packet in the comparison module; and enables the chip implementation module to receive the test packet sent by the input scheduling module, and performs address conversion on the test packet according to the actual design code of the NTB chip, outputs a second converted packet, and inputs it to the sub-comparison module corresponding to the destination virtual host module of the second converted packet in the comparison module; and a plurality of sub-comparison modules configured based on different virtual host modules are preset in the comparison module, and the first converted packet and the second converted packet are compared in the sub-comparison module corresponding to the destination virtual host module. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module fails the NTB cross-host domain verification.

[0013] The third aspect of this embodiment provides a computer device. The device includes a memory and a processor. When the computer program stored in the memory is executed by the processor, the processor is caused to execute the steps of the above method for verifying NTB across host domains.

[0014] The fourth aspect of this embodiment provides a computer-readable storage medium, storing a computer program, and when the computer program is executed by a processor, the processor is caused to execute the steps of the above method for verifying NTB across host domains.

[0015] The NTB cross-host domain verification system of the present application can quickly and comprehensively verify the cross-host domain functions of NTB chips. The PCIe system model can generate diverse test packets, covering various possible cross-domain access scenarios. Combining with the efficient scheduling mechanism of the input scheduling module, it can conduct a large number of tests on the chip in a short time, greatly improving the verification efficiency of the NTB cross-host domain. The design of the comparison module enables accurate positioning of the specific link with problems in the chip implementation module when the verification fails. Through the detailed packet comparison difference information, technicians can intuitively understand the deviation of the chip from the ideal simulation conversion method during the address conversion process, which helps to quickly find errors or defects in the chip design code, provides support for chip optimization and improvement, and shortens the chip R & D cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0017] Among them: Figure 1 is the structural block diagram of the NTB cross-host domain verification system in an embodiment; Figure 2 is the flowchart of the NTB cross-host domain verification method in an embodiment; Figure 3 is the structural block diagram of a computer device in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0019] As Figure 1 shown, in an embodiment, a NTB cross-host domain verification system is provided, including a PCIe system model 1, an input scheduling module 2, a cross-domain routing module 3, a chip implementation module 4, and a comparison module 5. Among them, the PCIe system model 1 is connected to the input scheduling module 2, the input scheduling module 2 is connected to the cross-domain routing module 3 and the chip implementation module 4, and the cross-domain routing module 3 and the chip implementation module 4 are connected to the comparison module 5; The PCIe system model 1 is configured with a number of virtual host modules 11. Each virtual host module 11 is respectively connected to the input scheduling module 2, and the states of each virtual host module 11 are respectively initialized, test packets are randomly generated or test packets are generated according to preset test rules, and are input to the input scheduling module 2; The input scheduling module 2 schedules and receives different test packets, and sequentially synchronously sends each test packet to the cross-domain routing module 3 and the chip implementation module 4; The cross-domain routing module 3 receives the test packet sent by the input scheduling module 2, performs address conversion on the test packet according to a preset simulation conversion method, outputs a first converted packet, and inputs it to the sub-comparison module 51 corresponding to the destination virtual host module 11 in the comparison module 5; The chip implementation module 4 receives the test packet sent by the input scheduling module 2, performs address conversion on the test packet according to the actual design code of the NTB chip, outputs a second converted packet, and inputs it to the sub-comparison module 51 corresponding to the destination virtual host module 11 in the comparison module 5; A plurality of sub-comparison modules 51 configured based on different virtual host modules 11 are preset in the comparison module 5. The first converted packet and the second converted packet are compared in the sub-comparison module 51 corresponding to the destination virtual host module 11. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module 4 fails the verification of the NTB cross-host domain.

[0020] In this embodiment, inside the PCIe system model 1, there are multiple virtual host modules 11. Each virtual host module 11 is connected to the input scheduling module 2. In the system initialization stage, according to the preset initialization rules, an independent address space, host number, etc. are configured for each virtual host module 11 to simulate the operating environments of different hosts in a real PCIe system.

[0021] In specific implementation, the virtual host module 11 randomly generates test packets, or generates test packets according to preset test rules. For example, when simulating a cross-domain data reading scenario, the virtual host module 11 generates a request packet (REQ packet) that conforms to the PCIe protocol specification. The source address is randomly selected from the address space of this virtual host module 11, and the destination address is selected from the address space of other virtual host modules 11 to simulate a real cross-host domain access request. In addition, for some specific test requirements, the virtual host module 11 can generate test packets with special requirements according to preset rules to comprehensively detect the function of NTB cross-domain access.

[0022] The input scheduling module 2 adopts the First-In-First-Out (FIFO) or priority scheduling algorithm to schedule and manage different received test messages. After the virtual host module 11 generates a test message, it will send it to the input scheduling module 2. The input scheduling module 2 will sequentially check the message queue and synchronously send each test message to the cross-domain routing module 3 and the chip implementation module 4. For example, when the system simultaneously receives test messages from multiple virtual host modules 11, the input scheduling module 2 will ensure that each message can be timely and completely transmitted to the subsequent processing modules according to the receiving order or priority of the messages, avoiding message loss or disorder in the processing order.

[0023] After receiving the test message sent by the input scheduling module 2, the cross-domain routing module 3 performs an address conversion operation according to the preset analog conversion method. The module internally stores a pre-configured address mapping table, which records the corresponding relationships of address conversions between different virtual host modules 11. For example, when receiving a test message with a destination address of virtual host module A, the cross-domain routing module 3 will look up the corresponding conversion rule in the address mapping table, convert the original address of the message into an address format recognizable by virtual host module A, and generate the first converted message. Subsequently, the cross-domain routing module 3 inputs it into the corresponding sub-comparison module 51 in the comparison module 5 according to the host number of the destination virtual host module 11 of the first converted message. Through this processing method, it simulates the address conversion process of the NTB device in the ideal state for comparison with the actual processing results of the subsequent chip. Specifically, the cross-domain routing module 3 makes processing judgments based on information such as the type, address, ID, etc. of the input test message; after confirming that message conversion is required, it traverses the address mapping table, uses the original domain information in the test message to find the destination domain information, and replaces the address and / or ID of the converted message with the destination address and / or ID, and outputs it to the comparison module 5.

[0024] After receiving the test message sent by the input scheduling module 2, the chip implementation module 4 processes it according to the actual design code of the NTB chip. The chip implementation module 4 simulates the address conversion logic of the NTB chip in the actual operating environment by calling the driver program or simulation model of the NTB chip. Since the NTB chips of different manufacturers have differences in design code and implementation details, the chip implementation module 4 needs to be adapted according to the specific chip model. For example, for a certain model of NTB chip, its address conversion may involve read and write operations of multiple registers and complex algorithm operations. The chip implementation module 4 will strictly execute the corresponding code logic according to the design document of the chip, perform address conversion on the test message, and generate the second converted message. Then, similarly, according to the host number of the destination virtual host module 11 of the second converted message, it inputs it into the corresponding sub-comparison module 51 in the comparison module 5.

[0025] The comparison module 5 internally presets multiple sub-comparison modules 51, and each sub-comparison module 51 corresponds to a virtual host module 11. During the actual verification process, when the first conversion message and the second conversion message based on the same test message are input into the sub-comparison module 51 corresponding to the destination virtual host module 11, the sub-comparison module 51 will perform a bit-by-bit comparison on each field of the two conversion messages. The comparison content includes but is not limited to key parameters such as address information, data content, and control flags. If the two messages are exactly the same in all comparison fields, it is determined that the NTB cross-host domain processing function of the chip implementation module 4 meets the expectations in this test scenario; if there is any field inconsistency, it is determined that the comparison result does not meet the preset consistency setting, indicating that there are problems with the address conversion or other related functions of the chip implementation module 4 in the NTB cross-host domain and the verification fails. At this time, the sub-comparison module 51 will record the detailed comparison difference information and generate a verification failure report for technicians to conduct problem troubleshooting and analysis, such as checking whether the implementation of the cross-domain routing module 3 is consistent with that of the chip implementation module 4; checking whether the code implementation of the chip implementation module 4 is consistent with the preset test plan; checking whether the abnormal content of the test message causes the output of the cross-domain routing module 3 and the chip implementation module 4 to be inconsistent.

[0026] Through the NTB cross-host domain verification system of this embodiment, the cross-host domain function of the NTB chip can be verified quickly and comprehensively. The PCIe system model 1 can generate diverse test messages covering various possible cross-domain access scenarios. Combined with the efficient scheduling mechanism of the input scheduling module 2, a large number of tests can be performed on the chip in a short time, greatly improving the verification efficiency of the NTB cross-host domain. The design of the comparison module 5 enables accurate positioning of the specific link where the chip implementation module 4 has problems when the verification fails. Through the detailed message comparison difference information, technicians can intuitively understand the deviation of the chip from the ideal simulation conversion method during the address conversion process, which helps to quickly find errors or defects in the chip design code, provides support for the optimization and improvement of the chip, and shortens the chip R & D cycle.

[0027] In a specific embodiment, the step of the PCIe system model 1 performing initialization settings on the states of the virtual host modules 11 respectively includes: The PCIe system model 1 receives global configuration parameters through the UVM command line parameter passing mechanism; According to the global configuration parameters, host numbers and corresponding address spaces are allocated to the virtual host modules 11; An ID domain id_base~id_limit is allocated to each virtual host module 11, where id_base is the ID of the virtual host module 11 and id_limit is the upper limit value of the ID of the device attached to the virtual host module 11; An address domain addr_base ~ addr_limit is allocated to each virtual host module 11, where addr_base ~ addr_limit is the address allocated to the virtual host module 11 and the devices attached to the virtual host module 11. The ID domain and address domain of each virtual host module 11 are saved into the global configuration parameters to obtain updated global configuration parameters. According to the updated global configuration parameters, the ID and address between different virtual host modules 11 are mapped and configured to obtain address mapping table information. The address mapping table information is synchronously updated to the cross-domain routing module 3 and the chip implementation module 4. Among them, the cross-domain routing module 3 obtains the updated address mapping table information through table entry instances, and the chip implementation module 4 obtains the updated address mapping table information through csr chain write tables.

[0028] In this embodiment, the PCIe system model 1 uses a general UVM command-line parameter passing mechanism to receive global configuration parameters. Through UVM, various configuration information required for the operation of the external input system can be obtained, such as global configuration parameters such as the number of hosts and the size of the address space.

[0029] According to the received global configuration parameters, the PCIe system model 1 creates several virtual host modules, assigns a unique host number to each virtual host module 11, and divides the corresponding address space. For example, if there are 3 virtual host modules set in the parameters, they are assigned numbers A, B, and C in sequence, and address spaces of 1MB, 2MB, and 3MB are respectively assigned according to preset rules (such as by proportion or specified size) to simulate the resource allocation of different hosts in a real PCIe system.

[0030] An ID domain is determined for each virtual host module 11, that is, id_base and id_limit are specified. id_base serves as the ID identifier of the virtual host module 11 itself to distinguish different hosts; id_limit limits the upper limit value of the ID of the devices attached to the virtual host module 11. For example, if the id_base of virtual host module A is set to 10 and the id_limit is set to 30, it means its own ID is 10, and the maximum ID of the devices it connects to does not exceed 30; the id_base of virtual host module B is set to 40 and the id_limit is set to 60.

[0031] For each virtual host module 11, an address range addr_base~addr_limit is allocated. This address range covers the addresses that can be used by the virtual host module 11 itself and the devices connected to it. For example, if the address range of virtual host module A is set to h100~h200, then this host and the devices connected to it will use the addresses within this range for data transmission and identification during communication; the address range of virtual host module B is set to h400~h600.

[0032] Save the ID domain and address domain information of each virtual host module 11 to the global configuration parameters and update them. The updated global configuration parameters contain the detailed and complete configuration information of each virtual host module.

[0033] Based on the updated global configuration parameters, the PCIe system model 1 configures the mapping of IDs and addresses between different virtual host modules 11. By means of rules preset manually, the corresponding relationship between different host IDs and addresses is established to generate address mapping table information. For example, it is stipulated that a certain address segment of virtual host module A corresponds to a specific ID identifier of virtual host module B, and a certain address segment of virtual host module B corresponds to a specific ID identifier of virtual host module A, clarifying the address conversion logic during cross-domain access.

[0034] Synchronously update the generated address mapping table information to the cross-domain routing module 3 and the chip implementation module 4 respectively. The cross-domain routing module 3 obtains the updated address mapping table information through table entry instances, that is, creates a special data structure (table entry instance) to store and manage the address mapping relationship, so as to quickly search and convert addresses when processing packets; the chip implementation module 4 obtains the information through writing tables in the CSR (control / status register) chain, and writes the address mapping table information into the internal storage structure of the chip by operating on relevant registers, enabling it to perform operations such as address conversion based on this information.

[0035] Furthermore, the global configuration parameters can also be modified in real time during the operation of the verification system, such as reallocating the address space of the virtual host module 11, adjusting the ID domain range, etc., to simulate the dynamic change scenarios of system configuration in actual applications. It should be noted that before performing the dynamic modification operation of the address mapping table, it is first necessary to confirm that the packets related to the expected modification content in the current system have successfully completed the process of looking up the address mapping table. After confirming that the preconditions are met, start synchronously updating the table entries in the cross-domain routing module 3 and the chip implementation module 4. After completing the update of the address mapping table, start sending the modified test packets to ensure that the test packets are consistent and there is no packet loss in the middle. If it cannot be ensured that the modified packets have been successfully forwarded, at this time, it is necessary to anticipate the possible situation of packets being discarded by the routing. To avoid errors in the verification environment, it is necessary to clean the first-in-first-out queue (FIFO) used for comparison in the comparison module 5 to eliminate the hidden danger of packet comparison errors caused by possible packet loss and ensure the stability and accuracy of the verification environment.

[0036] In a specific embodiment, the PCIe system model 1 performs the step of allocating host numbers and corresponding address spaces to each virtual host module 11 according to the global configuration parameters, and further includes: Reserving a hole address space, which is used to test the conversion processing of the hole address carried in the test packet.

[0037] In this embodiment, after allocating the basic address space for each virtual host module 11, the PCIe system model 1 will reserve a certain hole address space in these address spaces. The reserved hole address space can be discontinuous address segments. By reserving the hole address space, it is possible to simulate the abnormal address situations that may occur in actual applications, enabling the verification system to comprehensively test the conversion processing of the hole address carried in the test packet, which helps to discover potential problems that may exist in the NTB chip when processing non-standard addresses.

[0038] In a specific embodiment, the test packet is a REQ packet, and the PCIe system model 1 performs the step of randomly generating test packets, including: The PCIe system model 1 randomly selects an address under a virtual host module 11 as the source address; Randomly selects an address under another virtual host module 11 as the destination address; Generates a REQ packet according to the source address and the destination address.

[0039] In this embodiment, the REQ message is a message format used to initiate requests in the PCIe system, usually containing key information such as the source address, destination address, request type, data length, etc. When generating the REQ message, the randomly selected source address and destination address are filled into the corresponding fields in the message, and other necessary field information, such as the request type (which may be a read request, write request, etc.) and data length, can be further generated according to preset rules or randomly, finally forming a complete REQ message.

[0040] In a specific embodiment, the test message is a CPL message, and the PCIe system model 1 performs the step of randomly generating a test message, including: The PCIe system model 1 randomly selects an ID under a virtual host module 11 as the request ID; Randomly selects an ID under a virtual host module 11 as the completion ID, where the completion ID is different from the request ID; Generates the CPL message according to the request ID and the completion ID.

[0041] In this embodiment, the CPL message (Completion Message) is a standard message format used to respond to requests in the PCIe system, usually containing key information such as the request ID, completion ID, response status, data content, etc. During the generation process, the selected request ID and completion ID are filled into the corresponding fields in the message, and other necessary fields can be further generated according to preset rules or randomly, such as setting the response status (success, failure, etc.) according to the simulated response situation, generating or filling the data content according to requirements, etc., finally forming a complete CPL message.

[0042] In a specific embodiment, two virtual host modules 11 can send messages to each other for verification. For example, for virtual host module A and virtual host module B, set the id_base of virtual host module A to 10, id_limit to 30, and the address range to h100~h200; set the id_base of virtual host module B to 40, id_limit to 60, and the address range to h400~h600. Virtual host module A generates message TLP-A, the source address of the message is h102, the destination address is h403, and the ID is 12; virtual host module B generates message TLP-B, the source address of the message is h502, the destination address is h177, and the ID is 55. By sending TLP-A and TLP-B to the input scheduling module 2 respectively, and then performing conversion processing and comparison through the subsequent cross-domain routing module 3, chip implementation module 4, and comparison module 5, the verification of the NTB cross-domain access implementation is achieved.

[0043] In a specific embodiment, the steps of the input scheduling module 2 scheduling and receiving different test messages and sequentially synchronously sending each test message to the cross-domain routing module 3 and the chip implementation module 4 include The input scheduling module 2 schedules and receives different test messages and classifies them according to the virtual host module 11 that sends the test messages; For the test messages from the same virtual host module 11, different test messages are sorted according to the generation order of the test messages; For the test messages from different virtual host modules 11, a preset fair scheduling strategy is adopted for round-robin scheduling.

[0044] In this embodiment, by sorting the messages from the same virtual host module 11, it is ensured that the test messages can be processed in the order of generation. At the same time, a fair scheduling strategy is adopted for round-robin scheduling of the messages from different virtual host modules 11, realizing fair resource allocation among the virtual host modules 11. It avoids the situation that the messages of a certain virtual host module 11 cannot be processed for a long time due to a large number of messages from other modules, ensures that each virtual host module 11 can obtain a reasonable processing opportunity in the system, and improves the efficiency and fairness of the entire verification system.

[0045] In a specific embodiment, the chip implementation module 4 determines whether the PCIe system model 1 has not received an idle signal for a preset duration, where the idle signal is sent by the chip implementation module 4 to the PCIe system model 1 after completing the output of the second conversion message; If so, a stop packet sending instruction is sent to the PCIe system model 1 to cause the PCIe system model 1 to pause sending new test messages to the chip implementation module 4.

[0046] In this embodiment, after the chip implementation module 4 completes the output operation of the second conversion message, it will send an idle signal to the PCIe system model 1. The idle signal is used to inform the PCIe system model 1 that the chip implementation module 4 has completed a message processing task and is in a state where it can receive new test messages.

[0047] A timing mechanism is set inside the chip implementation module 4 to record the time interval from the last sending of the idle signal to the current moment. The chip implementation module 4 continuously compares this time interval with the preset duration. The preset duration is a time threshold preset according to the performance of the chip and the verification requirements.

[0048] If the chip implementation module 4 determines that the time interval from the last transmission of the idle signal to the current moment has exceeded the preset duration, it indicates that the chip implementation module 4 may have been in a busy state for a long time due to certain reasons (such as insufficient processing power, exceptions, etc.) and is unable to process new test packets in a timely manner. At this time, the chip implementation module 4 will send a stop packet transmission instruction to the PCIe system model 1, informing it to pause sending new test packets to the chip implementation module 4.

[0049] After receiving the stop packet transmission instruction, the PCIe system model 1 will pause sending new test packets to the chip implementation module 4 and wait until the chip implementation module 4 resumes normal processing capabilities before continuing to send. This can prevent the chip implementation module 4 from accumulating too many test packets.

[0050] Refer to Figure 2 , in one embodiment, a method for verifying NTB across host domains is provided. The method for verifying NTB across host domains is applied to the input scheduling module 2 in the foregoing embodiment and includes: S1: Schedule to receive different test packets. Among them, the test packets are randomly generated by the PCIe system model 1. A number of virtual host modules 11 are configured in the PCIe system model 1, and each virtual host module 11 is respectively connected to the input scheduling module 2, and the states of each virtual host module 11 are respectively initialized; S2: Sequentially synchronously send each test packet to the cross-domain routing module 3 and the chip implementation module 4, so that the cross-domain routing module 3 receives the test packet sent by the input scheduling module 2, performs address conversion on the test packet according to the preset simulation conversion method, outputs a first converted packet, and inputs it into the sub-comparison module 51 corresponding to the destination virtual host module 11 in the comparison module 5; and enables the chip implementation module 4 to receive the test packet sent by the input scheduling module 2, performs address conversion on the test packet according to the actual design code of the NTB chip, outputs a second converted packet, and inputs it into the sub-comparison module 51 corresponding to the destination virtual host module 11 in the comparison module 5; and a plurality of sub-comparison modules 51 configured based on different virtual host modules 11 are preset in the comparison module 5, and the first converted packet and the second converted packet are compared in the sub-comparison module 51 corresponding to the destination virtual host module 11. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module 4 fails the NTB cross-host domain verification.

[0051] In a specific embodiment, the step of the PCIe system model performing the initialization setting of the states of each virtual host module includes: The PCIe system model receives global configuration parameters through the UVM command-line parameter passing mechanism; According to the global configuration parameters, host numbers and corresponding address spaces are allocated to each virtual host module; An ID domain id_base~id_limit is allocated to each virtual host module, where id_base is the ID of the virtual host module, and id_limit is the upper limit value of the IDs of the devices attached to the virtual host module; An address domain addr_base ~ addr_limit is allocated to each virtual host module, where addr_base ~addr_limit are the addresses allocated to the virtual host module and the devices attached to the virtual host module; The ID domain and address domain of each virtual host module are saved into the global configuration parameters to obtain updated global configuration parameters; According to the updated global configuration parameters, ID and address mapping configurations are performed between different virtual host modules to obtain address mapping table information; The address mapping table information is synchronously updated to the cross-domain routing module and the chip implementation module. Among them, the cross-domain routing module obtains the updated address mapping table information through table entry instances, and the chip implementation module obtains the updated address mapping table information through csr chain write tables.

[0052] In a specific embodiment, when the PCIe system model executes the step of allocating host numbers and corresponding address spaces to each virtual host module according to the global configuration parameters, it further includes: Reserve a hole address space, which is used to test the conversion processing of the hole address carried in the test packet.

[0053] In a specific embodiment, the test packet is a REQ packet. When the PCIe system model executes the step of randomly generating test packets, it includes: The PCIe system model randomly selects an address under a virtual host module as the source address; Randomly select an address under another virtual host module as the destination address; Generate a REQ packet according to the source address and the destination address.

[0054] In a specific embodiment, the test packet is a CPL packet. When the PCIe system model executes the step of randomly generating test packets, it includes: The PCIe system model randomly selects an ID under a virtual host module as the request ID; Randomly select an ID under a virtual host module as the completion ID, where the completion ID is different from the request ID; Generate the CPL message according to the request ID and the completion ID.

[0055] In a specific embodiment, the steps of the input scheduling module scheduling to receive different test messages and sequentially synchronously sending each test message to the cross-domain routing module and the chip implementation module include: The input scheduling module schedules to receive different test messages and classifies them according to the virtual host module that sends the test messages; For test messages from the same virtual host module, sort different test messages according to the generation order of the test messages; For test messages from different virtual host modules, use a preset fair scheduling strategy for round-robin scheduling.

[0056] In a specific embodiment, the chip implementation module determines whether an idle signal has not been sent to the PCIe system model for a preset duration, where the idle signal is sent by the chip implementation module to the PCIe system model after completing the output of the second conversion message; If so, send a stop packet sending instruction to the PCIe system model to cause the PCIe system model to pause sending new test messages to the chip implementation module.

[0057] Through the NTB cross-host domain verification method of this embodiment, the cross-host domain function of the NTB chip can be verified quickly and comprehensively. The PCIe system model 1 can generate diverse test messages, covering various possible cross-domain access scenarios. Combining with the efficient scheduling mechanism of the input scheduling module 2, a large number of tests can be performed on the chip in a short time, greatly improving the verification efficiency of the NTB cross-host domain. The design of the comparison module 5 enables accurate positioning of the specific link where there is a problem in the chip implementation module 4 when the verification fails. Through the detailed message comparison difference information, technicians can intuitively understand the deviation between the chip and the ideal simulated conversion method during the address conversion process, which helps to quickly find errors or defects in the chip design code, provides strong support for the optimization and improvement of the chip, and shortens the chip R & D cycle.

[0058] Figure 3 Shows the internal structure diagram of a computer device in an embodiment. The computer device can specifically be a terminal or a server. As Figure 3As shown in the figure, the computer device includes a processor, a memory, and a network interface connected via a system bus. Among them, the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement the NTB cross-host domain verification method. The internal memory may also store a computer program. When the computer program is executed by the processor, the processor can execute the NTB cross-host domain verification method. Those skilled in the art can understand that Figure 3 The structure shown in the figure is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0059] In one embodiment, a computer device is proposed, including a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor performs the following steps: Schedule to receive different test messages. Among them, the test messages are randomly generated by the PCIe system model. A number of virtual host modules are configured in the PCIe system model, and each virtual host module is respectively connected to the input scheduling module. The states of each virtual host module are respectively initialized. Sequentially synchronously send each test message to the cross-domain routing module and the chip implementation module, so that the cross-domain routing module receives the test message sent by the input scheduling module, performs address conversion on the test message according to a preset simulation conversion method, outputs a first converted message, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; and enables the chip implementation module to receive the test message sent by the input scheduling module, performs address conversion on the test message according to the actual design code of the NTB chip, outputs a second converted message, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; and there are multiple sub-comparison modules configured based on different virtual host modules in the comparison module. Compare the first converted message and the second converted message in the sub-comparison module corresponding to the destination virtual host module. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module fails the NTB cross-host domain verification.

[0060] This embodiment can quickly and comprehensively verify the cross-host domain function of the NTB chip. The PCIe system model 1 can generate a variety of test messages, covering various possible cross-domain access scenarios. Combined with the efficient scheduling mechanism of the input scheduling module 2, it can perform a large number of tests on the chip in a short period of time, greatly improving the verification efficiency of the NTB cross-host domain. The design of the comparison module 5 enables the precise location of the specific link where the chip implementation module 4 has problems when the verification fails. Through detailed message comparison difference information, technicians can intuitively understand the deviation of the chip from the ideal analog conversion method during the address conversion process, which helps to quickly find errors or defects in the chip design code, provide strong support for chip optimization and improvement, and shorten the chip research and development cycle.

[0061] In one embodiment, a computer-readable storage medium is provided, storing a computer program, wherein when the computer program is executed by a processor, the processor performs the following steps: Scheduling to receive different test messages, wherein the test messages are randomly generated by the PCIe system model, the PCIe system model is configured with a number of virtual host modules, each virtual host module is respectively connected to the input scheduling module, and the state of each virtual host module is respectively initialized and set; Each test message is synchronously sent to the cross-domain routing module and the chip implementation module in sequence, so that the cross-domain routing module receives the test message sent by the input scheduling module, and performs address conversion on the test message according to a preset simulation conversion method, outputs a first conversion message, and inputs it into a sub-comparison module in the comparison module corresponding to the destination virtual host module of the first conversion message; and the chip implementation module receives the test message sent by the input scheduling module, and performs address conversion on the test message according to the actual design code of the NTB chip, outputs a second conversion message, and inputs it into a sub-comparison module in the comparison module corresponding to the destination virtual host module of the second conversion message; and a plurality of sub-comparison modules based on different virtual host module configurations are preset in the comparison module, and the first conversion message and the second conversion message are compared in the sub-comparison module corresponding to the destination virtual host module. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module has not passed the NTB cross-host domain verification.

[0062] This embodiment can quickly and comprehensively verify the cross-host domain function of the NTB chip. The PCIe system model 1 can generate a variety of test messages, covering various possible cross-domain access scenarios. Combined with the efficient scheduling mechanism of the input scheduling module 2, it can perform a large number of tests on the chip in a short period of time, greatly improving the verification efficiency of the NTB cross-host domain. The design of the comparison module 5 enables the precise location of the specific link where the chip implementation module 4 has problems when the verification fails. Through detailed message comparison difference information, technicians can intuitively understand the deviation of the chip from the ideal analog conversion method during the address conversion process, which helps to quickly find errors or defects in the chip design code, provide support for chip optimization and improvement, and shorten the chip research and development cycle.

[0063] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0064] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. An NTB cross-host domain authentication system, characterized in that It includes a PCIe system model, an input scheduling module, a cross-domain routing module, a chip implementation module, and a comparison module. Among them, the PCIe system model is connected to the input scheduling module, the input scheduling module is connected to the cross-domain routing module and the chip implementation module, and the cross-domain routing module and the chip implementation module are connected to the comparison module; A number of virtual host modules are configured in the PCIe system model. Each virtual host module is respectively connected to the input scheduling module, the status of each virtual host module is initialized respectively, test packets are randomly generated or generated according to preset test rules, and are input into the input scheduling module; The input scheduling module schedules and receives different test packets, and sequentially synchronously sends each test packet to the cross-domain routing module and the chip implementation module; The cross-domain routing module receives the test packets sent by the input scheduling module, performs address conversion on the test packets according to a preset simulation conversion method, outputs a first converted packet, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; The chip implementation module receives the test packets sent by the input scheduling module, performs address conversion on the test packets according to the actual design code of the NTB chip, outputs a second converted packet, and inputs it into the sub-comparison module corresponding to the destination virtual host module in the comparison module; A number of sub-comparison modules configured based on different virtual host modules are preset in the comparison module. The first converted packet and the second converted packet are compared in the sub-comparison module corresponding to the destination virtual host module. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module fails the NTB cross-host domain verification.

2. The NTB cross-host domain authentication system according to claim 1, wherein, The step of the PCIe system model performing initialization settings on the status of each virtual host module respectively includes: The PCIe system model receives global configuration parameters through the UVM command-line parameter passing mechanism; According to the global configuration parameters, host numbers and corresponding address spaces are allocated to each virtual host module; An ID domain id_base~id_limit is allocated to each virtual host module, where id_base is the ID of the virtual host module and id_limit is the upper limit value of the ID of the devices attached to the virtual host module; An address domain addr_base ~ addr_limit is allocated to each virtual host module, where addr_base ~ addr_limit is the address allocated to the virtual host module and the devices attached to the virtual host module; The ID domain and address domain of each virtual host module are saved into the global configuration parameters to obtain updated global configuration parameters; According to the updated global configuration parameters, the ID and address mapping configurations are performed between different virtual host modules to obtain address mapping table information; Synchronously update the address mapping table information to the cross-domain routing module and the chip implementation module, where the cross-domain routing module obtains the updated address mapping table information through table entry instances, and the chip implementation module obtains the updated address mapping table information through CSR chain writing tables.

3. The NTB cross-host domain verification system according to claim 2, characterized in that, The PCIe system model performs the step of allocating host numbers and corresponding address spaces to each virtual host module according to the global configuration parameters, and further includes: Reserve a hole address space, which is used to test the conversion process of the hole address carried in the test packet.

4. The NTB cross-host domain authentication system according to claim 2, wherein The test packet is a REQ packet, and the PCIe system model performs the step of randomly generating test packets, including: The PCIe system model randomly selects an address under a virtual host module as the source address; Randomly select an address under another virtual host module as the destination address; Generate a REQ packet according to the source address and the destination address.

5. The NTB cross-host domain verification system according to claim 2, wherein The test packet is a CPL packet, and the PCIe system model performs the step of randomly generating test packets, including: The PCIe system model randomly selects an ID under a virtual host module as the request ID; Randomly select an ID under a virtual host module as the completion ID, where the completion ID is different from the request ID; Generate the CPL packet according to the request ID and the completion ID.

6. The NTB cross-host domain authentication system according to claim 1, wherein The step of the input scheduling module scheduling to receive different test packets and sequentially synchronously sending each test packet to the cross-domain routing module and the chip implementation module includes: The input scheduling module schedules to receive different test packets and classifies them according to the virtual host module that sends the test packets; For test packets from the same virtual host module, sort different test packets according to the generation order of the test packets; For test packets from different virtual host modules, use a preset fair scheduling strategy for round-robin scheduling.

7. The NTB cross-host domain verification system according to claim 1, wherein The chip implementation module determines whether an idle signal has not been sent to the PCIe system model for a preset duration, where the idle signal is sent by the chip implementation module to the PCIe system model after the output of the second conversion packet is completed; If so, send a stop packet sending instruction to the PCIe system model to cause the PCIe system model to pause sending new test packets to the chip implementation module.

8. A verification method for NTB across host domains, characterized in that, The NTB cross-host domain verification method is applied to the input scheduling module according to any one of claims 1-7, including: Schedule to receive different test packets, where the test packets are randomly generated by the PCIe system model, several virtual host modules are configured in the PCIe system model, each virtual host module is respectively connected to the input scheduling module, and the states of each virtual host module are respectively initialized. Sequentially synchronously send each test message to the cross-domain routing module and the chip implementation module, so that the cross-domain routing module receives the test message sent by the input scheduling module, performs address conversion on the test message according to a preset analog conversion method, outputs a first converted message, and inputs it into the sub-comparison module corresponding to the destination virtual host module of the first converted message in the comparison module; and enables the chip implementation module to receive the test message sent by the input scheduling module, performs address conversion on the test message according to the actual design code of the NTB chip, outputs a second converted message, and inputs it into the sub-comparison module corresponding to the destination virtual host module of the second converted message in the comparison module; and a plurality of sub-comparison modules configured based on different virtual host modules are preset in the comparison module, and the first converted message and the second converted message are compared in the sub-comparison module corresponding to the destination virtual host module. If the comparison result does not meet the preset consistency setting, it is determined that the chip implementation module fails the NTB cross-host domain verification.

9. A computer device, characterized in that, The device includes a memory and a processor. When the computer program stored in the memory is executed by the processor, the processor executes the steps of the NTB cross-host domain verification method as claimed in claim 8.

10. A computer-readable storage medium, characterized in that, Stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the NTB cross-host domain verification method as claimed in claim 8.

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