Grid annealing method of ferroelectric transistor, grid structure and ferroelectric transistor

Abstract

The invention provides a gate annealing method for a ferroelectric transistor, and the method comprises the steps: forming an N / P well layer, a source electrode and a drain electrode on a substrate, and enabling the source electrode and the drain electrode to be formed at the two sides of the N / P well layer; through an atomic layer deposition process, ferroelectric materials are deposited in a grid region where a grid is to be formed, a ferroelectric layer is formed, titanium oxide is deposited on the surface of the ferroelectric layer to serve as a stress layer, amorphous silicon is deposited on the surface of the stress layer to serve as a sacrificial layer, and laser annealing treatment is carried out on the surface of the sacrificial layer to induce the ferroelectric layer to generate a ferroelectric phase. The stress layer provides stress for the ferroelectric layer to stabilize the ferroelectric phase; the sacrificial layer is removed, titanium nitride is deposited on the surface of the stress layer after laser annealing to serve as a work function layer, conductive metal is deposited on the work function layer to form a conductive layer, and the gate metal lamination layer is obtained. The invention further provides a gate structure obtained based on the gate annealing method and a ferroelectric transistor.

Description

Technical Field

[0001] The present disclosure belongs to the field of microelectronics, and in particular, relates to a gate annealing method of a ferroelectric transistor, a gate structure, and a ferroelectric transistor. Background Art

[0002] With the rapid development of modern information technology, big data, network intelligence, and cloud computing have fully entered people's daily lives. The amount of data information to be stored is continuously increasing, which poses a severe challenge to storage technology and prompts the industrial and academic communities to continuously develop new memory technologies to meet the ever-expanding market demand. The importance of ferroelectric transistors lies in their unique ferroelectric properties, which endow them with great potential in the fields of non-volatile storage and low-power electronics. They can achieve fast data writing and reading while maintaining low power consumption, which is crucial for improving the performance of electronic devices and extending battery life.

[0003] Ferroelectric properties have been discovered in doped hafnium oxide materials (HfO2), which are expected to solve the challenges of traditional ferroelectric materials in terms of size scaling and manufacturability, and have rekindled the high attention and research interest of the academic and industrial communities. They are considered strong contenders for next-generation non-volatile memories. However, there are still many problems in the current research on FeFETs: First is the fatigue problem. To make the doped hafnium-based oxide exhibit ferroelectricity, a metal capping layer is required to provide tensile stress to stabilize the ferroelectric orthorhombic phase. Considering compatibility with CMOS processes, TiN is usually selected as the top electrode, but Ti elements will absorb O elements in the hafnium-based oxide, resulting in a large number of oxygen vacancies near the top electrode / ferroelectric layer interface. These oxygen vacancies will trap charges and pin the effective ferroelectric switching domains, causing ferroelectric fatigue. Second is the thermal crosstalk problem. Among many doping elements, Hf 0.5 Zr 0.5 O2 has the lowest requirement for the thermal budget, but a rapid thermal processing (RTP) process at about 450 - 650 °C for about 1 minute is still required to activate the ferroelectric phase, which is a relatively high thermal budget requirement for small-sized devices. At the same time, long-time RTP annealing will cause non-uniform distribution of oxygen vacancies in the ferroelectric layer body, pinning ferroelectric domain switching and also causing fatigue phenomena. When using a laser annealing process, the high-intensity laser has a non-uniform light spot, which will cause ferroelectric differences and reduce the performance of the transistor.

[0004] Therefore, developing a method for uniformly annealing to induce the activation of the ferroelectric phase in hafnium-based ferroelectric materials and simultaneously improving the fatigue phenomenon of ferroelectric transistors has profound practical significance. Summary of the Invention

[0005] In view of this, to solve at least one technical problem in the related art and other aspects, the present disclosure proposes a gate annealing method for a ferroelectric transistor, including:

[0006] Form an N / P well layer, a source electrode, and a drain electrode on a substrate, wherein the source electrode and the drain electrode are formed on both sides of the N / P well layer;

[0007] Through an atomic layer deposition process, deposit a ferroelectric material in the gate region where the gate is to be formed to form a ferroelectric layer, deposit titanium oxide as a stress layer on the surface of the ferroelectric layer, deposit amorphous silicon as a sacrificial layer on the surface of the stress layer, and perform laser annealing treatment on the surface of the sacrificial layer to induce a ferroelectric phase in the ferroelectric layer, and the stress layer provides stress for the ferroelectric layer to stabilize the ferroelectric phase;

[0008] Remove the sacrificial layer, deposit titanium nitride as a work function layer on the surface of the stress layer after laser annealing, and deposit a conductive metal on the work function layer to form a conductive layer, obtaining a gate metal stack.

[0009] According to an embodiment of the present disclosure, the thermal expansion coefficient of the stress layer is 7.1×10 -6 K -1 ~9.2×10 -6 K -1 .

[0010] According to an embodiment of the present disclosure, the thickness of the stress layer is 2 - 5 nm.

[0011] According to an embodiment of the present disclosure, in the laser annealing treatment, the laser wavelength is 200 - 527 nm, the laser power is 3 - 5 W, and the laser current is 9.8 - 10.2 A.

[0012] According to an embodiment of the present disclosure, the thickness of the sacrificial layer is 5 - 10 nm.

[0013] According to an embodiment of the present disclosure, the method for removing the sacrificial layer includes: etching and rinsing the sacrificial layer with a tetramethylammonium hydroxide solution.

[0014] According to an embodiment of the present disclosure, the foregoing gate annealing method further includes performing photolithography and etching on the gate metal stack in sequence to obtain a gate with a target pattern.

[0015] According to an embodiment of the present disclosure, the ferroelectric material is hafnium oxide with a doping element, and the doping element includes any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.

[0016] In another aspect of the present disclosure, a gate structure of a ferroelectric transistor prepared according to the foregoing gate annealing method is provided, including a gate oxide layer, a ferroelectric layer, a stress layer, a work function layer, and a conductive layer. The gate oxide layer is adapted to form an insulating structure to reduce gate leakage, enhance the control of the gate voltage over channel carriers, and control the switching and operating current of the ferroelectric transistor; the ferroelectric layer is formed on the gate oxide layer, and the ferroelectric layer has a ferroelectric phase. Through the spontaneous polarization state, according to the change of the polarization state by the gate voltage signal, the threshold voltage drift of the channel current is regulated; the stress layer is formed on the ferroelectric layer, and the stress layer is adapted to stabilize the orthorhombic phase of the ferroelectric phase crystallization in the ferroelectric layer to enhance the ferroelectric characteristics of the ferroelectric layer. The work function layer is formed on the stress layer, and the work function layer is adapted to adjust the work function of the ferroelectric transistor; the conductive layer is formed on the work function layer, and the conductive layer is adapted to achieve gate electrode interconnection.

[0017] In another aspect of the present disclosure, a ferroelectric transistor is provided, including a substrate, an N / P well layer, a source electrode, a gate electrode, and a drain electrode. Among them, the N / P well layer is formed on the substrate and is adapted to isolate channel carriers from the substrate to avoid the latch-up effect; the source electrode and the drain electrode are respectively formed on both sides of the N / P well layer; the structure of the gate electrode is as described in the foregoing gate structure, formed in the middle of the N / P well layer and used as the gate electrode. When an external voltage is applied to the conductive layer of the gate metal stack, the ferroelectric layer is polarized, so that the gate structure outputs a gate voltage to control the state of channel carriers and realize the opening and closing of the ferroelectric transistor.

[0018] According to an embodiment of the present disclosure, titanium oxide as the stress layer has a large residual tensile stress, which can provide tensile stress to stabilize the ferroelectric orthorhombic phase; at the same time, since titanium oxide is an oxygen-rich interface layer, it can inhibit the diffusion of oxygen in the ferroelectric layer to the metal layer and reduce the generation of interface oxygen vacancies. The laser annealing scheme can relieve the aggregation of oxygen vacancies and reduce the activation time of the ferroelectric phase. The sacrificial layer, as the transfer and buffer region of laser heat, not only increases the laser power window and relieves the non-uniform heating of the laser spot; it also does not affect the interfaces of other structures during the removal process, avoiding the generation of low-quality interfaces in the ferroelectric crystallization thermal budget. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional schematic diagram after substrate pretreatment in Embodiment 1 of the present disclosure;

[0020] Figure 2 is in Embodiment 1 of the present disclosure Figure 1 on the basis of forming device isolation; a cross-sectional schematic diagram

[0021] Figure 3 is in Embodiment 1 of the present disclosure Figure 2 on the basis of forming a dummy gate and a hard mask stack; a cross-sectional schematic diagram

[0022] Figure 4 is a cross-sectional schematic diagram after etching the dummy gate and hard mask stack based on that in Figure 3 in Embodiment 1 of the present disclosure;

[0023] Figure 5 is a cross-sectional schematic diagram after forming sidewalls and performing source / drain implantation based on that in Figure 4 in Embodiment 1 of the present disclosure;

[0024] Figure 6 is an interface schematic diagram of exposing the dummy gate based on that in Figure 5 in Embodiment 1 of the present disclosure;

[0025] Figure 7 is a cross-sectional schematic diagram of forming a gate region based on that in Figure 6 in Embodiment 1 of the present disclosure;

[0026] Figure 8 is a cross-sectional schematic diagram of forming a ferroelectric layer, a stress layer, and a sacrificial layer based on that in Figure 7 in Embodiment 1 of the present disclosure;

[0027] Figure 9 is a cross-sectional schematic diagram of performing laser annealing based on that in Figure 8 in Embodiment 1 of the present disclosure;

[0028] Figure 10 is a cross-sectional schematic diagram of forming a conductive layer based on that in Figure 9 in Embodiment 1 of the present disclosure;

[0029] Figure 11 is a cross-sectional schematic diagram of forming gate lithography based on that in Figure 10 in Embodiment 1 of the present disclosure;

[0030] Figure 12 is a cross-sectional schematic diagram of forming a ferroelectric transistor based on that in Figure 11 in Embodiment 1 of the present disclosure

[0031] In the attached drawings of the present disclosure specification, the meanings of the reference numerals are as follows:

[0032] 1 - Substrate; 2 - Well oxide layer; 3 - Gate oxide layer; 4 - Dummy gate; 5 - ONO hard mask stack; 501 - Silicon dioxide layer; 502 - Silicon nitride layer; 6 - Sidewall; 71 - Source impurity region; 72 - Drain impurity region; 81 - Source silicide layer; 82 - Drain silicide; 9 - Isolation protection layer; 10 - Gate region; 11 - Ferroelectric layer; 12 - Stress layer; 13 - Sacrificial layer; 14 - Work function layer; 15 - Conductive layer; 16 - Gate; 17 - Spacer layer; 18 - Via interconnect metal; 19 - Electrode; 20 - Source; 21 - Drain. Detailed implementation manners

[0033] To make the objectives, technical solutions, and advantages of the present disclosure more apparent, the following provides a more detailed description of the present disclosure in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] In the ranges disclosed in the present disclosure, the endpoints and any values are not limited to the exact ranges or values. These ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in the present disclosure.

[0035] The terms used herein are merely for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0036] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0037] Throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. Also, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships. Additionally, in the present disclosure, any reference signs located between parentheses should not be construed as a limitation to the present disclosure.

[0038] Similarly, in order to streamline the present disclosure and assist in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0039] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0040] In the process of implementing this disclosure, it is found that for the fatigue problem and thermal crosstalk problem of the ferroelectric transistor gate, it is necessary to balance the heat treatment-induced ferroelectric phase transition and the oxygen vacancy problem caused by high temperature.

[0041] In the technical solution of this disclosure, a non-metallic stress layer is introduced to induce ferroelectric phase transition and prevent oxygen vacancy diffusion. At the same time, a sacrificial layer is also introduced to overcome the non-uniformity problem of laser annealing.

[0042] This disclosure proposes a gate annealing method for a ferroelectric transistor, including the following steps S101 - step S103:

[0043] Step S101: Form an N / P well layer, a source electrode 20, and a drain electrode 21 on a substrate 1, where the source electrode 20 and the drain electrode 21 are formed on both sides of the N / P well layer.

[0044] Step S102: Through atomic layer deposition technology, deposit a ferroelectric material in the gate region 10 where the gate is to be formed to form a ferroelectric layer 11. Deposit titanium oxide as a stress layer 12 on the surface of the ferroelectric layer 11, deposit amorphous silicon as a sacrificial layer 13 on the surface of the stress layer 12, and perform laser annealing treatment on the surface of the sacrificial layer 13 to induce a ferroelectric phase in the ferroelectric layer 11. The stress layer 12 provides stress for the ferroelectric layer 11 to stabilize the ferroelectric phase.

[0045] Step S103: Remove the sacrificial layer 13, deposit titanium nitride as a work function layer 14 on the surface of the stress layer 12 after laser annealing, and deposit a conductive metal on the work function layer 14 to form a conductive layer, obtaining a gate metal stack.

[0046] According to the embodiments of this disclosure, titanium oxide as a stress layer has a large residual tensile stress, which can provide tensile stress to stabilize the ferroelectric orthorhombic phase; at the same time, since titanium oxide is an oxygen-rich interface layer, it can inhibit the diffusion of oxygen in the ferroelectric layer 11 to the metal layer and reduce the generation of interface oxygen vacancies. The laser annealing scheme can relieve the aggregation of oxygen vacancies and reduce the time for ferroelectric phase activation. The sacrificial layer 13, as a transfer and buffer region for laser heat, not only increases the laser power window and relieves the non-uniform heating of the laser spot; it also does not affect the interfaces of other structures during the removal process, avoiding the generation of low-quality interfaces in the ferroelectric crystallization heat budget. According to the embodiments of this disclosure, in step S102, the thermal expansion coefficient of the deposited stress layer 12 is 7.1×10 -6 K -1 ~9.2×10-6 K -1 。

[0047] According to an embodiment of the present disclosure, compared with traditional titanium nitride as a capping layer, titanium oxide has a lower coefficient of thermal expansion (the coefficient of thermal expansion of titanium nitride is 9.4×10 -6 K -1 or so), that is, titanium oxide can provide greater residual tensile stress. TiO2 provides a clamping force to the ferroelectric layer 11 and inhibits the diffusion of oxygen in the ferroelectric layer 11 into TiN.

[0048] According to an embodiment of the present disclosure, the thickness of the stress layer 12 deposited in step S102 is 2-5 nm, for example, it can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc.

[0049] In some specific embodiments, the thickness of the ferroelectric layer 11 can be 5-15 nm.

[0050] According to an embodiment of the present disclosure, in the laser annealing treatment in step S102, the laser wavelength is 200-527 nm, for example, it can be 200 nm, 300 nm, 400 nm, 500 nm, 527 nm, etc., the laser power is 3-5 W, for example, it can be 3 W, 4 W, 5 W, etc., the corresponding current range is 9.8-10.2 A, preferably 10 A, and the corresponding laser power is 3.8 W.

[0051] According to an embodiment of the present disclosure, an annealing scheme of nanosecond short-wave laser annealing is designed in the present disclosure to activate the ferroelectric phase. Its extremely fast heating and cooling rate makes the oxygen vacancies not have enough time to aggregate in the ferroelectric layer 11, so as to achieve the purpose of regulating the oxygen vacancies in the body.

[0052] In some specific embodiments, the laser power density of annealing is related to the laser emitter and the ferroelectric crystallization temperature, and a suitable laser power density can be selected according to different laser emitters and ferroelectric materials.

[0053] According to an embodiment of the present disclosure, the thickness of the sacrificial layer 13 deposited in step S102 is 5-10 nm, for example, it can be 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, etc.

[0054] According to an embodiment of the present disclosure, amorphous silicon (α-Si) is used as the sacrificial layer 13 for heat transfer and laser damage, alleviating the ferroelectric difference caused by non-uniform light spots and protecting the surface from being burned by high-power lasers. Meanwhile, within the thickness range of 5 - 10 nm, it can not only ensure that the heat energy transferred by the sacrificial layer 13 is sufficient to induce ferroelectric phase transformation, but also reduce the thermal damage at the interface of the ferroelectric layer 11.

[0055] According to an embodiment of the present disclosure, in step S103, the method for removing the sacrificial layer 13 includes: etching the sacrificial layer with a tetramethylammonium hydroxide solution and rinsing.

[0056] According to an embodiment of the present disclosure, a tetramethylammonium hydroxide (TMAH) solution with a high selectivity ratio (only etching amorphous silicon) is used to remove α-Si, which is also one of the reasons for choosing amorphous silicon as the material of the sacrificial layer 13. After the damaged α-Si by the laser is removed, the subsequent structure is redeposited, avoiding the generation of a low-quality interface in the ferroelectric crystallization heat budget.

[0057] According to an embodiment of the present disclosure, the aforementioned gate annealing method further includes:

[0058] Step S104: Performing photolithography and etching on the gate metal stack in sequence to obtain a gate with a target pattern.

[0059] According to an embodiment of the present disclosure, in step S102, the ferroelectric material of the ferroelectric layer 11 is hafnium oxide with a doping element, and the doping element includes any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.

[0060] In some specific embodiments, the conductive metal is tungsten.

[0061] On the other hand, the present disclosure proposes a gate structure of a ferroelectric transistor prepared according to the aforementioned gate annealing method, including a gate oxide layer 3, a ferroelectric layer 11, a stress layer 12, a work function layer 14, and a conductive layer. Among them, the gate oxide layer 3 is suitable for forming an insulating structure to reduce gate leakage, enhance the control of the gate voltage over channel carriers, and control the switching and working current of the ferroelectric transistor; the ferroelectric layer 11 is formed on the gate oxide layer 3, and the ferroelectric layer 11 has a ferroelectric phase. Through the spontaneous polarization state, according to the change of the polarization state by the gate voltage signal, the threshold voltage drift of the channel current is regulated; the stress layer 12 is formed on the ferroelectric layer 11, and the stress layer 12 is suitable for stabilizing the orthorhombic phase of the ferroelectric phase crystallization in the ferroelectric layer 11 to enhance the ferroelectric characteristics of the ferroelectric layer 11. The work function layer 14 is formed on the stress layer 12, and the work function layer 14 is suitable for adjusting the work function of the ferroelectric transistor; the conductive layer 15 is formed on the work function layer 14, and the conductive layer 15 is suitable for realizing gate electrode interconnection.

[0062] In another aspect of the present disclosure, a ferroelectric transistor is proposed, which includes a substrate 1, an N / P well layer, a source electrode 20, a gate electrode 16, and a drain electrode 21. Among them, the N / P well layer is formed on the substrate 1 and is suitable for realizing the isolation of channel carriers from the substrate to avoid the latch-up effect; the source electrode 20 and the drain electrode 21 are respectively formed on both sides of the N / P well layer; the structure of the gate electrode 16 is as described in the foregoing gate structure, and is formed in the middle of the N / P well layer and serves as the gate electrode 16. When an external voltage is applied to the conductive layer 15 of the gate stack structure, the ferroelectric layer 11 is polarized, so that the gate structure outputs a gate voltage to control the state of channel carriers and realize the opening and closing of the ferroelectric transistor.

[0063] According to an embodiment of the present disclosure, when the gate structure obtained by applying the gate laser annealing method proposed in the present disclosure is used, the oxygen element in the ferroelectric layer 11 is stable during the operation of the ferroelectric transistor, the generation of oxygen vacancies is reduced, and the operation stability of the ferroelectric transistor is ensured.

[0064] In some specific embodiments, device isolation includes but is not limited to shallow trench isolation (STI) and local oxidation of silicon (LOCOS) technology.

[0065] In some specific embodiments, the manufacturing process of the ferroelectric transistor includes gate first and gate last technologies. Only the latter is shown in the embodiments of the present disclosure, and classical parameters and materials are selected in the device manufacturing process.

[0066] It should be noted that the described embodiments are only a part of the embodiments of the present disclosure, rather than all embodiments. Based on the embodiments in the present disclosure, other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0067] Embodiment

[0068] In this embodiment, a ferroelectric transistor is completely manufactured. Among them, the gate electrode is manufactured according to the foregoing gate annealing method. Figures 1 to 12 They are respectively schematic diagrams of the manufacturing process in this embodiment.

[0069] Specifically:

[0070] As Figure 1 shown, a single crystal silicon is used as the substrate 1, and the substrate 1 is pretreated to remove impurities and natural contaminants.

[0071] As Figure 2 shown, thermal oxidation is used to grow silicon dioxide on the surface of the substrate 1 as the well oxide layer 2 and then etched, and device isolation is realized through LOCOS isolation technology.

[0072] As shown Figure 3 in the figure, silicon dioxide is grown on the surfaces of the well oxide layer 2 and the substrate 1 as the gate oxide layer 3. Amorphous silicon, silicon dioxide, silicon nitride, and silicon dioxide are sequentially deposited on the gate oxide layer 3 to form a dummy gate 4, a silicon dioxide layer 501, a silicon nitride layer 502, and a silicon dioxide layer 501, respectively. Among them, the silicon dioxide layer 501, the silicon nitride layer 502, and the silicon dioxide layer 501 serve as the ONO hard mask stack 5.

[0073] As shown Figure 4 in the figure, the ONO hard mask stack 5 on both sides is etched.

[0074] As shown Figure 5 in the figure, silicon nitride is deposited and etched on both sides of the etched ONO hard mask stack 5 to obtain sidewalls 6 as isolation structures. The silicon dioxide in the source / drain regions is wet-etched, and source / drain ion implantation is performed on the surface of the substrate 1, and annealing is carried out to activate the impurity distributions in the source impurity region 71 and the drain impurity region 72. A metal silicide (Silicide) process technology is performed in the source impurity region 71 and the drain impurity region 72 to form a source silicide layer 81 and a drain silicide 82 to reduce the source / drain contact resistance.

[0075] As shown Figure 6 in the figure, silicon nitride is respectively deposited at the source / drain positions as an isolation protection layer 9, and part of the isolation protection layer 9 is removed by a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP) to expose the dummy gate 4.

[0076] As shown Figure 7 in the figure, the dummy gate 4 is removed to expose the gate region 10.

[0077] As shown Figure 8 in the figure, a ferroelectric material is deposited by ALD as the ferroelectric layer 11, and the thickness of the ferroelectric layer 11 is 7 nm. Titanium oxide and amorphous silicon are sequentially deposited to form a stress layer 12 and a sacrificial layer 13, respectively.

[0078] As shown Figure 9 in the figure, by nanosecond laser annealing, extremely fast heating and cooling induce the ferroelectric phase, relieve the aggregation of oxygen vacancies in the body, avoid pinning the ferroelectric switching domains, and improve the durability of the ferroelectric transistor. Among them, the parameters of the laser annealing are a Nd:YLF laser (Tolar527, 35K) with a laser wavelength of 527 nm, a laser pulse duration of 200 ns, a repetition rate of 500 Hz, and a laser power range of 3.1 - 4.9 W.

[0079] As shown Figure 10As shown, the sacrificial layer 13 is etched and rinsed with a tetramethylammonium hydroxide solution, and then titanium nitride and tungsten are sequentially deposited on the surface of the stress layer 12 as the work function layer 14 and the conductive layer 15.

[0080] As Figure 11 shown, photolithography is performed on the gate region 10, and finally the gate 16 is formed.

[0081] As Figure 12 shown, SiO2 is deposited as the spacer layer 17 and via etching is performed. Ti, TiN, and W are sequentially deposited in the via region. After polishing by the CMP process and depositing TiN for electrode etching, the via interconnect metal 18, the electrode 19 are obtained, and the source 20 and the drain 21 are formed. Among them, the structure of the ferroelectric transistor is as Figure 12 shown.

[0082] In the specific embodiments described above, the purpose, technical solutions, and beneficial effects of the present disclosure are further described in detail. It should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A gate annealing method for a ferroelectric transistor, comprising: Forming an N / P well layer, a source electrode, and a drain electrode on a substrate, wherein the source electrode and the drain electrode are formed on both sides of the N / P well layer; By atomic layer deposition process, depositing a ferroelectric material in a gate region where a gate is to be formed to form a ferroelectric layer, depositing titanium oxide as a stress layer on the surface of the ferroelectric layer, depositing amorphous silicon as a sacrificial layer on the surface of the stress layer, and performing laser annealing treatment on the surface of the sacrificial layer to induce a ferroelectric phase in the ferroelectric layer, and the stress layer provides stress for the ferroelectric layer to stabilize the ferroelectric phase; Removing the sacrificial layer, depositing titanium nitride as a work function layer on the surface of the stress layer after laser annealing, and depositing a conductive metal on the work function layer to form a conductive layer, thereby obtaining a gate metal stack.

2. The gate annealing method according to claim 1, wherein, The thermal expansion coefficient of the stress layer is 7.1×10 -6 K -1 ~9.2×10 -6 K -1 .

3. The gate annealing method according to claim 1, wherein, The thickness of the stress layer is 2 - 5 nm.

4. The gate annealing method according to claim 1, wherein In the laser annealing treatment, the laser wavelength is 200 - 527 nm, the laser power is 3 - 5 W, and the laser current is 9.8 - 10.2 A.

5. The gate annealing method according to claim 1, wherein, The thickness of the sacrificial layer is 5 - 10 nm.

6. The gate annealing method according to claim 1, wherein, The method for removing the sacrificial layer includes: etching and rinsing the sacrificial layer with a tetramethylammonium hydroxide solution.

7. The gate annealing method according to claim 1, further comprising performing photolithography and etching on the gate metal stack in sequence to obtain a gate with a target pattern.

8. The gate annealing method according to claim 1, wherein, The ferroelectric material is hafnium oxide with a doping element, and the doping element includes any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.

9. A gate structure of a ferroelectric transistor prepared by the gate annealing method according to any one of claims 1 - 8, comprising: A gate oxide layer, suitable for forming an insulating structure to reduce gate leakage, enhance the control of the gate voltage over channel carriers, and control the switching and operating current of the ferroelectric transistor; A ferroelectric layer, formed on the gate oxide layer, the ferroelectric layer having a ferroelectric phase, and regulating the threshold voltage drift of the channel current according to the change of the polarization state by the spontaneous polarization state in response to a gate voltage signal; A stress layer, formed on the ferroelectric layer, the stress layer being suitable for stabilizing the orthorhombic phase of the ferroelectric phase crystallization in the ferroelectric layer to enhance the ferroelectric characteristics of the ferroelectric layer; A work function layer, formed on the stress layer, the work function layer being suitable for adjusting the work function of the ferroelectric transistor; A gate metal stack, formed on the work function layer, the gate metal stack being suitable for realizing gate electrode interconnection.

10. A ferroelectric transistor, comprising: A substrate; An N / P well layer, formed on the substrate, suitable for realizing the isolation of channel carriers from the substrate and avoiding the latch-up effect; A source electrode and a drain electrode, respectively formed on both sides of the N / P well layer; A gate, the structure of the gate being the gate structure according to claim 9, formed in the middle of the N / P well layer and serving as a gate, and when an external voltage is applied to the conductive layer of the gate stack structure, the ferroelectric layer is polarized, so that the gate structure outputs a gate voltage to control the state of the channel carriers and realize the opening and closing of the ferroelectric transistor.

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