Semiconductor material and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor material and a preparation method thereof, and the semiconductor material comprises a first silicon carbide layer; the first silicon carbide layer comprises a twin crystal structure and a non-twin crystal structure; the twin crystal structure is embedded into the non-twin crystal structure; the projection of the growth direction of the twin crystal structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is larger than the grain size of the non-twin structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a semiconductor material and a preparation method thereof. Background Art

[0002] Semiconductor materials, such as silicon carbide (SiC), as important third-generation semiconductor materials, have characteristics such as wide bandgap, high critical electric field, high thermal conductivity, and high carrier saturation drift velocity, and have broad application prospects in the fields of semiconductor lighting, next-generation mobile communication, smart grid, high-speed rail transit, new energy vehicles, and consumer electronics. They are key new materials that support the development of industries such as information, energy, transportation, and national defense.

[0003] In practical applications, the properties of silicon carbide, such as etching resistance, directly affect the lifespan of semiconductor devices. Therefore, how to improve the etching resistance of silicon carbide has become an urgent problem to be solved currently. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor material and a preparation method thereof. Among them, the semiconductor material provided by the embodiments of the present disclosure includes: a first silicon carbide layer; the first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure on the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure.

[0005] In some embodiments, the twin structure includes a plurality of twin crystals; adjacent twin crystals are in contact with each other.

[0006] In some embodiments, the plurality of twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction.

[0007] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between the plurality of grains in the non-twin structure.

[0008] In some embodiments, the atomic density of the twin structure is greater than the atomic density of the non-twin structure.

[0009] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are uniformly arranged along a direction perpendicular to the thickness extension direction.

[0010] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0011] In some embodiments, among the multiple sub-structure layers, some of the twin structures extend from one sub-structure layer to another along the thickness extension direction.

[0012] In some embodiments, among the multiple twin structures in each sub-structure layer, at least some of the twin structures have different sizes.

[0013] In some embodiments, among the multiple sub-structure layers, the sizes of the multiple twin structures in each sub-structure layer are randomly distributed.

[0014] In some embodiments, the semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of non-twin structures; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction.

[0015] A method for preparing a semiconductor material provided by an embodiment of the present disclosure, the method includes: forming a first silicon carbide layer through a chemical vapor deposition process to form the semiconductor material; wherein, the first silicon carbide layer includes twin structures and non-twin structures; the twin structures are embedded in the non-twin structures; the projection of the growth direction of the twin structures in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structures is greater than the grain size of the non-twin structures.

[0016] An embodiment of the present disclosure provides a semiconductor material and a method for preparing the same. The semiconductor material includes: a first silicon carbide layer; the first silicon carbide layer includes twin structures and non-twin structures; the twin structures are embedded in the non-twin structures; the projection of the growth direction of the twin structures in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structures is greater than the grain size of the non-twin structures. In the embodiments of the present disclosure, on the one hand, by adding twin structures with high etching resistance in the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Moreover, the twin structures can enable the first silicon carbide layer to more evenly distribute stress during the deformation process, avoid stress concentration, and thus improve the overall deformation ability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structures is parallel to or intersects with (excluding perpendicular) the thickness direction of the first silicon carbide layer, the twin interfaces can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and extending the service life of the device. On the further hand, when the growth direction of the twin structures is parallel to or intersects with (excluding perpendicular) the thickness direction of the first silicon carbide layer, the size of the twin structures in the thickness extension direction can be precisely controlled, and thus the strength and toughness of the twin structures can reach the optimum. In this way, the high-strength and high-plasticity characteristics of the first silicon carbide layer can be synchronously improved, and further the stability of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is an exemplary cross-sectional schematic diagram of a semiconductor material provided by an embodiment of the present disclosure; Figure 2 is a solid cross-sectional schematic diagram of a semiconductor material provided by an embodiment of the present disclosure; Figure 3 is Figure 2 an enlarged schematic diagram of a local area in Figure 4 is a schematic process flow diagram for forming a semiconductor material provided by an embodiment of the present disclosure; Figure 5 is a schematic diagram of the principle for forming a silicon carbide semiconductor material provided by an embodiment of the present disclosure.

[0018] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0020] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid confusion with the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0021] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present disclosure. And when discussing a second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0023] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0024] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0025] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other implementation manners.

[0026] Silicon carbide is a wide-bandgap semiconductor material with advantages such as high breakdown voltage, high thermal conductivity, and high electrical saturation mobility, making it suitable for harsh environments such as high temperature, high pressure, and high frequency. There are various crystal orientation structures of silicon carbide, such as hexagonal structure (α-SiC), cubic structure (β-SiC), rhombohedral structure, etc. Silicon carbides with different crystal orientation structures have different physical and chemical properties, making them applicable to different fields. Among them, the cubic structure (such as 3C-SiC) has characteristics such as high temperature resistance, high pressure resistance, and high electron mobility, and is applicable to power electronic devices such as high frequency, high power, high temperature resistance, and corrosion resistance. The hexagonal structure (such as 4H-SiC and 6H-SiC) has characteristics such as high hardness and high thermal conductivity, and is widely used in the semiconductor field, such as high-power electronic devices and optoelectronic devices. The rhombohedral structure (such as 15R-SiC) has good thermal stability and mechanical properties, and is applicable to fields such as aerospace and nuclear energy development.

[0027] In some embodiments, silicon carbide can also be divided into single-crystal silicon carbide and polycrystalline silicon carbide. Single-crystal silicon carbide can be applied to mechanical structure materials, semiconductor devices, power electricity, optoelectronics, etc. in high-temperature environments; polycrystalline silicon carbide can be applied to semiconductor devices, thin film coatings, magnetic materials, etc. In some possible embodiments, polycrystalline silicon carbide can be widely used in components of plasma etching machines. For example, polycrystalline silicon carbide is used to prepare components such as focusing rings and upper electrodes (shower heads that also provide entry holes for multiple etching gases) in plasma etching machines.

[0028] In practical applications, the etching resistance of polycrystalline silicon carbide directly affects the service life of these components. Among them, the higher the etching resistance of polycrystalline silicon carbide, the longer the service life of the components. The more uniform the etching resistance of polycrystalline silicon carbide, the better the etching stability of the components. Therefore, how to improve the etching resistance and etching uniformity of polycrystalline silicon carbide has become an urgent problem to be solved.

[0029] In view of this, to solve one or more of the above problems, an exemplary cross-sectional schematic diagram of a semiconductor material provided by the present disclosure is shown in Figure 1 and Figure 2 ; Figure 1 this semiconductor material can improve the etching resistance and etching uniformity of polycrystalline silicon carbide. Figure 2A schematic cross-sectional view of an entity of a semiconductor material provided by the present disclosure; the semiconductor material includes a first silicon carbide layer 102; the first silicon carbide layer 102 includes a twin structure 100, and the projection of the growth direction of the twin structure 100 in the thickness extension direction of the first silicon carbide layer is greater than zero.

[0030] It should be noted that due to its high strength, high toughness, high stability and other characteristics, the twin structure has higher etching resistance. Thus, in the embodiments of the present disclosure, on the one hand, by adding a twin structure with high etching resistance in the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Moreover, the twin structure can make the first silicon carbide layer distribute stress more evenly during the deformation process, avoid stress concentration, and thus improve the overall deformation ability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is the same as or intersects (excluding perpendicular) with the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and extending the service life of the device. On the further hand, when the growth direction of the twin structure is the same as or intersects (excluding perpendicular) with the thickness direction of the first silicon carbide layer, the size of the twin structure in the thickness extension direction can be precisely controlled, and then the strength and toughness of the twin structure can reach the optimum. In this way, the high-strength and high-plasticity characteristics of the first silicon carbide layer can be improved synchronously, and the stability of the device can be enhanced.

[0031] In the embodiments of the present disclosure, the projection of the growth direction of the twin structure 100 in the thickness extension direction of the first silicon carbide layer is greater than zero. That is to say, the growth direction of the twin structure 100 can be the same as / consistent with the thickness extension direction of the first silicon carbide layer 102, or can intersect with the thickness extension direction of the first silicon carbide layer 102. It should be emphasized that the intersection here does not include perpendicular. In other words, in some embodiments, the growth direction of the twin structure 100 can be parallel to the thickness extension direction of the first silicon carbide layer 102. In this way, the twin structure can guide the dislocations to extend along a certain direction, avoid their lateral expansion, and improve the reliability of the semiconductor material. In other embodiments, the growth direction of the twin structure 100 forms an acute angle with the thickness extension direction of the first silicon carbide layer 102, rather than being completely perpendicular, that is, the twin structure grows obliquely; among them, the grain boundaries in the oblique twin structure can effectively intercept penetrating dislocations (such as screw dislocations and edge dislocations), reduce the defect density, and improve the reliability of the semiconductor material. In addition, the oblique twin structure can release the lattice mismatch stress through the shear component, that is, release the epitaxial stress, reduce the cracks and stacking faults in the first silicon carbide layer, and improve the quality of the semiconductor material.

[0032] The semiconductor material and the twin structure provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Here, the twin structure 100 can be, for example, a silicon carbide twin.

[0033] In some embodiments, referring to Figure 3 , Figure 3 is Figure 2 a schematic enlarged view of a local area in . Among them, the twin structure 100 may include a plurality of twin crystals; adjacent twin crystals are in contact with each other. In this way, the grain boundary migration and crack propagation can be inhibited, the strength and hardness of the twin structure can be enhanced, and the stability of the twin structure can be improved.

[0034] In some embodiments, referring to Figure 3 , a plurality of twin crystals are symmetrically arranged along a direction perpendicular to the thickness extension direction. It should be understood that the symmetrical arrangement helps to improve the stability of the twin structure. Here, the thickness extension direction of the first silicon carbide layer is, for example, the Z-axis direction, and the direction perpendicular to the thickness extension direction is, for example, the X-axis direction or the Y-axis direction. In some possible embodiments, a plurality of twin crystals may form a mirror-symmetric orientation relationship along a common twin interface in their arrangement direction (the X-axis direction or the Y-axis direction). In this way, on the one hand, by introducing a high density of twin interfaces, the strength and hardness of the twin structure can be significantly improved without sacrificing the ductility of the material. On the other hand, the twin interface has a low interface energy, so that a plurality of twin crystals are very stable, and thus the twin structure can maintain good stability even in a high-temperature or high-stress environment.

[0035] In some embodiments, referring to Figure 1 and Figure 2 , the first silicon carbide layer 102 further includes a non-twin structure 200; the twin structure 100 is embedded in the non-twin structure 200; here, the area of the non-twin structure 200 is larger than the area of the twin structure 100. The non-twin structure 200 is, for example, polycrystalline silicon carbide. The polycrystalline silicon carbide may include a plurality of crystal orientations, such as the <111> crystal orientation, the <100> crystal orientation, etc., and the specific crystal orientations of the polycrystalline silicon carbide in the embodiments of the present disclosure are not limited.

[0036] In some possible embodiments, the size of the twin structure 100 is larger than the grain size of the non-twin structure 200. In this way, when the first silicon carbide layer is subjected to stress, the crack propagation can be restricted, and the toughness and crack resistance of the first silicon carbide layer can be improved.

[0037] In some embodiments, the porosity between a plurality of twin crystals is smaller than the porosity between a plurality of grains in the non-twin structure. In other words, the arrangement between a plurality of twin crystals is closer, so that the twin structure has a higher density. In this way, the mechanical properties, durability and corrosion resistance of the twin structure can be improved, and the thermal stability of the twin structure can be enhanced.

[0038] In some embodiments, the atomic density of the twin structure 100 is greater than that of the non-twin structure 200. Thus, the defect density of the twin structure can be reduced, and the stability and etching resistance of the twin structure and the first silicon carbide layer can be improved.

[0039] In some embodiments, a plurality of twin structures are uniformly distributed in the first silicon carbide layer. Thus, the etching uniformity (i.e., etching uniformity degree) of the first silicon carbide layer can be improved. Further, in the embodiments of the present disclosure, the etching uniformity of the first silicon carbide layer can be improved by adjusting the distribution position of the twin structure in the first silicon carbide layer.

[0040] In some embodiments, the first silicon carbide layer may include a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are uniformly arranged in a direction perpendicular to the thickness extension direction. Thus, the etching resistance and etching uniformity of each sub-structure layer can be improved.

[0041] In some possible embodiments, referring to Figure 1 , the first silicon carbide layer 102 may include a first sub-structure layer 1021, a second sub-structure layer 1022, and a third sub-structure layer 1023 stacked along the Z-axis direction. Each of the first sub-structure layer 1021, the second sub-structure layer 1022, and the third sub-structure layer 1023 includes a plurality of twin structures. The plurality of twin structures in each sub-structure layer are uniformly arranged in the X-axis direction / Y-axis direction. Thus, the etching resistance and etching uniformity of each sub-structure layer can be improved.

[0042] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are randomly arranged in a direction perpendicular to the thickness extension direction. Here, the randomly arranged twin structures can hinder the movement of dislocations in multiple directions to achieve a more uniform strengthening effect, avoid the mechanical property shortcoming of a single orientation, and improve the overall strength, toughness, and stability of the semiconductor material.

[0043] In some embodiments, in a plurality of sub-structure layers, some twin structures extend from one sub-structure layer to another sub-structure layer along the thickness extension direction. Thus, the adhesion between these two sub-structure layers can be improved, and the stability of the first silicon carbide layer in its thickness extension direction can be improved.

[0044] In some possible embodiments, referring to Figure 1 , a twin structure (such as the twin structure labeled 100a) extends from the first sub-structure layer 1021 to the second sub-structure layer 1022 along the Z-axis direction. Thus, the adhesion performance between the first sub-structure layer 1021 and the second sub-structure layer 1022 can be improved, and the stability of the first silicon carbide layer in the Z-axis direction can be improved.

[0045] In some embodiments, among the multiple twin structures in each substructural layer, at least some of the twin structures have different sizes. In this way, the etching uniformity resistance of the first silicon carbide layer can be further improved.

[0046] In some possible embodiments, referring to Figure 1 , the multiple twin structures in the third substructural layer 1023 include a first twin structure 100b, a second twin structure 100c, and a third twin structure 100d. The sizes of the first twin structure 100b, the second twin structure 100c, and the third twin structure 100d are all different. In this way, stress can be dispersed within the third substructural layer 1023 to form a gradient distribution or a non-uniform distribution, thereby improving the overall strength and toughness of the third substructural layer 1023.

[0047] In some other possible embodiments, the second twin structure 100c in the third substructural layer 1023 may have the same size as the fourth twin structure 100e in the first substructural layer 1021. In this way, the damage distribution received by different substructural layers can be made more uniform, avoiding the rapid expansion of local damage. In other words, if some of the twin structures in the first silicon carbide layer have the same size and some have different sizes, the stress concentration in the first silicon carbide layer can be reduced, and the etching uniformity resistance of the first silicon carbide layer can be further improved.

[0048] In some embodiments, among the multiple substructural layers, the sizes of the multiple twin structures in each substructural layer are randomly distributed. In other words, the sizes of the multiple twin structures in the first silicon carbide layer are randomly distributed. In this way, the generation of internal defects can be reduced, thereby improving the fatigue resistance of the first silicon carbide layer, reducing the concentration of local stress in the first silicon carbide layer, and enhancing the crack resistance and etching uniformity resistance of the first silicon carbide layer.

[0049] In some possible embodiments, among the multiple twin structures in each substructural layer, the larger twin structures are evenly distributed, and the smaller twin structures are randomly arranged. In this way, the etching uniformity of the substructural layer and the semiconductor material can be further improved, and the generation of particles can be reduced.

[0050] In some embodiments, the semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of non-twin structures; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction. In this way, the crack probability of the semiconductor material in its thickness extension direction can be reduced, and the etching resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) can be enhanced.

[0051] In some possible embodiments, referring to Figure 1, the semiconductor material may include two layers of second silicon carbide layers, namely a bottom second silicon carbide layer 101 and a top second silicon carbide layer 103. The first silicon carbide layer 102 is located between the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103. The constituent materials of the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 may be the same, such as both being composed of a non-twin structure, that is, both the bottom second silicon carbide layer 101 and the top second silicon carbide layer 103 are polycrystalline silicon carbide.

[0052] It should be noted that in the later processing of the semiconductor material, processes such as grinding and polishing that may be used are likely to form cracks in the growth direction (i.e., the thickness extension direction); in this case, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can reduce the elastic deterioration of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) and improve the etching resistance of the semiconductor material in the growth direction. In other words, forming a second silicon carbide layer on at least one side of the first silicon carbide layer can not only improve the etching rate of the semiconductor material in the growth direction but also avoid generating cracks extending along the growth direction during the processing.

[0053] In other embodiments, the semiconductor material may also include only one layer of second silicon carbide layer, and this layer of second silicon carbide layer is stacked with the first silicon carbide layer along the Z-axis direction. Specifically, this layer of second silicon carbide layer may be Figure 1 the bottom second silicon carbide layer 101 in Figure 1 or the top second silicon carbide layer 103 in . In this way, the probability of generating longitudinal cracks due to the excessive size of the twin structure in the Z-axis direction can be reduced, and the quality and reliability of the semiconductor material can be improved.

[0054] Based on this, in the embodiments of the present disclosure, on the one hand, by adding a twin structure with high etching resistance to the first silicon carbide layer, the etching resistance of the first silicon carbide layer can be increased. Moreover, the twin structure can enable the first silicon carbide layer to more evenly distribute stress during the deformation process, avoiding stress concentration, thereby improving the overall deformation ability of the first silicon carbide layer. On the other hand, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the twin interface can effectively hinder the movement of dislocations, thereby improving the strength of the first silicon carbide layer and extending the service life of the device. Moreover, when the growth direction of the twin structure is consistent with the thickness direction of the first silicon carbide layer, the size of the twin structure in the thickness extension direction can be precisely controlled, and thus the strength and toughness of the twin structure can reach the optimum. In this way, the high-strength and high-plasticity characteristics of the first silicon carbide layer can be synchronously improved, and the stability of the device can be improved. On the other hand, the etching uniformity of the first silicon carbide layer can be improved by adjusting the distribution position of the twin structure in the first silicon carbide layer. By operating in this way, the service life of the device can be extended, and the stability of the device can be improved.

[0055] Based on the above semiconductor material, an embodiment of the present disclosure provides a method for preparing a semiconductor material. Refer to Figure 4 , Figure 4 which is a schematic process flow diagram for forming a semiconductor material provided by an embodiment of the present disclosure. Wherein, the method includes the following steps: Step S401: Form a first silicon carbide layer through a chemical vapor deposition process to form a semiconductor material. Wherein, the first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is larger than the grain size of the non-twin structure. Here, the twin structure includes silicon carbide twins.

[0056] It should be noted that the preparation process of the semiconductor material may include, for example, a solid-phase method, such as a carbothermal reduction method, a direct silicon-carbon reaction method, etc. A liquid-phase method (LPE, Liquid Phase Epitaxy), such as a sol-gel method, a polymer pyrolysis method, etc. A gas-phase method, such as a chemical vapor deposition method (CVD, Chemical Vapor Deposition), a physical vapor transport method (PVT, Physical Vapor Transport), and a high-temperature chemical vapor deposition method (HTCVD, High Temperature Chemical Vapor Deposition), a thermal decomposition method, a plasma method, a laser-induced gas-phase method, etc. The present disclosure does not limit this.

[0057] In an embodiment of the present disclosure, taking the formation of a semiconductor material by a chemical vapor deposition method (CVD) and the semiconductor material being a silicon carbide structure as an example for illustration. Wherein, the process of depositing to form a silicon carbide structure may include the following steps: providing a substrate and a CVD reaction device; placing the substrate on a pedestal in the CVD reaction chamber. Wherein, the substrate may include, but is not limited to, a graphite substrate.

[0058] Set a specific reaction pressure and a specific reaction temperature for the CVD reaction chamber, and while maintaining the specific reaction pressure and the specific reaction temperature, mix and inject a main reaction gas and a carrier gas into the reaction chamber (Chamber) for deposition. The main reaction gas may include a single-component reaction gas and a binary-component reaction gas. The single-component reaction gas is, for example, methyltrichlorosilane (MTS), dimethyldichlorosilane (DDS), trimethylchlorosilane (TCS), etc. The binary-component reaction gas may, for example, include a silane-based and a carbon-based. The carrier gas may, for example, be hydrogen and argon, etc.

[0059] For the sake of clear understanding, here and hereinafter, trichloromethylsilane (MTS) is taken as an example of the main reaction gas for illustration. It should be understood that the description of the reaction gas hereinafter is only for illustrating the present disclosure and does not limit the scope of the present disclosure.

[0060] In some possible embodiments, in the process of forming a silicon carbide structure on a graphite substrate using a system with MTS as the main reaction gas and hydrogen as the carrier gas, it is a process of a series of complex chain reactions between diluted gaseous MTS and excessive hydrogen near the substrate surface and the step-by-step condensation growth of gas-phase particles on the substrate surface. It mainly includes intermediate-phase reactions, decomposition, surface adsorption, and catalysis based on polyvalent and polyphase free radicals. During the deposition process, too high or too low values of process parameters such as the deposition temperature and the partial pressure of each gas-phase reactant will cause different changes in the reaction rates of each intermediate reaction, which can change the slowest step of the reaction process, resulting in changes in reaction products and different deposition structures. Therefore, different semiconductor materials can be obtained by adjusting the specific reaction pressure and the specific reaction temperature.

[0061] During the deposition process of preparing a silicon carbide structure from MTS, referring to Equation 1, Equation 1 provides the reaction formula of the total deposition reaction. The total deposition reaction can include three steps. In the first step, MTS is thermally decomposed in sequence into groups containing silicon element, carbon element, and chlorine element, referring to Equations 2 and 3; in the second step, several groups SiCl2 / CH2 formed by the first thermal decomposition are adsorbed onto the substrate and undergo secondary thermal decomposition, referring to Equations 4 and 5; in the third step, the mutual reaction between the groups adsorbed on the substrate is shown in Equation 6. Of course, the silicon element and the carbon element can react with each other to form silicon carbide, or form silicon carbide and silicon element, or form silicon carbide and carbon element.

[0062] (Equation 1) (Equation 2) (Equation 3) (Equation 4) (Equation 5) (Equation 6) Specifically, as Figure 5As shown, the steps of forming a silicon carbide structure may include: (1) transport of reactants, i.e., delivering gaseous reactants into a chemical vapor deposition reactor (i.e., a reaction chamber); (2) precursor reaction, i.e., the reaction gas undergoes a first thermal decomposition reaction to form groups containing silicon element, carbon element, and chlorine element; (3) gas molecule diffusion, i.e., the groups formed by the first thermal decomposition reaction diffuse; (4) precursor adsorption, i.e., the groups formed by the first thermal decomposition reaction are adsorbed onto the substrate; (5) the precursors diffuse into the substrate; (6) surface reaction, i.e., the groups adsorbed on the substrate react with each other to form a continuous silicon carbide structure; (7) desorption of by-products, i.e., desorbing the by-products adsorbed on the substrate; (8) removal of by-products, i.e., discharging the by-products from the outlet out of the reaction chamber.

[0063] Here, the silicon carbide structure may include a first silicon carbide layer. In other words, the first silicon carbide layer can be formed by the above method.

[0064] In some embodiments, the crystal orientation type of the semiconductor material can be adjusted by controlling different reaction parameters (such as a specific reaction pressure and a specific reaction temperature).

[0065] In some embodiments, the twin structure may include a plurality of twin crystals; adjacent said twin crystals are in contact with each other.

[0066] In some embodiments, the plurality of twin crystals are symmetrically arranged in a direction perpendicular to the thickness extension direction.

[0067] In some possible embodiments, the non-twin structure includes polycrystalline silicon carbide.

[0068] In some embodiments, the porosity between the plurality of twin crystals is less than the porosity between the plurality of grains in the non-twin structure.

[0069] In some embodiments, the atomic density of the twin structure is greater than the atomic density of the non-twin structure.

[0070] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

[0071] In some embodiments, the first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

[0072] In some embodiments, among the plurality of sub-structure layers, some twin structures extend from one sub-structure layer to another along the thickness extension direction.

[0073] In some embodiments, among the multiple twin structures in each substructure layer, at least some of the twin structures have different sizes.

[0074] In some embodiments, among the multiple substructure layers, the sizes of the multiple twin structures in each substructure layer are randomly distributed. In this way, the etching uniformity resistance of the first silicon carbide layer can be enhanced, and the generation of particles can be reduced.

[0075] In some embodiments, the method further includes: forming a second silicon carbide layer on at least one side of the first silicon carbide layer along the thickness extension direction. The second silicon carbide layer is composed of non-twin structures.

[0076] In some possible embodiments, the second silicon carbide layer may be located only on one side of the first silicon carbide layer along the thickness extension direction, or may be located on opposite sides of the first silicon carbide layer along the thickness extension direction respectively. In this way, the crack probability of the semiconductor material in the thickness extension direction can be reduced, and the etching resistance of the semiconductor material in the horizontal direction (i.e., perpendicular to the thickness extension direction) can be enhanced.

[0077] In some possible embodiments, the method may specifically include: forming a bottom second silicon carbide layer on a substrate, forming a first silicon carbide layer on the bottom second silicon carbide layer, and forming a top second silicon carbide layer on the first silicon carbide layer. In this way, a second silicon carbide layer can be formed on each of the opposite sides of the first silicon carbide layer along the growth direction, so as to further improve the quality and reliability of the semiconductor material.

[0078] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution is prior or subsequent, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0079] The above description is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor material, characterized in that, Comprising: A first silicon carbide layer; The first silicon carbide layer includes a twin structure and a non-twin structure; The twin structure is embedded in the non-twin structure; The projection of the growth direction of the twin structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure.

2. The semiconductor material according to claim 1, wherein, The twin structure includes a plurality of twin crystals; adjacent twin crystals are in contact with each other.

3. The semiconductor material according to claim 2, characterized in that, The plurality of twin crystals are symmetrically arranged in a direction perpendicular to the thickness extension direction.

4. The semiconductor material according to claim 2, wherein, The porosity between the plurality of twin crystals is less than the porosity between the plurality of grains in the non-twin structure.

5. The semiconductor material according to claim 1, characterized in that, The atomic density of the twin structure is greater than the atomic density of the non-twin structure.

6. The semiconductor material according to claim 5, wherein The first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are uniformly arranged in a direction perpendicular to the thickness extension direction.

7. The semiconductor material according to claim 5, characterized in that, The first silicon carbide layer includes a plurality of sub-structure layers stacked along the thickness extension direction; wherein, the plurality of twin structures in each sub-structure layer are randomly arranged in a direction perpendicular to the thickness extension direction.

8. The semiconductor material according to claim 6 or 7, characterized in that, Among the plurality of sub-structure layers, part of the twin structures extend from one sub-structure layer to another sub-structure layer along the thickness extension direction.

9. The semiconductor material according to claim 6 or 7, characterized in that, Among the plurality of twin structures in each sub-structure layer, at least part of the twin structures have different sizes.

10. The semiconductor material according to claim 6 or 7, characterized in that, Among the plurality of sub-structure layers, the sizes of the plurality of twin structures in each sub-structure layer are randomly distributed.

11. The semiconductor material according to any one of claims 1 to 3, characterized in that, The semiconductor material further includes: a second silicon carbide layer; the second silicon carbide layer is composed of a non-twin structure; the second silicon carbide layer and the first silicon carbide layer are alternately stacked along the thickness extension direction.

12. A method for preparing a semiconductor material, characterized in that, The method includes: Forming a first silicon carbide layer by chemical vapor deposition to form the semiconductor material; wherein, the first silicon carbide layer includes a twin structure and a non-twin structure; the twin structure is embedded in the non-twin structure; the projection of the growth direction of the twin structure in the thickness extension direction of the first silicon carbide layer is greater than zero; the size of the twin structure is greater than the grain size of the non-twin structure.

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