Processor-based system for allocating cache lines to higher-level cache memory

Abstract

A processor-based system for allocating a higher-level cache line in a higher-level cache memory in response to an eviction request for the lower-level cache line is disclosed. The processor-based system determines whether the cache line is opportunistic, sets an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicates the lower-level cache line and the opportunistic indicator. The processor-based system determines whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has a lower or equal importance than the lower-level cache line based on the opportunistic indicator of the lower-level cache line. In response, the processor-based system replaces the higher level cache line in the higher level cache memory with the lower level cache line, and associates the opportunistic indicator with the lower level cache line in the higher level cache memory.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 387,519, filed on December 15, 2022, entitled "PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY", which is hereby incorporated by reference in its entirety.

[0003] This application also claims priority to U.S. Patent Application Serial No. 18 / 169,852, filed on February 15, 2023, entitled "PROCESSOR-BASED SYSTEM FOR ALLOCATING CACHE LINES TO A HIGHER-LEVEL CACHE MEMORY", which is hereby incorporated by reference in its entirety. Background

[0005] I. Technical Field

[0006] The field of the present disclosure relates to cache memories in processor-based systems (e.g., graphics processing unit (GPU)-based systems, central processing unit (CPU)-based systems), and more particularly to methods for improving cache hit ratios in higher-level cache memories.

[0007] II. Background Art

[0008] A microprocessor, also known as a processing unit (PU), performs computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is a central processing unit (CPU). Another type of microprocessor or PU is a specialized processing unit called a graphics processing unit (GPU). The GPU is designed with specialized hardware to accelerate the rendering of graphics and video data to be displayed. The GPU can be implemented as an integrated element of a general-purpose CPU or as a discrete hardware element separate from the CPU. The PU executes software instructions that direct the processor to obtain data from a location in memory and use the obtained data to perform one or more processor operations. The result can then be stored in memory. For example, the memory can be a cache memory local to the PU, a shared local cache between PUs in a PU block, a shared cache between multiple PU blocks, and / or a system memory in a processor-based system. A cache memory (which can also be referred to simply as a "cache") is a smaller, faster memory that stores copies of data stored at frequently accessed memory addresses in main memory or a higher-level cache memory to reduce memory access latency. Thus, the PU can use the cache memory to reduce memory access time.

[0009] When the data requested by a memory read request is present in the cache memory (i.e., a cache "hit"), system performance can be improved by retrieving the data from the cache rather than from the slower access system memory. Conversely, if the requested data is not found in the cache (resulting in a cache "miss"), the requested data must be read from a higher-level cache memory or system memory. Frequent cache misses lead to a degradation of system performance, which may first negate the advantages of using a cache. The cache hit rate of a cache memory can generally be improved by increasing the size of the cache memory, since a larger-sized cache memory can store more cache lines, thereby increasing the likelihood of cache hits. However, increasing the size of the cache memory incurs an increased cost in terms of increased area and power consumption.

[0010] Returning to the situation when the requested data is read from a higher-level cache memory or system memory upon a cache miss, the requested data is typically stored in the cache memory local to the PU for later use. Frequently writing the requested data to the local cache will cause an existing cache line from the local cache to be evicted. The evicted cache line may need to be written to the higher-level cache memory for subsequent sharing among other PUs. Therefore, the higher-level cache memory is typically larger than the lower-level cache memory and may contain many unallocated or invalid cache lines. Whether to write the evicted line to the higher-level cache memory or allocate it to the higher-level cache memory can affect the cache hit rate of the higher-level cache memory and the performance of the PUs sharing the higher-level cache memory. SUMMARY OF THE INVENTION

[0011] Aspects disclosed in the detailed description include a processor-based system for allocating cache lines to a higher-level cache memory in response to an eviction request for a lower-level cache line. Related processor-based apparatus and methods are also disclosed. In an exemplary aspect, a cache allocation circuit is provided as part of a processor-based system. As an example, a processor-based system can include a processing unit (PU), such as a central processing unit (CPU) and / or a dedicated PU (such as a graphics processing unit (GPU)). The processor-based system also includes a multi-level cache system and a system memory. Since the lower-level cache memory is closer to the PU than the higher-level cache memory, data retrieved from the lower-level cache memory is faster than data retrieved from the higher-level cache memory. The highest-level cache memory is the last level of cache memory before accessing data from the system memory. The system memory contains the complete physical address space of the memory, while each level of the multi-level cache system does not. Since the higher-level cache memory is shared by multiple PUs when a cache line is evicted from the lower-level cache memory, the cache line may or may not be written to the higher-level cache memory. Heuristics or filters are applied to determine whether the evicted cache line is known to be useful (i.e., more likely to be accessed again in the cache memory before being evicted to the system memory), and if not useful, the cache line is opportunistic (i.e., less likely to be accessed again in the cache memory before being evicted to the system memory). Opportunistic cache lines have a lower importance compared to useful cache lines. However, some conventional cache allocation systems are designed not to allocate evicted cache lines that are not useful to the next higher-level cache. If the higher-level cache line in the higher-level cache memory (to which the lower-level cache line can be written) has a lower or equal importance compared to the lower-level cache line, the lower-level cache line will replace the data at that location in order to better utilize the higher-level cache memory with more important cache lines. As an example, an unallocated invalid cache line in the higher-level cache memory will be replaced with an opportunistic lower-level cache line. However, if the higher-level cache line has a higher importance compared to the lower-level cache line, the lower-level cache line will not overwrite the higher-level location in order not to contaminate the higher-level cache memory with less important data.

[0012] In this regard, in an exemplary aspect disclosed herein, when evicting a lower-level cache line in a processor-based system, the processor-based system will determine whether the cache line is opportunistic. The processor-based system will set an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicate the lower-level cache line and the opportunistic indicator to a higher-level cache memory (e.g., the next higher-level cache memory). The processor-based system determines whether at least one of the higher-level cache lines in the higher-level cache memory (e.g., the next higher-level cache memory) has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. In response to determining that the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line, the processor-based system replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line, and associates the opportunistic indicator with the lower-level cache line in the higher-level cache memory. In this example, the higher-level cache memory is utilized more highly with more important cache lines.

[0013] However, in another example, if it is determined that the higher-level cache line in the higher-level cache memory has higher importance compared to the evicted lower-level cache line, the evicted lower-level cache line is not written to the higher-level cache line. Instead, the higher-level cache memory is bypassed such that the evicted lower-level cache line is considered to replace a cache line in the next higher-level cache line, or is written back to the system memory. In this way, if the evicted lower-level cache line has lower importance compared to the next higher-level cache line, not writing it to the next higher-level cache memory can avoid contaminating the next higher-level cache memory.

[0014] Note that in another example, if it is determined that a first higher-level cache line in a higher-level cache memory has a higher importance compared to the evicted lower-level cache line, and there is another second higher-level cache memory between the first higher-level cache memory and the system memory, the processor-based system can also perform the same function. In this regard, the processor-based system can again determine whether at least one higher-level cache line among a plurality of higher-level cache lines in the second higher-level cache memory has a lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. In response to determining that the higher-level cache line in the second higher-level cache memory has a lower or equal importance compared to the lower-level cache line, the processor-based system replaces the higher-level cache line in the second higher-level cache memory with the lower-level cache line and associates the opportunistic indicator with the lower-level cache line in the second higher-level cache memory. If it is determined that the higher-level cache line in the second higher-level cache memory has a higher importance compared to the evicted lower-level cache line, the evicted lower-level cache line is not written to the second higher-level cache line and can be considered to be written to the next third higher-level cache memory (if any) or to the system memory.

[0015] In this regard, in one aspect, a processor-based system for allocating cache lines to a higher-level cache memory is disclosed. The processor-based system includes a lower-level cache memory configured to store data. The processor-based system is configured to, in response to an eviction request for a lower-level cache line in the lower-level cache memory, determine whether the lower-level cache line is opportunistic, set an opportunistic indicator to indicate whether the lower-level cache line is opportunistic, communicate the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory, and determine whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has a lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. In response to determining that the higher-level cache line has a lower or equal importance compared to the lower-level cache line, the processor-based system is configured to replace the higher-level cache line in the higher-level cache memory with the lower-level cache line and associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0016] In another aspect, a method for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory is disclosed. The method includes: determining whether the lower-level cache line is opportunistic, setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic, communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory, and determining whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. The method further includes: in response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line, replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line, and associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0017] In another aspect, a processor-based system for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory is disclosed. The processor-based system includes: means for determining whether the lower-level cache line is opportunistic; means for setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic; means for communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory; and means for determining whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. The processor-based system further includes: in response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line, means for replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and means for associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1is a block diagram of an exemplary processor-based system that includes a plurality of central processing units (CPUs) and a memory system that includes a cache memory system that includes a hierarchy of local and shared cache memories and a system memory, and wherein the processor-based system includes an exemplary cache allocation circuit that is configured to determine whether a higher-level cache line in a higher-level cache memory has lower or equal importance compared to a lower-level cache line based on a snoop indicator associated with the evicted lower-level cache line in order to replace the higher-level cache line in the higher-level cache memory;

[0019] Figure 2 is an illustration Figure 1 of a hierarchical structure diagram of exemplary relative importance of cache lines in a shared cache system;

[0020] Figure 3 is Figure 1 a block diagram of two exemplary alternative formats of an exemplary CPU, local cache, and shared system cache memory of a cache memory system in and cache lines stored in the local cache and the shared system cache memory;

[0021] Figure 4 is an illustration of a process for allocating a lower-level cache line from a lower-level cache memory to a higher-level cache memory in a processor-based system that includes Figure 1 and Figure 3 a flowchart of an exemplary process in a processor-based system;

[0022] Figure 5 is an illustration of an exemplary process for determining whether a lower-level cache line has lower or equal importance compared to a higher-level cache line in an exemplary process in Figure 4 a flowchart of an exemplary process;

[0023] Figure 6 is a flowchart of an exemplary process for retrieving a snoop indicator of a cache line that has been previously determined to be snooped;

[0024] Figure 7A is an illustration when the cache allocation circuit uses a modified least recently used technique to select among higher-level cache lines in the same cache way in a higher-level cache memory Figure 2 a hierarchical structure diagram of another example of the relative importance hierarchy in;

[0025] Figure 7B is an illustration when Figure 3The cache allocation circuit uses a modified least recently used technique to select between higher-level cache lines in the same way in the Figure 1 higher-level cache memory for eviction when Figure 2 Hierarchical structure diagram of another example of the relative importance hierarchical structure in

[0026] Figure 8A Illustrate two examples of four (4) higher-level cache lines returned in a 4-way higher-level cache to show examples of selection to sacrifice between higher-level cache lines when using the modified least recently used method to allocate sacrificed cache lines from the lower-level cache memory;

[0027] Figure 8B Illustrate two examples of four (4) higher-level cache lines returned in a 4-way higher-level cache to show examples of selection to sacrifice between higher-level cache lines when using the modified least recently used method to allocate sacrificed cache lines from the lower-level cache;

[0028] Figure 9 Illustrate showing before and after using the Figure 1 and Figure 3 cache allocation circuit of Figure 1 and Figure 3 two graphs of the utilization rate of the higher-level cache memory; and

[0029] Figure 10 is a block diagram of an exemplary processor-based system, which may include Figure 1 and Figure 3 the cache allocation circuit of DETAILED DESCRIPTION

[0030] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or having an advantage over other aspects.

[0031] Aspects disclosed in the detailed description include a processor-based system for allocating cache lines to a higher-level cache memory in response to an eviction request for a lower-level cache line. Related processor-based apparatus and methods are also disclosed. In an exemplary aspect, a cache allocation circuit is provided as part of a processor-based system. As an example, a processor-based system may include a processing unit (PU), such as a central processing unit (CPU) and / or a dedicated PU (such as a graphics processing unit (GPU)). The processor-based system also includes a multi-level cache system and system memory. Since the lower-level cache memory is closer to the PU than the higher-level cache memory, data retrieved from the lower-level cache memory is faster than data retrieved from the higher-level cache memory. The highest-level cache memory is the last level of cache memory before accessing data from the system memory. The system memory contains the complete physical address space of the memory, while each level of the multi-level cache system does not. Since the higher-level cache memory is shared by multiple PUs when a cache line is evicted from the lower-level cache memory, the cache line may or may not be written to the higher-level cache memory. Heuristics or filters are applied to determine whether the evicted cache line is known to be useful (i.e., more likely to be accessed again in the cache memory before being evicted to the system memory), and if not useful, the cache line is opportunistic (i.e., less likely to be accessed again in the cache memory before being evicted to the system memory). Opportunistic cache lines have a lower importance compared to useful cache lines. However, some conventional cache allocation systems are designed not to allocate evicted cache lines that are not useful for the next higher-level cache. If a higher-level cache line in the higher-level cache memory (to which the lower-level cache line may be written) has a lower or equal importance compared to the lower-level cache line, the lower-level cache line will replace the data at that location in order to better utilize the higher-level cache memory with more important cache lines. As an example, an unallocated invalid cache line in the higher-level cache memory will be replaced with an opportunistic lower-level cache line. However, if the higher-level cache line has a higher importance compared to the lower-level cache line, the lower-level cache line will not overwrite that higher-level location in order not to contaminate the higher-level cache memory with less important data.

[0032] In this regard, in the exemplary aspects disclosed herein, when evicting a lower-level cache line in a processor-based system, the processor-based system will determine whether the cache line is opportunistic. The processor-based system will set an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicate the lower-level cache line and the opportunistic indicator to a higher-level cache memory (e.g., the next higher-level cache memory). The processor-based system determines whether at least one of the higher-level cache lines in the higher-level cache memory (e.g., the next higher-level cache memory) has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. In response to determining that the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line, the processor-based system replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line and associates the opportunistic indicator with the lower-level cache line in the higher-level cache memory. In this example, the higher-level cache memory is utilized more highly with more important cache lines.

[0033] For example, Figure 1 is a block diagram of an exemplary processor-based system 100 that is configured to determine whether a higher-level cache line in a higher-level cache memory should be replaced with an evicted lower-level cache line based on an opportunistic indicator associated with the evicted lower-level cache line. Before discussing these aspects, other exemplary aspects of the processor-based system 100 are first described below.

[0034] The processor-based system 100 includes multiple (multi) central processing units (CPUs) (multi-CPUs) processors 102, which include multiple CPUs 104(0)-104(N) and a hierarchical memory system. As part of the hierarchical memory system, for example, CPU 104(0) includes a private local cache memory 106, which can be a level 2 (L2) cache memory. CPUs 104(1), 104(2) and CPUs 104(N-1), 104(N) are configured to interface with corresponding local shared cache memories 106S(0)-106S(X), which can also be, for example, L2 cache memories. If a data read request made by CPUs 104(0)-104(N) results in a cache miss in the corresponding cache memories 106, 106S(0)-106S(X), the read request can be communicated to the next level of cache memory, which is the shared system cache memory 108 in this example. For example, the shared cache memory 108 can be a level 3 (L3) cache memory. The cache memory 106, the local shared cache memories 106S(0)-106S(X) and the shared cache memory 108 are part of a hierarchical cache memory system 110. An interconnect bus 112, which can be a coherent bus, is provided, which allows each of CPUs 104(0)-104(N) to access the local shared cache memories 106S(0)-106S(X) (if shared to CPUs 104(0)-104(N)), the shared cache memory 108 and other shared resources coupled to the interconnect bus 112.

[0035] Figure 1The processor-based system 100 therein includes a cache allocation circuit 113 configured to allocate or write a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line. The cache allocation circuit 113 can be distributed between a local cache allocation circuit 113(0) residing in any or all of the CPUs 104(0-N) and a remote cache allocation circuit 113(1) residing in the multi-CPU processor 102. The remote cache allocation circuit 113(1) can alternatively reside in the interconnect bus 112 or any other higher-level cache memory (such as the shared system cache memory 108). In this example, in response to an eviction request for a lower-level cache line from the cache memory 106 or the local shared cache memories 106S(0)-106S(X), the cache allocation circuit 113 determines whether the lower-level cache line is opportunistic. An opportunistic cache line is less likely to be reused by subsequent memory addresses compared to a useful cache line. A varying heuristic (such as the amount of time taken to retrieve the lower-level cache line from the higher-level cache memory) is applied to the lower-level cache line to determine whether the lower-level cache line is useful, and if not useful, the lower-level cache line is opportunistic. A threshold determined by the heuristic between useful and opportunistic cache lines can be programmed or defined by the designer. The local cache allocation circuit 113(0) sets an opportunistic indicator associated with the lower-level cache line to indicate whether the lower-level cache line is useful or opportunistic. The description associated with Figure 3 will discuss in more detail an exemplary manner for associating the opportunistic indicator with the lower-level cache line. The local cache allocation circuit 113(0) conveys the lower-level cache line and the opportunistic indicator to the remote cache allocation circuit 113(1) in the multi-CPU processor 102 via the interconnect bus 112. In the architecture bus, user-defined bits in the defined architecture of ARM can be used to carry the opportunistic indicator between the local cache allocation circuit 113(0) and the remote cache allocation circuit 113(1).

[0036] The remote cache allocation circuit 113(1) determines whether a higher-level cache line in a plurality of higher-level cache lines in a higher-level cache memory (such as the shared system cache memory 108) has lower or equal importance compared to a lower-level cache line based on the snoop indicator of the lower-level cache line. For example, if the lower-level cache line is snooped and the higher-level cache line that can be displaced by the lower-level cache line is snooped or invalid (not previously allocated), the remote cache allocation circuit 113(1) replaces the higher-level cache line in the shared system memory 108 with the lower-level cache line and associates the snoop indicator with the replaced higher-level cache line in the shared system cache memory 108.

[0037] Figure 2 is illustrative Figure 1 Hierarchical structure diagram of the exemplary relative importance of cache lines in a shared cache system. The useful cache line 200(0) is more important than the snooped cache line 200(1) and the invalid cache line 200(2). The snooped cache line 200(1) is more important than the invalid cache line 200(2). When the cache allocation circuit 113(1) compares the relative importance between a lower-level cache line in a lower-level cache memory and a higher-level cache line in a higher-level cache memory, if the two lines have the same importance, the cache allocation circuit 113(1) will replace the higher-level cache line.

[0038] Continuing to refer to Figure 1 , in this example, the processor-based system 100 further includes a snoop controller 114, which is also coupled to the interconnect bus 112. The snoop controller 114 is a circuit that monitors or snoops cache memory bus transactions on the interconnect bus 112 to maintain cache coherence among the cache memories 106, 106S(0)-106S(X), 108 in the cache memory system 110. Other shared resources accessible by the CPUs 104(0)-104(N) through the interconnect bus 112 may include input / output (I / O) devices 116 and system memory 118 (e.g., dynamic random access memory (DRAM)). If a read request issued by the CPUs 104(0)-104(N) results in a cache miss in each level of the cache memories 106, 106S(0)-106S(X), 108 accessible by the CPUs 104(0)-104(N), the read request is serviced by the system memory 118, and the data associated with the read request is installed in the cache memories 106, 106S(0)-106S(X), 108 associated with the requested CPUs 104(0)-104(N).

[0039] Figure 3 is Figure 1 Block diagrams of two exemplary alternative formats of cache lines that can be stored in the CPU 0 104(0), local cache memory 106, and shared system cache memory 108 of the cache memory system 110 in . A cache line includes at least one set of cache lines that resolve to the same hash. Figure 3 Also applicable to Figure 1 CPUs 1 - CPU N and shared L2 cache memories 106S(0) - 106S(X) in Figure 3 . The local cache memory 106 includes an M-way cache 300. The CPU 0 includes a hashing circuit 302. The hashing circuit 302 hashes a memory address to access a cache line including M cache lines in the local cache memory 106. The shared system cache memory 108 includes a hashing circuit 304 and an N-way cache 306. The hashing circuit 304 hashes a memory address to access a cache line including N cache lines. In Figure 3 Figure 3 , all cache lines in the same cache line are shown in the same row of the M-way cache 300 and the N-way cache 306. M and N may be equal or may not be equal.

[0040] The exemplary cache line 307(H) may have one of two alternative formats (format 310A or format 310B). When the cache allocation circuit 113(1) selects between higher-level cache lines in the same cache line to be replaced by a lower-level cache line, formats 310A and 310B are used to utilize a hierarchical structure with a finer granularity of importance than the hierarchical structure in Figure 2 Figure 3 , and will be discussed in conjunction with FIGS. 7 and 8. The exemplary cache line 307(L) may also utilize format 310A or format 310B.

[0041] Format 310A includes data 312, an optional dirty bit 314, a speculative indicator 316, and a priority indicator 318. The dirty bit 314 indicates whether the exemplary cache line 308(L) or 308(H) has been written since it was initially stored in the M-way cache 300 or the N-way cache 306, respectively. The speculative indicator 316 indicates whether the exemplary cache line 308(L) or 308(H) is useful or speculative. The priority indicator 318A is utilized when the cache memory 106 or the shared system cache memory 108 deploys a modified least recently used technique in selecting between cache lines in the same cache way for replacement. The priority indicator 318A is set when a cache line is read and reset when all cache lines in the same cache way have been read. When selecting between cache lines in the same cache way for replacement, the priority indicator and the speculative indicator are used to determine which cache line in the same cache way is the least important, which will be further discussed in conjunction with FIGS. 7-8.

[0042] An alternative format 310B includes data 312, an optional dirty bit 314, a speculative indicator 316 for each allocated cache line in the same cache way, and an LRU field 318B for the cache way, which is encoded to maintain the least recently used order of all cache lines in the same cache way. The LRU field 318B is utilized when the cache memory 106 or the shared system cache memory 108 deploys a modified least recently used technique in selecting between cache lines in the same cache way for replacement.

[0043] Formats 310A and 310B are used by the cache allocation circuit 113(1) to select between higher-level cache lines in the same way, which will be further discussed in conjunction with FIGS. 7-8.

[0044] Figure 4 is an example of a process 400 for allocating a lower-level cache line from a lower-level cache memory to a higher-level cache memory in a processor-based system including Figure 1 and Figure 3 in a processor-based system. In response to an eviction request for a lower-level cache line in the lower-level cache memory, process 400 determines at block 402 whether the lower-level cache line is speculative. As discussed in conjunction with Figure 1As described, a run heuristic is used to classify whether a lower-level cache line is useful or opportunistic. Based on the heuristic, at block 404, process 400 sets an opportunistic indicator associated with the lower-level cache line. Alternatively, for blocks 402 and 404, the lower-level cache line may already have its opportunistic indicator 316 pre-set such that it is not necessary to run the heuristic. This can occur if the lower-level cache line was previously evicted to a higher-level cache memory, which would result in the opportunistic indicator being saved with the cache line when the opportunistic indicator is stored in the higher-level cache. More details of this scenario are discussed in conjunction with Figure 6 At block 406, process 400 communicates the lower-level cache line and the opportunistic indicator associated with the lower-level cache line indicating whether the lower-level cache line is opportunistic to a higher-level cache memory. In the case of a distributed cache allocation circuit, cache allocation circuit 113(0) performs blocks 402 - 406.

[0045] At block 408, process 400 determines whether a higher-level cache line in a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line. At block 410, when block 408 has determined that the higher-level cache line has lower or equal importance compared to the lower-level cache line, process 400 addresses a logical path. In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line, process 400 replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line at block 414 and associates the opportunistic indicator of the lower-level cache line with the replaced higher-level cache line in the higher-level cache memory at block 414.

[0046] Figure 5 is a flowchart expansion of block 408 that determines whether a lower-level cache line has lower or equal importance compared to a higher-level cache line in an exemplary process in Figure 4 At block 502, process 400 retrieves a plurality of higher-level cache lines from a higher-level cache (such as shared system cache memory 108) based on the memory address of the lower-level cache line. For example, hash circuit 304 hashes the memory address to allow cache allocation circuit 113(1) to access N higher-level cache lines from the N-way cache 306 in the higher-level cache. At block 504, process 400 determines whether there is at least one invalid cache line from the set of N higher-level cache lines. If there is at least one invalid cache line, then process 400 replaces one of the invalid cache lines with the lower-level cache line including the opportunistic indicator associated with the lower-level cache line in the higher-level cache at block 506.

[0047] If there is no invalid cache line in the set of N higher-level cache lines, process 400 proceeds to block 508 and determines whether there is at least one snooping cache line from the set of N higher-level cache lines. If there is at least one snooping cache line in the set of N higher-level cache lines, process 400 proceeds to block 510 and replaces one of the snooping higher-level cache lines with a lower-level cache line that includes a snooping indicator associated with the lower-level cache line in the higher-level cache.

[0048] If there is not at least one snooping cache line in the set of N higher-level cache lines, process 400 proceeds to block 512 and checks the snooping indicator of the lower-level cache line (also referred to as the evicted lower-level cache line), because at this point in process 400, there are no invalid or snooping cache lines in the set of N higher-level cache lines, and thus all cache lines in the set of N higher-level cache lines are useful. If the snooping indicator indicates that the lower-level cache line is also useful, process 400 proceeds to block 514 and selects the least recently used higher-level useful cache line to replace with the lower-level cache line that includes the snooping indicator of the lower-level cache line.

[0049] If the snooping indicator indicates that the lower-level cache line is snooping, process 400 proceeds to optional block 515 to determine whether the higher-level cache memory is the highest level in the cache memory hierarchy. If not, process 400 repeats the blocks starting from block 500 for the next higher-level cache memory in the cache memory hierarchy. If the higher-level cache memory is the highest level or optional block 515 does not exist, process 400 proceeds to block 516 and does not allocate the lower-level cache line to the higher-level cache memory. Process 400 proceeds to block 518 and reads the associated dirty bit 314 of the lower-level cache line. If the lower-level cache line is not dirty, which means it has not been written while in the lower-level cache, process 400 ends. If the lower-level cache line is dirty, process 400 proceeds to block 520 to write the lower-level cache line to the system memory 118. The cache allocation circuit 113(1) performs blocks 504 - 520.

[0050] If there are more than one snooping cache lines in a set of N higher-level cache lines (which can occur at blocks 508 and 510), or more than one useful cache lines in a set of N higher-level cache lines (which can occur at blocks 512 and 514), then process 400 selects one of the higher-level cache lines in the higher-level cache lines to sacrifice using a modified least recently used or modified least recently unused technique. Tie-breaking among the sets of N higher-level cache lines to be sacrificed will be further discussed in conjunction with FIGS. 7 and 8.

[0051] Figure 6 FIG. 6 is a flowchart of an exemplary process 600 for retrieving a snooping indicator for a cache line previously determined to be snooping. Doing so allows the cache allocation circuit 113(0) to store the snooping indicator together with the cache line retrieved from the higher-level cache memory, and use the stored snooping indicator in the lower-level cache memory to determine whether the retrieved cache line is useful or snooping. At block 602, in response to a memory read request, process 600, a CPU (such as CPU0104(0)), requests a cache line from a higher-level cache memory (such as the shared system cache memory 108) based on the address. At block 604, process 600 searches the higher-level cache memory to determine whether the cache line is stored with the same address. At block 606, process 600 determines whether the address hits the higher-level cache memory. If there is no hit in the higher-level cache memory, process 600 proceeds to block 608. If the higher-level cache memory is the highest-level cache memory, process 600 proceeds to block 610, where the CPU retrieves the cache line from the system memory (such as the system memory 118). Otherwise, the address is passed to the next higher-level cache memory, and process 600 proceeds to block 604 to process the next higher-level cache memory.

[0052] Returning to block 606, if there is a hit in the higher-level cache memory for the address, process 600 proceeds to block 612, where the higher-level cache memory conveys the hit cache line and the snooping indicator associated with the hit cache line (if a snooping indicator has been set) to the CPU. At block 614, the CPU stores the snooping indicator together with the hit cache line in its local cache (such as the private L2 cache memory 106).

[0053] Figure 7A FIG. Figure 3 illustrates when the cache allocation circuit 113(1) of FIG. uses a modified least recently used technique to select among higher-level cache lines in the same cache way in the higher-level cache memory for evictionFigure 2 a hierarchical structure diagram of another example of the relative importance grading structure in Figure 8A and will be discussed in conjunction with Figure 8A Including two examples of four (4) higher-level cache lines returned in a 4-way higher-level cache memory to show the selection among higher-level cache lines to sacrifice when allocating a sacrificed cache line from a lower-level cache using a modified least recently used method. In these examples, the N-way cache 306 of the shared system cache memory 108 is a 4-way cache.

[0054] Returning to Figure 7A , below the useful cache line 200(0), there are three exemplary usefulness levels in hierarchical order; useful and most recently used 702(0), useful and between least recently used and most recently used 702(1), and useful and least recently used 702(2). Below the opportunistic cache line 200(1), there are three opportunistic levels in hierarchical order; opportunistic and most recently used 704(0), opportunistic and between least recently used and most recently used 704(1), and opportunistic and least recently used 704(2). This hierarchical structure is used when the cache allocation circuit 113(1) selects among higher-level cache lines in the same way in the higher-level cache memory to replace with a more important lower-level cache line. The actual number of levels of usefulness and opportunism depends on the number of ways in the cache. For example, an M-way cache will have M levels of usefulness and M levels of opportunism because each cache line in the cache way will track in order using the modified least recently used technique.

[0055] In example 800, for the memory address that also corresponds to the sacrificed lower-level cache line, four cache lines 802(1), 802(2), 802(3), and 802(4) and the LRU 804 are returned. The cache allocation circuit 113(1) selects among the cache lines 802(1), 802(2), 803(3), and 802(4) to sacrifice in order to replace with the sacrificed lower-level cache line. The LRU 804 maintains the order of the most recently used cache lines 802(1), 802(2), 802(3), and 802(4). As Figure 8A shown, the cache line 802(4) is the most recently used, followed by the cache line 802(2), followed by the cache line 802(3), followed by the cache line 802(1). The decoding of the cache lines 802(1), 802(2), 802(3), and 802(4) follows Figure 3Format 310B in. If the sacrificed lower-level cache line is opportunistic or useful, one of the higher-level cache lines 802(1), 802(2), or 802(3) will be selected to be replaced by the cache allocation circuit 113(1) because the cache lines 802(1), 802(2), and 802(3) are also opportunistic and less important compared to the sacrificed lower-level cache line. To break the tie, the cache allocation circuit 113(1) reads the LRU 804 and determines that the cache line 802(1) is the least recently used opportunistic cache line, and thus sacrifices the higher-level cache line 802(1) and replaces the higher-level cache line with the sacrificed lower-level cache line. In example 800, the cache allocation circuit 113(1) follows the path of blocks 502, 504, 508, and 510 of process 400 in Figure 5 . The modified least recently used technique supplements the conventional least recently used technique to break the tie by restricting the selection of cache lines in the same cache way to cache lines that have equal or lower importance compared to the lower-level cache line being sought for replacement.

[0056] In example 805, four higher-level cache lines 806(1), 806(2), 806(3), and 806(4) have been returned for the memory address corresponding to the sacrificed lower-level cache line. The higher-level cache lines 806(1), 806(2), 806(3), and 806(4) set their opportunistic indicators to no, such that they are all useful. If the sacrificed lower-level cache line is opportunistic, the lower-level cache line will not replace any of the cache lines 806(1), 806(2), 806(3), and 806(4) because the sacrificed cache line has lower or equal importance compared to the useful higher-level cache lines 806(1), 806(2), 806(3), and 806(4). In this case, the cache allocation circuit 113(1) will follow process 400 at Figure 5 . If the sacrificed lower-level cache line is useful, the cache allocation circuit 113(1) selects between the useful higher-level cache lines 806(1), 806(2), 806(3), and 806(4) by reading the LRU 808 and determining that the cache line 806(4) is the least recently used useful higher-level cache line, and thus, sacrifices the higher-level cache line 806(4) as the sacrificed lower-level cache line, which follows process 400 at Figure 5 .

[0057] Figure 7B Illustrates when Figure 3The cache allocation circuit uses a modified least recently used technique to select among higher-level cache lines in the same way in a higher-level cache memory, such as the shared system cache memory 108, for eviction when Figure 2 Hierarchical structure diagram of another example of the relative importance hierarchical structure in. Will be combined with Figure 8B discussed Figure 7B , Figure 8B Includes two examples of four (4) higher-level cache lines returned in a 4-way higher-level cache to show the selection among higher-level cache lines to sacrifice when using the modified least recently used method to allocate sacrificed cache lines from a lower-level cache. In these examples, the N-way cache 306 of the shared system cache memory 108 is a 4-way cache.

[0058] Return to Figure 7B ,below the useful cache line 200(0), there are two usefulness levels in hierarchical order: useful and high priority 706(0), and useful and low priority 706(1). Below the opportunistic cache line 200(1), there are two opportunistic levels in hierarchical order: opportunistic and high priority 708(0), and opportunistic and low priority 708(1). This hierarchical structure is used when the cache allocation circuit 113(1) selects among higher-level cache lines in the same way in a higher-level cache memory to sacrifice for a more important lower-level cache line.

[0059] In example 810, for the memory address that also corresponds to the sacrificed lower-level cache line, four cache lines 812(1), 812(2), 812(3), and 812(4) are returned. The cache allocation circuit 113(1) selects among the cache lines 812(1), 812(2), 812(3), and 812(4) to sacrifice in order to replace the sacrificed lower-level cache line. As Figure 8B shown, the opportunistic indicators of all cache lines are set to yes, the priority indicators of cache lines 812(1) and 812(4) are set to low, and the priority indicators of cache lines 812(2) and 812(3) are set to high. Using the modified least recently used technique, cache lines 812(1) and 812(4) have been written for a longer time compared to cache lines 812(2) and 812(3) in the past. In the modified, least recently used technique, whenever a cache line is written, its associated priority indicator is set to high. When the last cache line in the same cache way is set to high, the priority indicators of the remaining cache lines are set to low. The decoding of cache lines 812(1), 812(2), 812(3), and 812(4) follows Figure 3Format 310A in. If the sacrificed lower - level cache line is opportunistic or useful, one of the higher - level cache lines 812(1), 812(2), 812(3), or 812(4) will be selected to be replaced by the cache allocation circuit 113(1) because the cache lines 812(1), 812(2), 812(3), or 812(4) are all opportunistic and less important compared to the sacrificed lower - level cache line. To break the tie, the cache allocation circuit 113(1) will read the priority indicators of the cache lines and narrow the selection to cache lines 812(1) and 812(4) because they are both low - priority. The cache allocation circuit 113(1) randomly selects between cache lines 812(1) and 812(4) to sacrifice. In example 810, the cache allocation circuit 113(1) follows Figure 5 the path of blocks 502, 504, 508, and 510 of process 400 in.

[0060] In example 814, for the memory address corresponding to the sacrificed lower - level cache line, four higher - level cache lines 816(1), 816(2), 816(3), and 816(4) have been returned. The higher - level cache lines 816(1), 816(2), 816(3), and 816(4) set their opportunistic indicators to no, making them all useful. If the sacrificed lower - level cache line is opportunistic, the lower - level cache line will not replace any of the cache lines 816(1), 816(2), 816(3), and 816(4) because the sacrificed cache line has lower or equal importance compared to the useful higher - level cache lines 816(1), 816(2), 816(3), and 816(4). In this case, the cache allocation circuit 113(1) will follow Figure 5 process 400 at block 516 in. If the sacrificed lower - level cache line is useful, the cache allocation circuit 113(1) selects between the useful higher - level cache lines 816(1), 816(2), 816(3), and 816(4) by reading their respective priority indicators and determining that cache line 816(1) is the only low - priority useful higher - level cache line, and thus, sacrifices cache line 816(1) as the sacrificed lower - level cache line. The cache allocation circuit 113(1) follows Figure 5 the path of blocks 502, 504, 508, 512, and 514 of process 400 in.

[0061] The modified least recently used technique supplements the regular least recently used technique to break ties between opportunistic cache lines or useful cache lines by using priority indicator settings. Associated with Figure 7AAnd Figure 8A Unlike the modified least recently used technique described, the modified least non - recently used technique narrows the selection of cache lines in the same cache way and may have to randomly select between the narrowed selections.

[0062] Figure 9 Illustrations show before and after using Figure 1 and Figure 3 the cache allocation circuit, Figure 1 and Figure 3 two graphs of the utilization of a higher - level cache memory. Graph 900 shows the system cache memory 108 configured as 16 MB of Figure 1 Graph 902 shows the system cache memory 108 configured as 32 MB of Figure 1 Graphs 900 and 902 illustrate before and after using the cache allocation circuit 113. The y - axis shows the percentage of tests or traces. These tests include various industry - standard benchmarks, including SPEC CPU20017, GeekBench, etc. The x - axis shows the percentage of shared system cache lines in use (i.e., not invalid). For example, the 15% point on the x - axis means that only 15% of the system cache memory is actually allocated and in use. Referring to graph 900 at the 80% horizontal line representing the completion of 80% of the tests, less than 10% of the system cache memory was in use before using the cache allocation circuit 113. After using the cache allocation circuit 113, 50% of the system cache memory was in use. As shown in graphs 900 and 902, in both configurations, the utilization of the shared system cache memory 108 has a higher utilization at the same level of cache test percentage.

[0063] An electronic device including a processor - based system can be provided in or integrated into any processor - based device that includes a plurality of central processing units and a memory system that includes a cache memory system as in Figure 1 and a cache memory system as in Figure 1 and Figure 3The cache allocation circuit shown, the cache memory system including a hierarchy of local and shared cache memories and a system memory, the cache allocation circuit for determining, in response to an eviction request for a lower-level cache line, whether the lower-level cache line is opportunistic and, if a higher-level cache line has lower or equal significance compared to the lower-level cache line and in accordance with any aspect disclosed herein, replacing the higher-level cache line with the lower-level cache line. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smart phones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0064] In this regard, Figure 10 An example of a processor-based system 100 is illustrated, the processor-based system may include Figure 1 and Figure 3 a cache allocation circuit that, in response to an eviction request for a lower-level cache line, determines whether the lower-level cache line is opportunistic and, if a higher-level cache line has lower or equal significance compared to the lower-level cache line and in accordance with any exemplary aspect disclosed herein, replaces the higher-level cache line in the higher-level cache memory. In this example, the processor-based system 1000 may be formed as an integrated circuit (IC) 1004 and includes a cache allocation circuit 1002, such as Figure 1 and Figure 3The described cache allocation circuit 113 and is deployed as a system-on-chip (SoC) 1006. The processor-based system 1000 includes a central processing unit (CPU) 1008, the central processing unit (CPU) includes one or more processors 1010, the one or more processors may also be referred to as CPU cores or processor cores. The CPU 1008 may have a cache memory 1012 coupled to the CPU 1008 for fast access to temporarily stored data. The CPU 1008 is coupled to a system bus 1014 and may couple the master and slave devices included in the processor-based system 1000 to each other. As is well known, the CPU 1008 communicates with these other devices by exchanging address, control, and data information on the system bus 1014. For example, the CPU 1008 may convey a bus transaction request to a memory controller 1016, which is an example of a slave device. Although not illustrated in Figure 10 , multiple system buses 1014 may be provided, where each system bus 1014 constitutes a different architecture.

[0065] Other master and slave devices may be connected to the system bus 1014. As Figure 10 illustrated, by way of example, these devices may include a memory system 1020 (which includes a memory controller 1016 and a memory array 1018), one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028. Each of the memory system 1020, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028 may be provided in the same or different electronic devices. The input device 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 1026 may be any device configured to allow data exchange to and from a network 1030. The network 1030 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth TM networks, and the Internet. The network interface device 1026 may be configured to support any type of communication protocol desired.

[0066] The CPU 1008 may also be configured to access the display controller 1028 via the system bus 1014 to control the information transmitted to one or more displays 1032. The display controller 1028 transmits the information to be displayed to the displays 1032 via one or more video processors 1034, and the one or more video processors process the information to be displayed into a format suitable for the displays 1032. For example, the display controller 1028 and the video processors 1034 may be included as ICs in the same or different electronic devices, as well as in the same or different electronic devices containing the CPU 1008. The displays 1032 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light emitting diode (LED) display, etc.

[0067] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or another computer-readable medium, and any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate such interchangeability, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been described generally above. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. A person skilled in the art may implement the described functionality in different ways for each particular application, but such specific implementation decisions should not be construed as causing a departure from the scope of the present disclosure.

[0068] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or executed by a processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0069] Aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In an alternative, the storage medium may be integral with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0070] It is also noted that the operational steps described in any of the exemplary aspects herein are described for purposes of providing examples and discussion. The described operations may be performed in numerous different sequences other than the illustrated sequences. Further, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more of the operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different technologies and processes may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0071] The foregoing description of the disclosure has been provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0072] Specific implementation examples are described in the following numbered clauses:

[0073] 1. A processor-based system for allocating cache lines to a higher-level cache memory, the processor-based system comprising:

[0074] A lower-level cache memory configured to store data;

[0075] The processor-based system is configured to respond to an eviction request for a lower-level cache line in the lower-level cache memory by:

[0076] Determining whether the lower-level cache line is opportunistic;

[0077] Setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;

[0078] Communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;

[0079] Determining whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line; and

[0080] In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line:

[0081] Replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0082] Associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0083] 2. The processor-based system according to clause 1, wherein the processor-based system is configured to determine whether a higher-level cache line among the plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line by being configured to perform the following operations:

[0084] Determining whether the higher-level cache line in the higher-level cache memory is invalid; and

[0085] In response to determining that the higher-level cache line in the higher-level cache memory is invalid:

[0086] Replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0087] Associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0088] 3. The processor-based system according to clause 2, the processor-based system is further configured by being configured to perform the following operations in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid:

[0089] Determine whether the higher-level cache line in the higher-level cache memory is speculative based on a second speculative indicator of the higher-level cache line; and

[0090] In response to determining that the second speculative indicator of the higher-level cache line is speculative:

[0091] Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0092] Associate the speculative indicator of the lower-level cache line in the higher-level cache memory.

[0093] 4. The processor-based system according to clause 3, the processor-based system is further configured in response to determining whether the higher-level cache line in the higher-level cache memory is not speculative:

[0094] Determine whether the lower-level cache line is dirty based on a dirty indicator of the lower-level cache line; and

[0095] In response to determining that the dirty indicator of the lower-level cache line is dirty:

[0096] Write the lower-level cache line to the system memory.

[0097] 5. The processor-based system according to clauses 1 to 4, wherein the speculative indicator indicates that the lower-level cache line is speculative.

[0098] 6. The processor-based system according to clauses 1 to 5, the processor-based system is configured to determine whether the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line by being configured to perform the following operations:

[0099] Determine whether a first higher-level cache line has lower or equal importance compared to the lower-level cache line;

[0100] Determine whether a second higher-level cache line has lower or equal importance compared to the lower-level cache line; and

[0101] In response to determining that the first higher-level cache line has lower or equal importance compared to the lower-level cache line and that the second higher-level cache line has lower or equal importance compared to the lower-level cache line:

[0102] Determine whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line; and

[0103] In response to determining that the first higher-level cache line has lower or equal importance compared to the second higher-level cache line:

[0104] Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line, and

[0105] Associate the snoop indicator of the lower-level cache line in the higher-level cache memory.

[0106] 7. The processor-based system according to clauses 1 to 6, wherein the processor-based system is configured to determine whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line by being configured to perform the following operations:

[0107] Determine whether the first higher-level cache line is invalid;

[0108] Determine whether the second higher-level cache line is not invalid; and

[0109] In response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

[0110] Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0111] Associate the snoop indicator of the lower-level cache line in the higher-level cache memory.

[0112] 8. The processor-based system according to clause 7, wherein the processor-based system is further configured by being configured to perform the following operations in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid:

[0113] Determine a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

[0114] In response to determining that the first priority indicator of the first higher-level cache line has been least recently used compared to the second priority indicator of the second higher-level cache line:

[0115] Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0116] Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0117] 9. The processor-based system according to clause 7, the processor-based system being further configured by being configured to perform the following in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid:

[0118] Determine an LRU indicator that tracks the order of multiple least recently used cache lines, the multiple least recently used cache lines including the first higher-level cache line and the second higher-level cache line; and

[0119] In response to determining that the LRU indicator indicates that the first higher-level cache line has been least recently used compared to the second higher-level cache line:

[0120] Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0121] Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0122] 10. The processor-based system according to clauses 1 to 9, the processor-based system being configured to associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory by being configured to perform the following:

[0123] Store the opportunistic indicator of the lower-level cache line in the higher-level cache line.

[0124] 11. The processor-based system according to clauses 1 to 10, the processor-based system being integrated into an integrated circuit (IC).

[0125] 12. A processor-based system according to clauses 1 to 11, the processor-based system being integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a Global Positioning System (GPS) device; a mobile phone; a cellular phone; a smart phone; a Session Initiation Protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a Personal Digital Assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a Digital Video Disc (DVD) player; a portable digital video player; a vehicle; a vehicle component; an avionics system; a drone; and a multi-rotor aircraft.

[0126] 13. A method for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory, the method comprising:

[0127] Determining whether the lower-level cache line is opportunistic;

[0128] Setting an opportunistic indicator to indicate whether the lower-level cache line is opportunistic;

[0129] Communicating the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory;

[0130] Determining whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line; and

[0131] In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line:

[0132] Replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0133] Associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0134] 14. The method according to clause 13, wherein determining whether a higher-level cache line among the plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line comprises:

[0135] Determine whether the higher-level cache line in the higher-level cache memory is invalid; and

[0136] In response to determining that the higher-level cache line in the higher-level cache memory is invalid:

[0137] Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0138] Associate the snooping indicator of the lower-level cache line in the higher-level cache memory.

[0139] 15. The method according to clause 14, wherein in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid, the method further includes:

[0140] Determine whether the higher-level cache line in the higher-level cache memory is snooping based on a second snooping indicator of the higher-level cache line; and

[0141] In response to determining that the second snooping indicator of the higher-level cache line is snooping:

[0142] Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0143] Associate the snooping indicator of the lower-level cache line in the higher-level cache memory.

[0144] 16. The method according to clause 15, wherein in response to determining whether the higher-level cache line in the higher-level cache memory is not snooping, the method includes:

[0145] Determine whether the lower-level cache line is dirty based on a dirty indicator of the lower-level cache line; and

[0146] In response to determining that the dirty indicator of the lower-level cache line is dirty:

[0147] Write the lower-level cache line to the system memory.

[0148] 17. The method according to clauses 13 to 16, wherein the snooping indicator indicates that the lower-level cache line is snooping.

[0149] 18. The method according to clauses 13 to 17, wherein determining whether the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line further includes:

[0150] Determining whether a first higher-level cache line has lower or equal importance compared to the lower-level cache line;

[0151] Determining whether a second higher-level cache line has lower or equal importance compared to the lower-level cache line; and

[0152] In response to determining that the first higher-level cache line has lower or equal importance compared to the lower-level cache line and the second higher-level cache line has lower or equal importance compared to the lower-level cache line:

[0153] Determining whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line; and

[0154] In response to determining that the first higher-level cache line has lower or equal importance compared to the second higher-level cache line:

[0155] Replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0156] Associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0157] 19. The method according to clauses 13 to 18, wherein determining whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line further includes:

[0158] Determining whether the first higher-level cache line is invalid;

[0159] Determining whether the second higher-level cache line is invalid; and

[0160] In response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid:

[0161] Replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0162] Associating the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

[0163] 20. The method according to clause 19, wherein in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, the method further comprises:

[0164] determining a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; and

[0165] in response to determining that the first priority indicator of the first higher-level cache line is less recently used compared to the second priority indicator of the second higher-level cache line:

[0166] replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0167] associating the snoop indicator of the lower-level cache line in the higher-level cache memory.

[0168] 21. The method according to clause 19, wherein in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, the method comprises:

[0169] determining an LRU indicator that tracks the order of a plurality of least recently used cache lines, the plurality of least recently used cache lines including the first higher-level cache line and the second higher-level cache line; and

[0170] in response to determining that the LRU indicator indicates that the first higher-level cache line is less recently used compared to the second higher-level cache line:

[0171] replacing the first higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0172] associating the snoop indicator of the lower-level cache line in the higher-level cache memory.

[0173] 22. A processor-based system for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory, the processor-based system comprising:

[0174] means for determining whether the lower-level cache line is snoopable;

[0175] means for setting a snoop indicator to indicate whether the lower-level cache line is snoopable;

[0176] A component for communicating the lower-level cache line and the snoop indicator indicating that the lower-level cache line is snooping to the higher-level cache memory;

[0177] A component for determining whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the snoop indicator of the lower-level cache line; and

[0178] In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line:

[0179] A component for replacing the higher-level cache line in the higher-level cache memory with the lower-level cache line; and

[0180] A component for associating the snoop indicator of the lower-level cache line in the higher-level cache memory.

Claims

1. A processor-based system for allocating cache lines to a higher-level cache memory, the processor-based system comprising: A lower-level cache memory configured to store data; The processor-based system is configured to, in response to an eviction request for a lower-level cache line in the lower-level cache memory: Determine whether the lower-level cache line is opportunistic; Set an opportunistic indicator to indicate whether the lower-level cache line is opportunistic; Communicate the lower-level cache line and the opportunistic indicator indicating that the lower-level cache line is opportunistic to the higher-level cache memory; Determine whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the opportunistic indicator of the lower-level cache line; And In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

2. The processor-based system according to claim 1, wherein the processor-based system is configured to determine whether a higher-level cache line among the plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line by being configured to perform the following operations: Determine whether the higher-level cache line in the higher-level cache memory is invalid; And In response to determining that the higher-level cache line in the higher-level cache memory is invalid: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

3. The processor-based system according to claim 2, wherein the processor-based system is further configured by being configured to perform the following operations in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid: Determine whether the higher-level cache line in the higher-level cache memory is speculative based on a second speculative indicator of the higher-level cache line; And In response to determining that the second opportunistic indicator of the higher-level cache line is opportunistic: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

4. The processor-based system according to claim 3, wherein the processor-based system is further configured in response to determining whether the higher-level cache line in the higher-level cache memory is not opportunistic to: Determine whether the lower-level cache line is dirty based on a dirty indicator of the lower-level cache line; and In response to determining that the dirty indicator of the lower-level cache line is dirty: Write the lower - level cache line to system memory.

5. The processor - based system according to claim 1, wherein the snoop indicator indicates that the lower - level cache line is snooping.

6. The processor - based system according to claim 1, the processor - based system is configured to determine whether the higher - level cache line in the higher - level cache memory has lower or equal significance compared to the lower - level cache line by being configured to perform the following operations: Determine whether a first higher - level cache line has lower or equal significance compared to the lower - level cache line; Determine whether a second higher - level cache line has lower or equal significance compared to the lower - level cache line; And In response to determining that the first higher - level cache line has lower or equal significance compared to the lower - level cache line and the second higher - level cache line has lower or equal significance compared to the lower - level cache line: Determine whether the first higher - level cache line has lower or equal significance compared to the second higher - level cache line; And In response to determining that the first higher - level cache line has lower or equal significance compared to the second higher - level cache line: Replace the first higher - level cache line in the higher - level cache memory with the lower - level cache line, and Associate the snoop indicator of the lower - level cache line in the higher - level cache memory.

7. The processor - based system according to claim 6, the processor - based system is configured to determine whether the first higher - level cache line has lower or equal significance compared to the second higher - level cache line by being configured to perform the following operations: Determine whether the first higher - level cache line is invalid; Determine whether the second higher - level cache line is not invalid; And In response to determining that the first higher - level cache line is invalid and the second higher - level cache line is not invalid: Replace the first higher - level cache line in the higher - level cache memory with the lower - level cache line; And Associate the snoop indicator of the lower - level cache line in the higher - level cache memory.

8. The processor - based system according to claim 7, the processor - based system is further configured by being configured to perform the following operations in response to determining that the first higher - level cache line is not invalid and the second higher - level cache line is not invalid: Determine a first priority indicator for the first higher-level cache line and a second priority indicator for the second higher-level cache line; And In response to determining that the first priority indicator of the first higher - level cache line has been less recently used compared to the second priority indicator of the second higher - level cache line: Replace the first higher - level cache line in the higher - level cache memory with the lower - level cache line; And Associate the snoop indicator of the lower - level cache line in the higher - level cache memory.

9. The processor-based system according to claim 7, the processor-based system is further configured by being configured to perform the following operations in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid: An LRU indicator that determines an order for tracking a plurality of least recently used cache lines, the plurality of least recently used cache lines including the first higher-level cache line and the second higher-level cache line; And In response to determining that the LRU indicator indicates that the first higher-level cache line has been used less recently than the second higher-level cache line: Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the snoop indicator of the lower-level cache line in the higher-level cache memory.

10. The processor-based system according to claim 1, the processor-based system is configured to associate the snoop indicator of the lower-level cache line in the higher-level cache memory by being configured to perform the following operations: Store the snoop indicator of the lower-level cache line together with the higher-level cache line.

11. The processor-based system according to claim 1, the processor-based system is integrated into an integrated circuit (IC).

12. The processor-based system according to claim 1, the processor-based system is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed-position data unit; a mobile-position data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a car; a vehicle component; an avionics system; a drone; and a multi-rotor aircraft.

13. A method for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory, the method comprising: Determine whether the lower-level cache line is snoop; Set a snoop indicator to indicate whether the lower-level cache line is snoop; Communicate the lower-level cache line and the snoop indicator indicating that the lower-level cache line is snoop to the higher-level cache memory; Determine whether a higher-level cache line among a plurality of higher-level cache lines in the higher-level cache memory has lower or equal importance compared to the lower-level cache line based on the snoop indicator of the lower-level cache line; And In response to determining that the higher-level cache line has lower or equal importance compared to the lower-level cache line: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

14. The method according to claim 13, wherein determining whether the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line includes: Determining whether the higher-level cache line in the higher-level cache memory is invalid; And In response to determining that the higher-level cache line in the higher-level cache memory is invalid: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

15. The method according to claim 14, wherein in response to determining whether the higher-level cache line in the higher-level cache memory is not invalid, the method further includes: Determining whether the higher-level cache line in the higher-level cache memory is opportunistic based on a second opportunistic indicator of the higher-level cache line; And In response to determining that the second opportunistic indicator of the higher-level cache line is opportunistic: Replace the higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

16. The method according to claim 15, wherein in response to determining whether the higher-level cache line in the higher-level cache memory is not opportunistic, the method includes: Determining whether the lower-level cache line is dirty based on a dirty indicator of the lower-level cache line; And In response to determining that the dirty indicator of the lower-level cache line is dirty: Write the lower-level cache line to the system memory.

17. The method according to claim 13, wherein the opportunistic indicator indicates that the lower-level cache line is opportunistic.

18. The method according to claim 13, wherein determining whether the higher-level cache line in the higher-level cache memory has lower or equal importance compared to the lower-level cache line further includes: Determining whether a first higher-level cache line has lower or equal importance compared to the lower-level cache line; Determining whether a second higher-level cache line has lower or equal importance compared to the lower-level cache line; And In response to determining that the first higher-level cache line has lower or equal importance compared to the lower-level cache line and the second higher-level cache line has lower or equal importance compared to the lower-level cache line: Determine whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line; And In response to determining that the first higher-level cache line has lower or equal importance compared to the second higher-level cache line: Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

19. The method according to claim 18, wherein determining whether the first higher-level cache line has lower or equal importance compared to the second higher-level cache line further includes: Determine whether the first higher-level cache line is invalid; Determine whether the second higher-level cache line is invalid; And In response to determining that the first higher-level cache line is invalid and the second higher-level cache line is not invalid: Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

20. The method according to claim 19, wherein in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, the method further includes: Determine a first priority indicator of the first higher-level cache line and a second priority indicator of the second higher-level cache line; And In response to determining that the first priority indicator of the first higher-level cache line has been least recently used compared to the second priority indicator of the second higher-level cache line: Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

21. The method according to claim 19, wherein in response to determining that the first higher-level cache line is not invalid and the second higher-level cache line is not invalid, the method includes: Determine an LRU indicator that tracks the order of multiple least recently used cache lines, the multiple least recently used cache lines including the first higher-level cache line and the second higher-level cache line; And In response to determining that the LRU indicator indicates that the first higher-level cache line has been least recently used compared to the second higher-level cache line: Replace the first higher-level cache line in the higher-level cache memory with the lower-level cache line; And Associate the opportunistic indicator of the lower-level cache line in the higher-level cache memory.

22. A processor-based system for allocating a cache line to a higher-level cache memory in response to an eviction request for a lower-level cache line in a lower-level cache memory, the processor-based system comprising: A component for determining whether the lower - level cache line is opportunistic; A component for setting an opportunistic indicator to indicate whether the lower - level cache line is opportunistic; A component for communicating the lower - level cache line and the opportunistic indicator indicating that the lower - level cache line is opportunistic to the higher - level cache memory; A component for determining whether a higher - level cache line among a plurality of higher - level cache lines in the higher - level cache memory has lower or equal importance compared to the lower - level cache line based on the opportunistic indicator of the lower - level cache line; And In response to determining that the higher - level cache line has lower or equal importance compared to the lower - level cache line: A component for replacing the higher - level cache line in the higher - level cache memory with the lower - level cache line; And A component for associating the opportunistic indicator of the lower - level cache line in the higher - level cache memory.

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