Device packaging method
Patent Information
- Application Number
- CN202380087024.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-06
- Publication Date
- 2025-07-22
AI Technical Summary
In the prior art, there is a problem of large alignment errors when bonding connectors and chips, resulting in reduced reliability.
Make an interconnection bridge on the temporary substrate, transfer it to the carrier board, and fit it to the corresponding position of the metal pin to ensure that the position of the interconnection bridge is fixed, so that the chip can be positioned according to the position of the interconnection bridge when attaching the chip. Press to avoid accumulation of pressing errors in sequence.
By independently preparing the interconnection bridge structure, chip bonding errors are reduced and the reliability and packaging accuracy of system-level packaging are improved.
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Figure CN120359613A_ABST
Abstract
Description
Device packaging method Technical Field
[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a device packaging method. Background Art
[0002] Chip interconnect bridge technology can connect two independent devices in a timely manner, reducing the wiring distance between the two chips and achieving high performance at low power consumption. Traditionally, the interconnect bridge and chip bonding is to bond the interconnect bridges one by one independently to the carrier board, and then align the chip and the interconnect bridge. Due to alignment errors, the errors caused by each bonding between the chip and the interconnect bridge will accumulate, affecting the subsequent bonding and alignment process and reducing reliability. Although the solder reflow process can partially compensate for the bonding error, it cannot solve the cumulative effect of the errors caused by the sequential bonding. After multiple bonding cycles, the problem of large alignment errors still exists.
[0003] In summary, in the prior art, when bonding a connector to a chip, there is a problem of large alignment error.
[0004] Summary of the Invention
[0005] The purpose of the present application is to provide a device packaging method to solve the problem of large alignment error when bonding a connector to a chip in the prior art.
[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:
[0007] An embodiment of the present application provides a device packaging method, the method comprising:
[0008] Providing a carrier board, wherein a metal interconnection layer is arranged on the carrier board, and metal pins are arranged in the metal interconnection layer;
[0009] providing a temporary substrate;
[0010] fabricating a temporary bonding layer and an insulating layer based on the temporary substrate;
[0011] An interconnection bridge is fabricated based on the insulating layer; wherein the position of the interconnection bridge corresponds to the position of the metal pin;
[0012] Laminating the temporary substrate to the carrier substrate, wherein the insulating layer is laminated to the metal interconnection layer;
[0013] peeling off the temporary substrate;
[0014] Device patching is performed based on the insulating layer; wherein the devices are bonded to the metal pins and the interconnection bridges respectively.
[0015] Optionally, the step of performing device bonding based on the insulating layer includes:
[0016] Holes are drilled based on the insulating layer and the metal interconnection layer to expose the metal pins.
[0017] Optionally, before the step of performing device bonding based on the insulating layer, the method further includes:
[0018] Solder joints are arranged based on the locations of the interconnect bridges.
[0019] Optionally, after the step of performing device bonding based on the insulating layer, the method further includes:
[0020] Add filling material and seal.
[0021] Optionally, the step of providing a temporary substrate includes:
[0022] Available in glass, ceramic or silicon wafer substrates.
[0023] Optionally, the step of manufacturing a temporary bonding layer and an insulating layer based on the temporary substrate includes:
[0024] A thermal decomposable bonding film or a photodecomposable bonding film and an insulating layer are manufactured based on the temporary substrate.
[0025] Optionally, the step of manufacturing an interconnection bridge based on the insulating layer includes:
[0026] A single-layer or multi-layer metal interconnection bridge is manufactured based on the insulating layer, wherein the line width of the interconnection bridge is 1-50 μm and the line spacing is 1-50 microns.
[0027] Optionally, a first metal interconnection layer and a second metal interconnection layer are arranged on the carrier, and the first metal interconnection layer and the second metal interconnection layer are respectively located on two sides of the carrier, and the step of performing device bonding based on the insulating layer includes:
[0028] bonding the device to the metal pins of the first metal interconnection layer;
[0029] After the step of performing device bonding based on the insulating layer, the method further includes:
[0030] Openings are made in the second metal interconnection layer to expose the metal pins.
[0031] Optionally, the step of manufacturing an interconnection bridge based on the insulating layer includes:
[0032] Interconnection bridges having a density greater than that of metal lines in the metal interconnection layer are fabricated based on the insulation layer.
[0033] Optionally, the step of performing device bonding based on the insulating layer includes:
[0034] Chip dies, devices or sensor patches are made based on the insulating layer.
[0035] Compared with the prior art, this application has the following effects:
[0036] The present application provides a device packaging method, first providing a carrier board, wherein a metal interconnection layer is arranged on the carrier board, and metal pins are provided in the metal interconnection layer, then providing a temporary substrate, and then making a temporary bonding layer and an insulating layer based on the temporary substrate, and then making an interconnection bridge based on the insulating layer; wherein the position of the interconnection bridge corresponds to the position of the metal pin, then the temporary substrate is correspondingly bonded to the carrier board, wherein the insulating layer is bonded to the metal interconnection layer and then the temporary substrate is peeled off, and finally the device is patched based on the insulating layer, wherein the device is bonded to the metal pin and the interconnection bridge respectively. Since the interconnection bridge is made on the temporary substrate in the present application, the independent production of the interconnection bridge is realized, which can improve the production yield. At the same time, after the interconnection bridge is made on the temporary substrate, the interconnection bridge can be completely transferred. When the device is aligned and pressed, since the interconnection bridge is fixed, the patch error is avoided during patching. At the same time, the interconnection bridge can be used to achieve positioning, and the packaging is more accurate.
[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0039] FIG1 is an exemplary flow chart of a device packaging method provided in an embodiment of the present application.
[0040] FIG2 is a schematic structural diagram of a carrier board provided in an embodiment of the present application.
[0041] FIG3 is another structural schematic diagram of a carrier board provided in an embodiment of the present application.
[0042] FIG4 is a schematic cross-sectional view of a carrier provided in an embodiment of the present application.
[0043] FIG5 is a schematic structural diagram of a temporary substrate provided in an embodiment of the present application.
[0044] FIG6 is a cross-sectional schematic diagram corresponding to S108 in FIG1 provided in an embodiment of the present application.
[0045] FIG7 is a cross-sectional schematic diagram corresponding to S110 in FIG1 provided in an embodiment of the present application.
[0046] FIG8 is a cross-sectional schematic diagram corresponding to S112 in FIG1 provided in an embodiment of the present application.
[0047] FIG9 is a cross-sectional schematic diagram corresponding to S114 in FIG1 provided in an embodiment of the present application.
[0048] icon:
[0049] 110 - first metal interconnection layer; 120 - carrier; 130 - second metal interconnection layer; 140 - third metal interconnection layer; 210 - temporary substrate; 220 - temporary bonding layer; 230 - insulating layer; 300 - device. DETAILED DESCRIPTION
[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.
[0051] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.
[0052] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.
[0053] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.
[0054] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.
[0055] As described in the background, prior art devices suffer from large alignment errors during chip placement. The fundamental reason for this is that, in prior art, interconnect bridges are bonded to the chip by individually bonding the bridges to the carrier board before the chip is aligned and connected to the bridges. This can lead to alignment errors for each independent bridge and errors when aligning and connecting the chip to the bridges. This can lead to cumulative errors and ultimately to large alignment errors.
[0056] In light of this, the present application provides a device packaging method that first positions and prepares all interconnect bridge structures on a temporary substrate, and then transfers all interconnect bridges to a carrier board. Because the positions of the interconnect bridges are fixed, the chip can be positioned and pressed according to the positions of the interconnect bridges during pressing, eliminating the cumulative error caused by sequential pressing. Furthermore, by independently preparing the interconnect bridge structures, chip assembly errors can be greatly reduced, improving the reliability of system-level packaging.
[0057] The device packaging method provided in this application is exemplified below:
[0058] As an optional implementation, referring to FIG1 , the method includes:
[0059] S102, providing a carrier board, wherein a metal interconnection layer is arranged on the carrier board, and metal pins are provided in the metal interconnection layer;
[0060] S104, providing a temporary substrate;
[0061] S106, manufacturing a temporary bonding layer and an insulating layer based on the temporary substrate;
[0062] S108, fabricating an interconnection bridge based on the insulating layer; wherein the position of the interconnection bridge corresponds to the position of the metal pin;
[0063] S110, laminating the temporary substrate and the carrier substrate, wherein the insulating layer and the metal interconnection layer are laminated;
[0064] S112, peeling off the temporary substrate;
[0065] S114, performing device bonding based on the insulating layer; wherein the device is bonded to the metal pins and the interconnection bridge respectively.
[0066] The present application does not limit the material or layered structure of the carrier 120. For example, the carrier 120 may be a PCB, BT (Bismaleimide Triazine, a resin substrate), ABF, or other chip packaging substrate. Furthermore, the carrier 120 is provided with metal interconnect layers. The present application does not limit the number of metal interconnect layers. For example, referring to FIG2 , a first metal interconnect layer 110 and a second metal interconnect layer 130 are provided on each side of the carrier 120; or, referring to FIG3 , a third metal interconnect layer 140 is also provided on the carrier 120. For ease of explanation, the present application uses the example of a carrier 120 having a first metal interconnect layer 110 and a second metal interconnect layer 130 provided on each side.
[0067] Referring to FIG. 4 , metal wires and metal pins are arranged in the first metal interconnect layer 110 and the second metal interconnect layer 130 , and the metal pins are connected to the metal wires. In addition, a through-hole is provided on the carrier 120 , and the through-hole is also filled with a conductive material. The conductive material further connects the first metal interconnect layer 110 and the second metal interconnect layer 130 , thereby realizing the connection between the metal interconnect layers.
[0068] It is understood that the metal wires in the first metal interconnect layer 110 and the second metal interconnect layer 130 are actually the circuit traces of the chip. They can form metal traces in the metal interconnect layer, or they can implement circuit layout in the metal interconnect layer, which is not limited here. The metal wires in the metal interconnect layer are low-density metal wires, and the metal pins are used to connect to other structures, and the metal pins can be used as welding points. In addition, this application does not limit the specific material of the metal wires. For example, the metal wires can be made of copper, gold, or silver.
[0069] In one implementation, a glass, ceramic, or silicon wafer substrate can be used as the temporary substrate 210, and a temporary bonding layer 220 and an insulating layer 230 can be sequentially fabricated on the temporary substrate 210. For example, the temporary bonding layer 220 can be fabricated by coating a bonding adhesive, and then the insulating layer 230 can be fabricated on the surface of the temporary bonding layer 220 by a deposition process, as shown in FIG5 . In the schematic diagram of the present application, the thickness ratio between the various hierarchical structures is only for illustration, not for actual ratio. For example, in FIG5 , the thickness of the temporary bonding layer 220 is the same as that of the temporary substrate 210, but in actual applications, the thickness of the temporary bonding layer 220 is much smaller than that of the temporary substrate 210.
[0070] Furthermore, the present application does not limit the materials of the temporary bonding layer 220 and the insulating layer 230. For example, the material of the temporary bonding layer 220 can be a pyrolytic bonding film or a photolytic bonding film, and the material of the insulating layer 230 can be epoxy resin, BT or polyimide.
[0071] After forming the insulating layer 230, an interconnect bridge can be formed on the insulating layer 230. It should be noted that the interconnect bridge is used to connect the subsequently laminated devices 300. For example, when two devices 300 are laminated, the two devices 300 need to be electrically connected via the interconnect bridge to enable signal transmission. Therefore, as shown in Figure 6, a connecting bridge is required at a specific location on the insulating layer 230 to facilitate bonding when laminating the devices 300.
[0072] As shown in Figure 6, in the actual manufacturing process, the corresponding grooves can be first formed in the insulating layer 230, and then the grooves are filled with metal to realize the production of the interconnect bridge. In addition, in one implementation, the density of the interconnect bridge is greater than the density of the metal lines in the metal interconnect layer, thereby independently completing the high-density interconnect bridge and improving the yield rate.
[0073] 7 , the temporary substrate 210 is laminated to the carrier 120 , wherein the insulating layer 230 is laminated to the metal interconnect layer. In actual operation, the temporary substrate 210 is flipped over and then laminated to the carrier 120 .
[0074] Because the interconnect bridges were positioned during fabrication on the temporary substrate 210, they are fixed in place after lamination, and their relative position to the metal interconnect layer is also fixed. Furthermore, since the interconnect bridges are now encased by the insulating layer 230, their position cannot be moved, minimizing significant errors during lamination.
[0075] After the temporary substrate 210 is transferred, as shown in Figure 8, the temporary bonding layer 220 and the temporary substrate 210 can be peeled off. During the peeling process, the peeling method can be determined according to different materials of the temporary bonding layer 220. For example, when the temporary bonding layer 220 is a pyrolysis bonding film, the temporary substrate 210 can be peeled off by heating; when the temporary bonding layer 220 is a photolysis bonding film, the temporary substrate 210 can be peeled off by laser or other methods.
[0076] Afterwards, the device 300 can be mounted based on the insulating layer. The device 300 described in this application includes but is not limited to a chip die, a device 300 or a sensor patch.
[0077] In one implementation, before patching, the method further includes:
[0078] Holes are drilled through the insulating layer 230 and the metal interconnect layer to expose the metal pins.
[0079] Punching, on the one hand, exposes the metal pins, allowing for connection between the device 300 and the metal pins during placement. On the other hand, the punched holes can be used for positioning. Using the fixed bridge as a reference for positioning greatly reduces positioning errors caused by placement and alignment, achieving more precise packaging.
[0080] 9 , when bonding the device 300 , the device 300 may be bonded to the metal pins of the first metal interconnect layer 110 first, forming a structure as shown in FIG9 , in which the solder joints are used to respectively realize bonding between the device 300 and the first metal interconnect layer 110 and between the device 300 and the connecting bridge.
[0081] Furthermore, after bonding is achieved, it is necessary to add filling materials and perform plastic encapsulation, for example, by using epoxy resin, BT or polyimide and other materials, and heat and cure them to achieve plastic encapsulation protection for the entire device 300 .
[0082] Afterwards, the second metal interconnection layer 130 is opened to expose the metal pins in the second metal interconnection layer 130 , so as to realize the installation of the device 300 .
[0083] In summary, the present application provides a device packaging method, first providing a carrier board, wherein a metal interconnection layer is arranged on the carrier board, and metal pins are provided in the metal interconnection layer, then providing a temporary substrate, and then making a temporary bonding layer and an insulating layer based on the temporary substrate, and then making an interconnection bridge based on the insulating layer; wherein the position of the interconnection bridge corresponds to the position of the metal pin, and then the temporary substrate is correspondingly bonded to the carrier board, wherein the insulating layer is bonded to the metal interconnection layer and then the temporary substrate is peeled off, and finally the device is patched based on the insulating layer, wherein the device is bonded to the metal pin and the interconnection bridge respectively. Since the interconnection bridge is made on the temporary substrate in the present application, the independent production of the interconnection bridge is realized, which can improve the production yield. At the same time, after the interconnection bridge is made on the temporary substrate, the interconnection bridge can be completely transferred. When the device is aligned and pressed, since the interconnection bridge is fixed, the patch error is avoided during patching. At the same time, the interconnection bridge can be used to achieve positioning, and the packaging is more accurate.
[0084] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.
[0085] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.
Claims
1. A device packaging method, characterized in that: The method comprises: Providing a carrier board, wherein a metal interconnection layer is arranged on the carrier board, and metal pins are arranged in the metal interconnection layer; providing a temporary substrate; fabricating a temporary bonding layer and an insulating layer based on the temporary substrate; fabricating an interconnection bridge based on the insulating layer; Laminating the temporary substrate to the carrier substrate, wherein the insulating layer is laminated to the metal interconnection layer; peeling off the temporary substrate; Device patching is performed based on the insulating layer; wherein the devices are bonded to the metal pins and the interconnection bridges respectively.
2. The device packaging method according to claim 1, wherein: Before the step of performing device bonding based on the insulating layer, the method further includes: Holes are drilled based on the insulating layer and the metal interconnection layer to expose the metal pins.
3. The device packaging method according to claim 1, wherein: Before the step of performing device bonding based on the insulating layer, the method further includes: Solder joints are arranged based on the locations of the interconnect bridges.
4. The device packaging method according to claim 1, wherein: After the step of performing device bonding based on the insulating layer, the method further includes: Add filling material and seal.
5. The device packaging method according to claim 1, wherein: The step of providing a temporary substrate comprises: Available in glass, ceramic or silicon wafer substrates.
6. The device packaging method according to claim 1, wherein: The steps of manufacturing a temporary bonding layer and an insulating layer based on the temporary substrate include: A thermal decomposable bonding film or a photodecomposable bonding film and an insulating layer are manufactured based on the temporary substrate.
7. The device packaging method according to claim 1, wherein: The steps of making an interconnection bridge based on the insulating layer include: A single-layer or multi-layer metal interconnection bridge is manufactured based on the insulating layer, wherein the line width of the interconnection bridge is 1-50 μm and the line spacing is 1-50 microns.
8. The device packaging method according to claim 1, wherein: A first metal interconnection layer and a second metal interconnection layer are arranged on the carrier board, and the first metal interconnection layer and the second metal interconnection layer are respectively located on two sides of the carrier board. The step of performing device bonding based on the insulating layer includes: bonding the device to the metal pins of the first metal interconnection layer; After the step of performing device bonding based on the insulating layer, the method further includes: Openings are made in the second metal interconnection layer to expose the metal pins.
9. The device packaging method according to claim 1, wherein: The steps of making an interconnection bridge based on the insulating layer include: Interconnection bridges having a density greater than that of metal lines in the metal interconnection layer are fabricated based on the insulation layer.
10. The device packaging method according to claim 1, wherein: The steps of performing device patching based on the insulating layer include: Chip dies, devices or sensor patches are made based on the insulating layer.