Memory distortion neutralization in differential power amplifier circuits

Abstract

Memory distortion neutralization in a differential power amplifier circuit is provided. The differential power amplifier circuit includes a pair of differential amplifiers, each configured to amplify a radio frequency (RF) signal based on a modulated voltage. In embodiments disclosed herein, a neutralization circuit is configured to inject a neutralization current into each of the differential amplifiers, thereby neutralizing a modulated leakage current that causes undesired memory distortion to reduce adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By neutralizing the modulated leakage current, it is possible to prevent the generation of the undesired memory distortion, thereby helping to improve the ACLR of the differential power amplifier circuit.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 478,750, filed on January 6, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The technology of the present disclosure generally relates to neutralizing memory distortion in differential power amplifier circuits. Background Art

[0004] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The popularity of these mobile communication devices is partly driven by the many functions currently enabled on such devices. The enhanced processing capabilities of such devices mean that mobile communication devices have evolved from pure communication tools into complex mobile multimedia centers capable of enhancing the user experience.

[0005] The redefined user experience relies on the higher data rates provided by advanced fifth-generation (5G) and 5G New Radio (5G-NR) systems, where the transmit circuit typically amplifies a radio frequency (RF) signal to a higher power before transmission. In a typical transmit circuit, a transceiver circuit is configured to generate an RF signal, a power management circuit is configured to generate a modulation voltage, a power amplifier circuit is configured to amplify the RF signal based on the modulation voltage, and an antenna circuit is configured to transmit the RF signal at one or more RF frequencies.

[0006] The RF signals transmitted in 5G and 5G-NR systems are subject to strict adjacent channel leakage ratio (ACLR) requirements imposed by standards bodies and / or regulatory authorities. ACLR defines the ratio between the power of an RF signal transmitted on an intended radio channel and the power of an RF signal received in an unintended adjacent radio channel. Given that the ACLR of a broadband RF signal can be largely dominated by re-modulation terms, such as third-order intermodulation products (IMD3), it is desirable to improve the IMD3 performance of the transmit circuit, thereby improving the ACLR. Summary of the Invention

[0007] Embodiments of the present disclosure relate to memory distortion cancellation in a differential power amplifier circuit. The differential power amplifier circuit includes a pair of differential amplifiers, each differential amplifier being configured to amplify a radio frequency (RF) signal based on a modulation voltage. In the embodiments disclosed herein, a cancellation circuit is configured to inject a cancellation current into each of the differential amplifiers to cancel the modulation leakage current that causes undesired memory distortion to reduce the adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By canceling the modulation leakage current, it is possible to prevent the generation of undesired memory distortion, thereby helping to improve the ACLR of the differential power amplifier circuit.

[0008] In one aspect, a differential power amplifier circuit is provided. The differential power amplifier circuit includes an output stage. The output stage includes a collector node. The collector node is coupled to a power management integrated circuit (PMIC) to receive a modulation voltage. The output stage further includes an inter-stage transformer. The inter-stage transformer is configured to receive an RF signal. The output stage further includes a pair of differential amplifiers. Each differential amplifier of the pair of differential amplifiers is coupled to the inter-stage transformer and is configured to amplify the RF signal based on the modulation voltage received via the collector node. The output stage further includes an output transformer. The output transformer is coupled to each differential amplifier of the pair of differential amplifiers. The output transformer includes a center tap that is coupled to the collector node to receive the modulation voltage. The output transformer is configured to output the RF signal amplified by each differential amplifier of the pair of differential amplifiers. The output stage further includes a cancellation circuit. The cancellation circuit is coupled between the inter-stage transformer and the output transformer and is configured to inject an output stage cancellation current into each differential amplifier of the pair of differential amplifiers to suppress the modulation leakage current caused by the modulation voltage in each differential amplifier of the pair of differential amplifiers.

[0009] On the other hand, a wireless device is provided. The wireless device includes a transmitting circuit system. The transmitting circuit system includes a differential power amplifier circuit. The differential power amplifier circuit includes an output stage. The output stage includes a collector node. The collector node is coupled to a power management integrated circuit (PMIC) to receive a modulation voltage. The output stage further includes an inter-stage transformer. The inter-stage transformer is configured to receive an RF signal. The output stage further includes a pair of differential amplifiers. Each differential amplifier of the pair of differential amplifiers is coupled to the inter-stage transformer and is configured to amplify the RF signal based on the modulation voltage received via the collector node. The output stage further includes an output transformer. The output transformer is coupled to each differential amplifier of the pair of differential amplifiers. The output transformer includes a center tap that is coupled to the collector node to receive the modulation voltage. The output transformer is configured to output the RF signal amplified by each differential amplifier of the pair of differential amplifiers. The output stage further includes a neutralization circuit. The neutralization circuit is coupled between the inter-stage transformer and the output transformer and is configured to inject an output stage neutralization current into each differential amplifier of the pair of differential amplifiers, thereby suppressing modulation leakage current caused by the modulation voltage in each differential amplifier of the pair of differential amplifiers.

[0010] On the other hand, a method for neutralizing memory distortion in a differential power amplifier circuit is provided. The method includes receiving a modulation voltage and an RF signal. The method further includes amplifying the RF signal based on the modulation voltage. The method further includes outputting the RF signal amplified by each differential amplifier of the pair of differential amplifiers. The method further includes injecting an output stage neutralization current into each differential amplifier of the pair of differential amplifiers, thereby suppressing modulation leakage current caused by the modulation voltage in each differential amplifier of the pair of differential amplifiers.

[0011] Those skilled in the art will recognize the scope of the present disclosure and understand its additional aspects after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings incorporated in and forming a part of this specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] FIG. 1A is a schematic diagram of a conventional wireless transmitting circuit that may suffer from degraded adjacent channel leakage ratio (ACLR) performance due to memory distortion in a radio frequency (RF) signal caused by a power amplifier circuit;

[0014] FIG. 1B is a schematic diagram showing the internal structure of the output stage of the power amplifier circuit in FIG. 1A;

[0015] Figure 2 is a schematic diagram of an exemplary differential power amplifier circuit, where a neutralization circuit is configured according to an embodiment of the present disclosure to neutralize memory distortion;

[0016] Figure 3A and 3B is a schematic diagram providing an exemplary illustration of a neutralization circuit in a differential power amplifier circuit that Figure 2 provides;

[0017] Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit configured according to another embodiment of the present disclosure to neutralize memory distortion;

[0018] Figure 5 is a schematic diagram of an exemplary differential power amplifier circuit configured according to yet another embodiment of the present disclosure to neutralize memory distortion;

[0019] Figure 6 is a schematic diagram of exemplary user elements of a differential power amplifier circuit in which Figure 2 , 4 and 5 can be set; and

[0020] Figure 7 is a flowchart of an exemplary process for neutralizing memory distortion in a differential power amplifier circuit for Figure 2 , 4 and 5. DETAILED DESCRIPTION

[0021] The embodiments set forth below represent information necessary for those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts that are not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0022] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It should be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending onto" another element, it can be directly on or directly extend onto the other element, or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as being "above" or "extending above" another element, it can be directly above or directly extend above the other element, or there can also be intervening elements. In contrast, when an element is referred to as being "directly above" or "directly extending above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0024] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as shown in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientations depicted in the figures.

[0025] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that unless explicitly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0027] Embodiments of the present disclosure relate to memory distortion cancellation in a differential power amplifier circuit. The differential power amplifier circuit includes a pair of differential amplifiers, each differential amplifier being configured to amplify a radio frequency (RF) signal based on a modulation voltage. In embodiments disclosed herein, a cancellation circuit is configured to inject a cancellation current into each of the differential amplifiers to cancel a modulation leakage current that causes an undesired memory distortion to reduce an adjacent channel leakage ratio (ACLR) of the differential power amplifier circuit. By canceling the modulation leakage current, it is possible to prevent the generation of an undesired memory distortion, thereby helping to improve the ACLR of the differential power amplifier circuit.

[0028] Before discussing the differential power amplifier circuit according to the present disclosure, starting from Figure 2 beginning, a brief discussion of an existing power amplifier circuit is first provided with reference to FIGS. 1A and 1B to help understand how memory distortion can be formed at the collector nodes of the power amplifier circuit.

[0029] FIG. 1A is a schematic diagram of an exemplary existing wireless transmission circuit 10 that may suffer from degraded ACLR performance due to memory distortion caused by a power amplifier circuit 12 in an RF signal 14. The existing wireless transmission circuit 10 includes a transceiver circuit 16 and a power management integrated circuit (PMIC) 18. The transceiver circuit 16 is configured to generate and provide the RF signal 14 to the power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-varying target voltage V ENV (t) according to the time-varying power envelope P TGT (t) of the RF signal 14 and provide the time-varying target voltage V TGT (t) to the PMIC 18. The PMIC 18 is configured to generate a time-varying modulation voltage V TGT (t) based on (also referred to as tracking) the time-varying target voltage V CC (t), such as an envelope tracking (ET) modulation voltage or an average power tracking (APT) modulation voltage. It is noted that since the time-varying modulation voltage V CC (t) is generated based on the time-varying target voltage V TGT (t), and the time-varying target voltage V TGT (t) is generated according to the time-varying power envelope P ENV (t) of the RF signal 14, the time-varying modulation voltage V CC (t) is associated with a time-varying voltage envelope V ENV (t) that tracks the time-varying power envelope P ENV (t) of the RF signal 14. The PMIC 18 is configured to provide the time-varying modulation voltage V TRACE-PMIC via an external conductive trace 20 associated with a corresponding equivalent inductive impedance L CC(t) is provided to the power amplifier circuit 12.

[0030] In this document, the power amplifier circuit 12 is a multi-stage power amplifier that includes an input stage 22 (denoted as "PA IN ") and an output stage 24 (denoted as "PA OUT "). The input stage 22 is configured to receive a time-varying modulation voltage V CC (t) (also denoted as "V PA-I (t)") at the input stage collector node 26, and the output stage 24 is configured to receive a time-varying modulation voltage V CC (t) (also denoted as "V PA-O (t)") at the output stage collector node 28. The output stage collector node 28 is coupled to the input stage collector node 26 via an internal conductive trace 30. Similar to the external conductive trace 20, the internal conductive trace 30 is also associated with a corresponding equivalent inductive impedance. Therefore, the time-varying modulation voltage V CC (t) received at the input stage collector node 26 can be different from the time-varying modulation voltage V CC (t) received at the output stage collector node 28 in terms of phase and / or amplitude.

[0031] The input stage 22 is configured to receive the RF signal 14 via the input stage input node 32 and amplify the RF signal 14 based on the time-varying modulation voltage V CC (t) (also referred to as V PA-I (t)) received at the input stage collector node 26. The output stage 24 is configured to receive the RF signal 14 that has been amplified by the input stage 22 via the output stage input node 34. Therefore, the output stage 24 will further amplify the RF signal 14 based on the time-varying modulation voltage V CC (t) (also referred to as V PA-O (t)) received at the output stage collector node 28.

[0032] The output stage 24 has a corresponding parasitic capacitance between the output stage collector node 28 and the output stage input node 34, as represented by the corresponding equivalent capacitor C BC-O . Additionally, there is an equivalent coupling capacitance C CPL between the input stage 22 and the output stage 24. As discussed in detail in FIG. 1B, the equivalent capacitor C BC-O is a major factor in memory distortion in the RF signal 14.

[0033] FIG. 1B is a schematic diagram showing the internal structure of the output stage 24 of the power amplifier circuit 12 in FIG. 1A. Common elements between FIGS. 1A and 1B are shown with common element numbers and will not be re-described herein.

[0034] The output stage 24 may include a transistor 36, such as a bipolar junction transistor (BJT) or a complementary metal oxide semiconductor (CMOS) transistor. Taking the BJT as an example, the transistor 36 may include a base electrode B, a collector electrode C, and an emitter electrode E. The collector electrode C is coupled to the output stage collector node 28 to receive the time-varying modulation voltage V PA-O (t).

[0035] The time-varying modulation voltage V PA-O (t) may include both a linear term and a non-linear term, as expressed in Equation (Equation 1) below.

[0036] V PA-O (t) = V DC + A × V ENV (t) + B × V ENV (t) 2 + C × V ENV (t) 3 + … (Equation 1)

[0037] In Equation (Equation 1), V DC represents a constant direct current (DC) voltage, A × V ENV (t) represents the linear term, and B × V ENV (t) 2 + C × V ENV (t) 3 + … represents the non-linear term. Research shows that the time-varying modulation voltage V PA-O (t) is dominated by the linear term A × V ENV (t). Therefore, the time-varying modulation voltage V PA-O (t) can be linearly approximated as Equation (Equation 2).

[0038] V PA-O (t) ≈ V DC + A × V ENV (t) (Equation 2)

[0039] When the time-varying modulation voltage V BC-O is applied across the equivalent capacitor C PA-O between the output stage collector node 28 and the output stage input node 34, the modulated output stage current I BC-O (t) is injected from the output stage collector node 28 into the output stage input node 34. In this regard, the modulated output stage current I BC-O (t) is also referred to as the “modulation leakage current” hereinafter. As shown in Equation (Equation 3) below, the modulated output stage current I BC-O (t) is largely a linear modulation current.

[0040] I CB-O (t) ≈ C BC-O×A×dV ENV (t) / dt (Equation 3)

[0041] Modulate the output stage current I BC-O (t) through the output stage net impedance R presented at the base electrode B of the output stage 24 bb-O Convert to voltage R bb-O ×I CB-O (t), and then add it to the RF signal 14 at the base electrode B of the transistor 36 to generate the distorted base voltage V CB (t), as shown in the following equation (Equation 4).

[0042]

[0043] In the said equation (Equation 4), K RF Represents a dimensionless constant (e.g., constant gain). The time-varying voltage envelope V ENV (t) and the RF signal 14 are remodulated by even-order (mainly second-order) distortion within the output stage 24 to generate an output stage distortion product, which can be expressed as:

[0044]

[0045] It is worth noting that as the derivative of the time-varying voltage envelope V ENV (t), the output stage distortion product inherently has memory (also known as memory effect), which may be difficult to compensate for by techniques such as isoGain and linear digital predistortion (DPD). Therefore, the power amplifier circuit 12 may suffer from reduced ACLR performance. Therefore, it is necessary to prevent the generation of the output stage distortion product, thereby helping to improve the ACLR performance of the power amplifier circuit 12.

[0046] In this regard, Figure 2 Is a schematic diagram of an exemplary differential power amplifier circuit 38A configured according to an embodiment of the present disclosure for neutralizing the output stage distortion presented in the power amplifier circuit 12 of the existing wireless transmission circuit 10 in FIG. 1A. In the embodiment, the differential power amplifier circuit 38A is coupled to the PMIC 40 via a conductive trace 42. Similar to the external conductive trace 20 in FIG. 1A, the conductive trace 42 is also associated with the corresponding equivalent inductive impedance L TRACE-PMIC Associated. Similar to the PMIC18 in FIG. 1A, the PMIC 40 is configured to generate a modulation voltage V ENV (t) associated with the voltage envelope V CC (t) (e.g., ET modulation voltage or APT modulation voltage), and transmit the modulation voltage V CC(t) is provided to the collector node 44 in the differential power amplifier circuit 38A. Generally, the collector node 44 is coupled to a capacitor C LOAD , and the capacitor defines a part of the equivalent capacitance C PA of the differential power amplifier circuit 38A.

[0047] Given the influence of the corresponding equivalent inductive impedance L TRACE-PMIC , the modulation voltage V CC (t) generated by the PMIC 40 can be modified (e.g., in amplitude and / or phase) the modulation voltage V CC (t) received at the collector node 44. For the purpose of distinction, the modulation voltage V CC (t) received at the collector node 44 is hereinafter referred to as "the received modulation voltage V PA (t)".

[0048] The differential power amplifier circuit 38A includes an input stage 46 and an output stage 48. The input stage 46 is configured to amplify the RF signal 50. The output stage 48 is coupled to the input stage 46 via an inter-stage transformer 52 and is configured to receive the amplified RF signal 50 from the input stage 46 via the inter-stage transformer 52.

[0049] The output stage 48 includes a pair of differential amplifiers 54, 56, and each differential amplifier is coupled to the inter-stage transformer 52 via a corresponding DC-blocking capacitor C BLK . The differential amplifiers 54, 56 are each configured to further amplify the RF signal 50 based on the received modulation voltage V PA (t), and the RF signal has been amplified by the input stage 46. The differential amplifiers 54, 56 are each coupled to an output transformer 58, and the output transformer outputs the RF signal after the RF signal 50 is further amplified by the differential amplifiers 54, 56.

[0050] In a non-limiting example, each of the differential amplifiers 54, 56 includes a corresponding heterojunction bipolar transistor (HBT). Specifically, the HBT transistor includes a base electrode (denoted as "B") coupled to the DC-blocking capacitor C BLK and receiving a bias voltage V BIAS , a collector electrode (denoted as "C") coupled to the output transformer 58, and an emitter electrode (denoted as "E") coupled to ground.

[0051] The transistor HBT in each of the differential amplifiers 54, 56 can be the same as the transistor 36 shown in FIG. 1B. In this regard, similar to the transistor 36 in FIG. 1B, the transistor HBT in each of the differential amplifiers 54, 56 may have a corresponding equivalent capacitor C BC-O1and CBC -O2 . Thus, when the received modulation voltage V PA (t) is applied across the equivalent capacitor C BC-O , a pair of modulation output stage currents I BC-O1 (t) and I BC-O2 (t) (the sum of which is equal to the modulation output stage current I BC-O (t) shown in FIG. 1B and represented in Equation (Equation 3) above) can each be injected from the collector electrode C into the base - collector B. In a non - limiting example, the modulation output stage currents I BC-O1 (t) and I BC-O2 (t) are approximately equal. From the foregoing discussion, it can be understood that the modulation output stage currents I BC-O1 (t) and I BC-O2 (t) can re - modulate the voltage envelope V ENV (t) and the RF signal 50 through even - order (primarily second - order) distortion within the output stage 48 to generate output - stage distortion products that may reduce the ACLR of the differential power amplifier circuit 38A.

[0052] In this regard, the output stage 48 is configured to include a neutralization circuit 60. The neutralization circuit 60 is configured to generate an output - stage neutralization current I NEU-O (t), and inject the output - stage neutralization current I NEU-O (t) into the base electrodes B of the transistors HBT in each of the differential amplifiers 54, 56. Specifically, the output - stage neutralization current I NEU-O (t) is generated to include a pair of neutralization currents I NEU-O1 (t) and I NEU-O2 (t), which are respectively approximately equal to the pair of modulation output stage currents I BC-O1 (t) and I BC-O2 (t), but flow in a direction opposite to the pair of modulation output stage currents I BC-O1 (t) and I BC-O2 (t). In other words, I NEU-O1 (t)≈I BC-O1 (t), and I NEU-O2 (t)≈I BC-O2 (t). Herein, each of the neutralization currents I NEU-O1 (t) and I NEU-O2 (t) can be approximately half (1 / 2) of the output - stage neutralization current I NEU-O (t). According to the embodiments described herein, the neutralization circuit 60 is configured to generate the output - stage neutralization current I NEU-O (t) at a baseband frequency (e.g., <200 MHz), which is much lower than the carrier frequency of the RF signal 50 (e.g., >2 GHz). By neutralizing a pair of modulation output stage currents IBC-O1 (t) and I BC-O2 (t), can prevent the generation of undesired memory distortion, thereby helping to improve the ACLR of the differential power amplifier circuit 38A.

[0053] According to an embodiment of the present disclosure, the neutralization circuit 60 is coupled between the center tap 62 of the inter-stage transformer 52 and the center tap 64 of the output transformer 58. The neutralization circuit 60 is configured to receive the modulation voltage V via the center tap 64 of the output transformer 58 PA (t), and derive the output stage neutralization current I from the received modulation voltage V PA (t) NEU-O (t). Thus, the neutralization circuit 60 injects the output stage neutralization current I NEU-O (t) into the center tap 62 of the inter-stage transformer 52.

[0054] It should be noted that the center tap 62 and the center tap 64 are virtual ground (also known as virtual earth) points. In this context, a virtual ground point is a node in a circuit that is maintained at a stable reference potential without being directly connected to any reference potential. Thus, the neutralization circuit 60 can be turned on and off without affecting the amplitude-amplitude (AMAM) and amplitude-phase (AMPM) waterfall curves of the RF signal 50. In addition, it is possible to retrofit the neutralization circuit 60 into an existing differential power amplifier circuit.

[0055] Figure 3A and 3B are schematic diagrams providing exemplary illustrations of the neutralization circuit 60 configured according to various embodiments of the present disclosure. Figure 2 、 3A The common elements between 3B are shown with common element numbers therein and will not be re-described here.

[0056] Referring Figure 3A , in one embodiment, the neutralization circuit 60 can be configured to include an HBT 66 and a mirror circuit 68. The HBT 66 is configured to derive the emitter neutralization current I from the received modulation voltage V PA (t) NEU-S (t). In an alternative embodiment, the HBT 66 can be replaced by a capacitor. The mirror circuit 68 (e.g., a 1-to-N mirror circuit) is configured to amplify the emitter neutralization current I NEU-S (t) (e.g., amplify by a factor of N), reverse the direction of the output stage neutralization current I NEU-O (t), and inject the amplified output stage neutralization current I NEU-O (t) into the center tap 62 of the inter-stage transformer 52.

[0057] Referring Figure 3B, in an alternative embodiment, the neutralization circuit 60 may be configured to include an HBT 66 and a common emitter circuit 70. Herein, the common emitter circuit 70 is configured to amplify the sum of the inter-stage neutralization current I NEU-I (t) and the emitter neutralization current I NEU-S (t), so as to inject the amplified output-stage neutralization current I NEU-O (t) into the center tap 62 of the inter-stage transformer 52.

[0058] Return reference Figure 2 , similar to the power amplifier circuit 12 in FIG. 1A, there is an equivalent coupling capacitor C between the input stage 46 and the output stage 48 in the differential power amplifier circuit 38A CPL . The equivalent coupling capacitor C CPL can also cause a second leakage current (not shown) to be added to the pair of modulated output-stage currents I BC-O1 (t) and I BC-O2 (t). Although this additional leakage current is much smaller (e.g., 10 times smaller) than the pair of modulated output-stage currents I BC-O1 (t) and I BC-O2 (t), it still deteriorates the output-stage distortion product in the output stage 48. In this regard, it may be necessary to further suppress the additional leakage current caused by the equivalent coupling capacitor C CPL .

[0059] Reference Figure 3A , the neutralization circuit 60 may also be configured to derive the inter-stage neutralization current I PA (t) from the received modulated voltage V NEU-I (t) to help suppress the additional leakage current caused by the equivalent coupling capacitor C CPL . Therefore, the mirror circuit 68 will amplify the sum of the emitter neutralization current I NEU-S (t) and the inter-stage neutralization current I NEU-I (t) (e.g., amplified by N times), so as to generate the amplified output-stage neutralization current I NEU-O (t). Therefore, Figure 4 is a schematic diagram of an exemplary differential power amplifier circuit 38B configured according to another embodiment of the present disclosure to further suppress the additional leakage current caused by the equivalent coupling capacitor C CPL . Figure 2 、 3A and the common elements between 4 are shown with common element numbers therein and will not be described again here.

[0060] Herein, the input stage 46 includes an input-stage HBT 72. The neutralization circuit 60 is also configured to derive the inter-stage neutralization current I NEU-I (t) from the collector electrode C of the input-stage HBT 72 in the input stage 46(t), thereby suppressing the additional leakage current caused by the coupling capacitance C between the input stage 46 and the output stage 48. CPL The additional leakage current caused.

[0061] As an alternative to coupling the neutralization circuit 60 to the center tap 64 of the output transformer 58, it is also possible to couple the neutralization circuit to a voltage divider network. Figure 5 is a schematic diagram of an exemplary differential power amplifier circuit 38C configured according to another embodiment of the present disclosure. Figure 2 and 5 Common elements between are shown with common reference numerals therein and will not be described again here.

[0062] The differential power amplifier circuit 38C includes an output stage 48A, wherein the neutralization circuit 60 is coupled to the output transformer 58 via a voltage divider network 74. Thus, the neutralization circuit 60 is configured to receive the modulation voltage V via the voltage divider network 74. PA (t). In a non-limiting example, the voltage divider network 74 is coupled in parallel to the output transformer 58 and is configured to divide the received modulation voltage V. PA (t). Specifically, the neutralization circuit 60 is coupled between the center point 76 of the voltage divider network 74 and the center tap 62 of the inter-stage transformer 52. Then, the neutralization circuit 60 derives the output stage neutralization current I from the modulation voltage V received via the center point 76. PA (t), and injects the output stage neutralization current I. NEU-O (t) into the center tap 62 of the inter-stage transformer 52. NEU-O (t).

[0063] Figure 2 The differential power amplifier circuit 38A of Figure 4 The differential power amplifier circuit 38B of Figure 5 The differential power amplifier circuit 38C of can be provided in a user element (also referred to as a wireless device) to implement the above embodiments. In this regard, Figure 6 is where Figure 2 The differential power amplifier circuit 38A of Figure 4 The differential power amplifier circuit 38B of Figure 5 The differential power amplifier circuit 38C of can be provided. A schematic diagram of an exemplary user element 100.

[0064] In this document, the user element 100 can be any type of user element, such as a mobile terminal, a smartwatch, a tablet computer, a computer, a navigation device, an access point, and similar wireless communication devices that support wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communication. The user element 100 will typically include a control system 102, a baseband processor 104, a transmit circuitry 106, a receive circuitry 108, an antenna switch circuitry 110, a plurality of antennas 112, and a user interface circuitry 114. In a non-limiting example, for instance, the control system 102 can be a field programmable gate array (FPGA). In this regard, the control system 102 can at least include a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 108 receives radio frequency signals from one or more base stations via the antenna 112 and through the antenna switch circuitry 110. A low noise amplifier and a filter cooperate to amplify and neutralize broadband interference from the received signal for processing. Then, a downconversion and digitization circuitry (not shown) downconverts the filtered received signal to an intermediate or baseband frequency signal, and then digitizes the signal into one or more digital streams using an analog-to-digital converter (ADC).

[0065] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0066] For transmission, the baseband processor 104 receives digitized data from the control system 102 that can represent voice, data, or control information, and the baseband processor encodes the digitized data for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the frequency or frequencies to be transmitted. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to the antenna 112 through the antenna switch circuitry 110. The plurality of antennas 112 and replicated transmit circuitry 106 and receive circuitry 108 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0067] In an embodiment, the transmit circuitry 106 can act as a wireless transmit circuit. Thus, the transmit circuitry 106 can be configured to include Figure 2 a differential power amplifier circuit 38A of Figure 4 a differential power amplifier circuit 38B of Figure 5any one of the differential power amplifier circuits 38C.

[0068] In an embodiment, it is possible to neutralize based on during a process and Figure 2 the differential power amplifier circuit 38A, Figure 4 the differential power amplifier circuit 38B, and / or Figure 5 the memory distortion in the differential power amplifier circuit 38C. In this regard, Figure 7 is for neutralizing Figure 2 the differential power amplifier circuit 38A, Figure 4 the differential power amplifier circuit 38B, and Figure 5 the flowchart of an exemplary process 200 for neutralizing the memory distortion in the differential power amplifier circuit 38C.

[0069] In this document, process 200 includes receiving a modulation voltage V PA (t) and an RF signal 50 (step 202). Process 200 also includes amplifying the RF signal 50 based on the modulation voltage V PA (t) (step 204). Process 200 also includes outputting the RF signal 50 amplified by each of a pair of differential amplifiers 54, 56 (step 206). Process 200 also includes injecting an output stage neutralization current I NEU-O (t) into each of the pair of differential amplifiers 54, 56, thereby suppressing the modulation leakage current (I PA (t)) caused by the modulation voltage V BC-O (t) in each of the pair of differential amplifiers 54, 56 (step 208).

[0070] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A differential power amplifier circuit (38A, 38B, 38C) comprising an output stage (48, 48A), the output stage including: A collector node (44) coupled to a power management integrated circuit PMIC (40) to receive a modulation voltage; An inter-stage transformer (52) configured to receive a radio frequency RF signal (50); A pair of differential amplifiers (54, 56), each of the pair of differential amplifiers being coupled to the inter-stage transformer (52) and configured to amplify the RF signal (50) based on the modulation voltage received via the collector node (44); An output transformer (58) coupled to each of the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulation voltage, the output transformer (58) being configured to output the RF signal (50) amplified by each of the pair of differential amplifiers (54, 56); and Neutralization circuit (60), the neutralization circuit being coupled between the inter-stage transformer (52) and the output transformer (58), and configured to inject an output stage neutralization current (I NEU-O (t)) into each of the pair of differential amplifiers (54, 56) so as to suppress the modulation leakage current (I BC-O (t)) caused by the modulation voltage in each of the pair of differential amplifiers (54, 56).

2. The differential power amplifier circuit according to claim 1, wherein: Each of the pair of differential amplifiers includes a heterojunction bipolar transistor HBT having a base electrode coupled to the inter-stage transformer via a DC blocking capacitor, a collector electrode coupled to the output transformer to receive the modulation voltage, and an emitter electrode coupled to ground; and The neutralization circuit is further configured to inject an output stage neutralization current into the base electrode of the HBT in each of the pair of differential amplifiers, thereby suppressing the modulation leakage current caused by the equivalent capacitance of the HBT in each of the pair of differential amplifiers and the modulation voltage.

3. The differential power amplifier circuit according to claim 2, wherein the neutralization circuit is further configured to inject the output stage neutralization current in a direction opposite to the direction of the modulation leakage current flowing through the HBT in each of the pair of differential amplifiers.

4. The differential power amplifier circuit according to claim 3, wherein the output stage neutralization current includes a pair of neutralization currents, each of the pair of neutralization currents being equal to half of the output stage neutralization current.

5. The differential power amplifier circuit (38A, 38B) according to claim 1, wherein the neutralization circuit (60) is coupled between the center tap (62) of the inter-stage transformer (52) and the center tap (64) of the output transformer (58) and is configured to: Receive the modulation voltage via the center tap (64) of the output transformer (58); Derive the output stage neutralization current from the modulation voltage; And Inject the output stage neutralization current into the center tap (62) of the inter-stage transformer (52).

6. The differential power amplifier circuit (38A, 38B) according to claim 5, wherein the neutralization circuit (60) includes: One of a heterojunction bipolar transistor HBT (66) and a capacitor, one of the heterojunction bipolar transistor and the capacitor being configured to emit an emitter neutralization current (I NEU-S (t)) from the modulation voltage; And A mirror circuit (68), the mirror circuit being configured to at least amplify the emitter neutralization current (I NEU-S (t)), thereby generating an amplified output stage neutralization current and injecting the amplified output stage neutralization current into the center tap of the inter-stage transformer.

7. The differential power amplifier circuit (38A, 38B) according to claim 5, wherein the neutralization circuit (60) comprises: Heterojunction bipolar transistor HBT (66), the heterojunction bipolar transistor being configured to derive an emitter neutralization current (I NEU-S (t)) from the modulation voltage; and Common stage circuit (70), the common stage circuit being configured to at least amplify the emitter neutralization current (I NEU-S (t)), thereby generating an amplified output stage neutralization current and injecting the amplified output stage neutralization current into the center tap of the inter-stage transformer.

8. The differential power amplifier circuit (38A, 38B, 38C) according to claim 6 or 7, further comprising an input stage (46) coupled to the inter-stage transformer (52), wherein the neutralization circuit (60) is further configured to: Derive the inter-stage neutralization current (I NEU-I (t)) from the modulation voltage; and Amplify the sum of the emitter neutralizing current (I NEU-S (t)) and the inter-stage neutralizing current (I NEU-I (t)), thereby generating the inter-stage neutralizing current (I NEU-I (t)) and injecting the inter-stage neutralizing current into the center tap (62) of the inter-stage transformer (52), thereby suppressing the additional leakage current caused by the coupling capacitance between the input stage (46) and the output stages (48, 48A).

9. The differential power amplifier circuit (38C) according to claim 1, wherein: the output stage (48A) further comprises a voltage divider network (74), the voltage divider network being coupled in parallel to the output transformer (58) and configured to divide the modulation voltage received via the collector node (44); and the neutralization circuit (60) is coupled between the center point (76) of the voltage divider network (74) and the center tap (62) of the inter-stage transformer (52), the neutralization circuit (60) being configured to: receive the modulation voltage via the center point (76) of the voltage divider network (74); derive the output stage neutralization current from the modulation voltage; and inject the output stage neutralization current into the center tap (62) of the inter-stage transformer (52).

10. The differential power amplifier circuit according to claim 1, wherein the neutralization circuit is further configured to generate the output stage neutralization current at a baseband frequency.

11. A wireless device (100) comprising a transmit circuit system (106), the transmit circuit system (106) comprising a differential power amplifier circuit (38A, 38B, 38C), the differential power amplifier circuit comprising an output stage (48, 48A), the output stage comprising: a collector node (44), the collector node being coupled to a power management integrated circuit PMIC (40) to receive a modulation voltage; an inter-stage transformer (52), the inter-stage transformer being configured to receive a radio frequency RF signal (50); a pair of differential amplifiers (54, 56), each of the pair of differential amplifiers being coupled to the inter-stage transformer (52) and configured to amplify the RF signal (50) based on the modulation voltage received via the collector node (44); an output transformer (58), the output transformer being coupled to each differential amplifier of the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulation voltage, the output transformer (58) being configured to output the RF signal (50) amplified by each differential amplifier of the pair of differential amplifiers (54, 56); and Neutralization circuit (60), the neutralization circuit being coupled between the inter-stage transformer (52) and the output transformer (58), and configured to inject an output stage neutralization current (I NEU-O (t)) into each of the pair of differential amplifiers (54, 56), thereby suppressing the modulation leakage current (I BC-O (t)) caused by the modulation voltage in each of the pair of differential amplifiers (54, 56).

12. The wireless device according to claim 11, wherein: each of the pair of differential amplifiers comprises a heterojunction bipolar transistor HBT having a base electrode coupled to the inter-stage transformer via a DC blocking capacitor, a collector electrode coupled to the output transformer to receive the modulation voltage, and an emitter electrode coupled to ground; and The neutralization circuit is further configured to inject the output-stage neutralization current into the base electrode of the HBT in each of the pair of differential amplifiers, thereby suppressing the modulation leakage current caused jointly by the equivalent capacitance of the HBT in each of the pair of differential amplifiers and the modulation voltage.

13. The wireless device according to claim 12, wherein the neutralization circuit is further configured to inject the output-stage neutralization current in a direction opposite to the modulation leakage current flowing through the HBT in each of the pair of differential amplifiers.

14. The wireless device (100) according to claim 11, wherein the neutralization circuit (60) is coupled between the center tap (62) of the inter-stage transformer (52) and the center tap (64) of the output transformer (58), and is configured to: Receive the modulation voltage via the center tap (64) of the output transformer (58); Derive the output-stage neutralization current from the modulation voltage; And Inject the output-stage neutralization current into the center tap (62) of the inter-stage transformer (52).

15. The wireless device (100) according to claim 14, wherein the neutralization circuit (60) comprises: One of a heterojunction bipolar transistor HBT (66) and a capacitor, one of the heterojunction bipolar transistor and the capacitor being configured to emit an emitter neutralization current (I NEU-S (t)) from the modulation voltage; And A mirror circuit (68), the mirror circuit being configured to at least amplify the emitter neutralization current (I NEU-S (t)), thereby generating an amplified output stage neutralization current and injecting the amplified output stage neutralization current into the center tap of the inter-stage transformer.

16. The wireless device (100) according to claim 14, wherein the neutralization circuit (60) comprises: Heterojunction bipolar transistor HBT (66), the heterojunction bipolar transistor being configured to derive an emitter neutralization current (I NEU-S (t)) from the modulation voltage; And Common stage circuit (70), the common stage circuit being configured to at least amplify the emitter neutralization current (I NEU-S (t)), thereby generating an amplified output stage neutralization current and injecting the amplified output stage neutralization current into the center tap of the inter-stage transformer.

17. The wireless device (100) according to claim 15 or 16, wherein the differential power amplifier circuit (38A, 38B, 38C) further comprises an input stage (46) coupled to the inter-stage transformer (52), wherein the neutralization circuit (60) is further configured to: Derive the inter-stage neutralization current (I NEU-I (t)) from the modulation voltage; and Amplify the sum of the emitter neutralizing current (I NEU-S (t)) and the inter-stage neutralizing current (I NEU-I (t)) to generate the inter-stage neutralizing current (I NEU-I (t)) and inject the inter-stage neutralizing current into the center tap (62) of the inter-stage transformer (52), thereby suppressing the additional leakage current caused by the coupling capacitance between the input stage (46) and the output stages (48, 48A).

18. The wireless device (100) according to claim 11, wherein: The output stage (48A) further comprises a voltage divider network (74), the voltage divider network being coupled in parallel to the output transformer (58) and being configured to divide the modulation voltage received via the collector node (44); and The neutralization circuit (60) is coupled between the center point (76) of the voltage divider network (74) and the center tap (62) of the inter-stage transformer (52), the neutralization circuit (60) being configured to: Receive the modulation voltage via the center point (76) of the voltage divider network (74); Derive the output-stage neutralization current from the modulation voltage; And Inject the output-stage neutralization current into the center tap (62) of the inter-stage transformer (52).

19. A method for neutralizing memory distortion in a differential power amplifier circuit (38A, 38B, 38C), comprising: Receiving a modulation voltage (V PA (t)) and a radio frequency (RF) signal (50); Amplifying the RF signal (50) based on the modulation voltage; Outputting the RF signal (50) amplified by each of a pair of differential amplifiers (54, 56); And Inject the output stage neutralizing current (I NEU-O (t)) into each of the pair of differential amplifiers (54, 56) to suppress the modulation leakage current (I BC-O (t)) caused by the modulation voltage in each of the pair of differential amplifiers (54, 56).

20. The method according to claim 19, wherein: Receiving the modulation voltage includes receiving the modulation voltage via a collector node (44) coupled to a power management integrated circuit PMIC (40); Receiving the RF signal (50) includes receiving the RF signal (50) via an inter-stage transformer (52); Amplifying the RF signal (50) includes amplifying the RF signal (50) using a pair of differential amplifiers (54, 56) each coupled to the inter-stage transformer (52); Outputting the RF signal (50) includes outputting the RF signal (50) from an output transformer (58) coupled to each of the pair of differential amplifiers (54, 56) and having a center tap (64) coupled to the collector node (44) to receive the modulation voltage; and Injecting the output stage neutralizing current (I NEU-O (t)) into each of the pair of differential amplifiers (54, 56) includes injecting the output stage neutralizing current (I NEU-O (t)) using a neutralizing circuit (60) coupled between the inter-stage transformer (52) and the output transformer (58).

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