Active snubber circuit

Abstract

In some examples, an apparatus includes a transistor (202) having a control terminal, where the transistor is coupled between a power terminal (118) and a ground terminal (120). The apparatus also includes a resistor (204). The apparatus also includes a controller (206) having first and second controller inputs and first and second controller outputs, where the first controller input is coupled to the power terminal, the second controller input is coupled to the control terminal, and the first controller output is coupled to the control terminal. The first controller output is coupled to the control terminal, and the resistor is coupled between the control terminal and the second controller output.

Description

BACKGROUND OF THE INVENTION

[0001] A switched-mode power supply (SMPS) transfers power from an input power supply to a load by switching one or more power transistors or other switching elements, which are coupled to an energy storage element (e.g., an inductor, an inductance of a transformer, and / or a capacitor) that can be coupled to the load via a switching node / terminal. The power transistor may be included in a power converter that includes the energy storage element or is capable of being coupled to the energy storage element. SUMMARY OF THE INVENTION

[0002] In some examples, a device includes a first transistor having a first control terminal, where the first transistor is coupled between a power terminal and a ground terminal. The device further includes a second transistor having a second control terminal, where the second transistor is coupled between the first control terminal and the ground terminal. The device further includes a resistor. The device further includes a third transistor having a third control terminal, where the third transistor is coupled between the resistor and the ground terminal, and the resistor is coupled between the first control terminal and the third transistor. The device further includes circuitry having a first input, a second input, a first output, and a second output, where the first input is coupled to the power terminal, the second input is coupled to the first control terminal, the first output is coupled to the second control terminal, and the second output is coupled to the third control terminal.

[0003] In some examples, a device includes a transistor having a control terminal, where the transistor is coupled between a power terminal and a ground terminal. The device further includes a resistor. The device further includes a controller having a first controller input, a second controller input, a first controller output, and a second controller output, where the first controller input is coupled to the power terminal, the second controller input is coupled to the control terminal, the first controller output is coupled to the control terminal, and the resistor is coupled between the control terminal and the second controller output.

[0004] In some examples, a system includes a switching regulator having a regulator input and a switching node, the regulator input being coupled to a power supply voltage terminal. The system also includes a buffer circuit coupled to the switching node. The buffer circuit includes a first transistor having a first control terminal, wherein the first transistor is coupled between a power terminal and a ground terminal. The buffer circuit also includes a resistor. The buffer circuit also includes a buffer controller. The buffer controller includes a second transistor having a second control terminal, wherein the second transistor is coupled between the first control terminal and the ground terminal. The buffer controller also includes a third transistor having a third control terminal, wherein the third transistor is coupled between the resistor and the ground terminal, and the resistor is coupled between the first control terminal and the third transistor. The buffer controller also includes circuitry having a first input, a second input, a first output, and a second output, wherein the first input is coupled to the power terminal, the second input is coupled to the first control terminal, the first output is coupled to the second control terminal, and the second output is coupled to the third control terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a system according to various examples.

[0006] Figure 2 is a schematic diagram of a buffer circuit according to various examples.

[0007] Figure 3 is a timing diagram of signals in a buffer circuit according to various examples.

[0008] Figure 4 is a schematic diagram of a buffer circuit according to various examples.

[0009] Figure 5 is a timing diagram of signals in a buffer circuit according to various examples.

[0010] Figure 6 is a schematic diagram of a buffer circuit according to various examples.

[0011] Figure 7 is a timing diagram of signals in a buffer circuit according to various examples.

[0012] Figure 8 is a timing diagram of signals in a system according to various examples. DETAILED DESCRIPTION

[0013] As described above, a SMPS transfers power from an input power source to a load by switching one or more power transistors or other switching elements. The switching of the power transistors of the SMPS can create voltage transients or ringing in the output voltage of the SMPS. As the switching speed of the power transistors increases, the amplitude of the voltage transients caused by the switching in the output voltage may also increase. Large voltage transients or ringing can adversely affect the operation of the SMPS (or the load), may reduce the efficiency of the energy conversion between the input power source and the load, or have other adverse effects on the input power source, the SMPS, and / or the load.

[0014] There are various methods for mitigating voltage transients, one of which is to implement a buffer circuit. The buffer circuit limits voltage transients. However, conventional buffer circuit architectures may consume a greater amount of energy than is compatible with the power reduction specifications for some devices or application environments used with SMPSs.

[0015] Examples of this specification mitigate transient voltages in the output voltage of a SMPS. The examples described can be implemented as a buffer circuit that mitigates transient voltages or ringing. In some examples, the buffer circuit is an active buffer circuit. Compared to a passive buffer circuit that can be formed by passive circuit elements, an active buffer circuit can have certain circuit characteristics that vary in response to changes in the output voltage of the SMPS. The buffer circuit can monitor the voltage value of the SMPS compared to a target value or a programmed value. In response to the monitored voltage value being greater than the target value, the buffer circuit can be activated. In response to the output voltage value not being greater than the target value, the buffer circuit can be deactivated, thereby reducing the power consumption of the components of the buffer circuit and / or the SMPS.

[0016] Figure 1 is a block diagram of a system 100 according to various examples. System 100 represents an application that provides power to a load. For example, system 100 represents a motor vehicle or other vehicle, a computing device such as a laptop computer, a notebook computer, a server, a smartphone, a tablet computer, a wearable device, etc. System 100 can include a SMPS or other power source, etc. In an example, system 100 includes a load 102, a power converter 104, and a control circuitry 106. In an example, the power converter 104 is a switching regulator that includes a switching circuit 108 and an energy storage component 110. The control circuitry 106 includes a controller 112 and a buffer circuit 114. Some examples of system 100 also include a gate driver 116. Although shown as Figure 1 separate from the power converter 104 and the control circuitry 106 in, in some examples, the gate driver 116 can be incorporated into the power converter 104 or the control circuitry 106. In an example, as Figure 1As shown, the components of system 100 are coupled. In an example, controller 112 includes any suitable analog components, digital components, or combinations thereof for implementing a circuit architecture suitable for determining a value of a gate control signal or a gate drive signal and providing the gate control signal to gate driver 116 or providing the gate drive signal to power converter 104 for controlling the switches of power converter 104.

[0017] In an example of operation of system 100, power converter 104 receives an input voltage (VDD) from a power source (not shown) and provides an output voltage (VOUT) based on VDD and control applied to power converter 104 by control circuitry 106. Power converter 104 can have any suitable architecture, such as buck, boost, or buck-boost. VOUT is provided to load 102 to power components (not shown) of load 102 and / or facilitate other operations of load 102. In an example, control circuitry 106 controls power converter 104 according to pulse frequency modulation (PFM). For example, control circuitry 106 provides a gate control signal that causes gate driver 116 to provide a gate drive signal to switch circuit 108 to turn on or off the switches of power converter 104. The gate control signal can be timed such that the switches of switch circuit 108 (not shown) are turned on (e.g., in a conductive state) or off (e.g., in a non-conductive state) for an amount of time determined based on a programmed value of VOUT. For example, for a larger value of VOUT relative to VDD in a buck architecture, the gate control signal can cause the switches of switch circuit 108 to be turned on for a longer period of time compared to a smaller value of VOUT relative to VDD.

[0018] In an example, a buffer circuit 114 is coupled between a switch node 118 and a ground terminal 120. The switch node 118 is a node of a power converter 104 at which a switch circuit 108 is coupled to an energy storage component 110. The buffer circuit 114 limits a voltage amplitude and / or a voltage increase rate at the switch node 118. However, in doing so, the buffer circuit 114 increases power losses of the system 100 and thus reduces an efficiency of power transfer between a power supply and a load 102. To mitigate the power losses, the buffer circuit 114 is configured to monitor a voltage (SW) provided at the switch node 118. In response to determining that SW has a value greater than a target voltage, the buffer circuit 114 is configured to be active and conduct current from the switch node 118 to the ground terminal 120 to mitigate a voltage transient or ringing at the switch node 118 and thus mitigate a voltage transient or ringing in VOUT. In response to determining that SW has a value not greater than the target voltage, the buffer circuit 114 is configured to be inactive and not conduct current from the switch node 118 to the ground terminal 120, thereby reducing power consumption of the buffer circuit 114. For example, compared to other buffer implementations, power consumption of the buffer circuit 114 can be reduced between a time when a value of SW starts to increase and a time when the value of SW is greater than the target voltage. This reduction can be achieved by the buffer circuit 114 being inactive during the above-mentioned time period in which the value of SW increases in response to the buffer circuit 114 monitoring the value of SW and comparing the value of SW with the target voltage.

[0019] Figure 2FIG. 0 is a schematic diagram of a buffer circuit 114 according to various examples. In an example implementation, the buffer circuit 114 includes a buffer transistor 202, a buffer resistor 204, and a buffer controller 206. The buffer controller 206 includes a comparator 208, a control circuitry 210, a transistor 212, a transistor 214, a comparator 216, and a bias source 218. In an example architecture of the buffer circuit 114, the buffer transistor 202 has a drain coupled to a switch node 118, a source coupled to a ground terminal 120, and a gate. As used herein, the gate of a transistor may be referred to as the control terminal of the transistor. The buffer resistor 204 is coupled between the gate of the buffer transistor 202 and the buffer controller 206. The comparator 208 has a first input coupled to the switch node 118, a second input coupled to a target voltage terminal 220, and an output. The control circuitry 210 has a first input coupled to the output of the comparator 208, a second input, and an output. The transistor 212 has a drain coupled to the gate of the buffer transistor 202, a source coupled to the ground terminal 120, and a gate coupled to the output of the control circuitry 210. The transistor 214 has a drain coupled to the buffer resistor 204 (e.g., coupled to the gate of the buffer transistor 202 through the buffer resistor 204), a source coupled to the ground terminal 120, and a gate. The comparator 216 has a first input coupled to the gate of the buffer transistor 202, a second input, and an output coupled to the gate of the transistor 214 and the second input of the control circuitry 210. The bias source 218 is coupled to the second input of the comparator 216.

[0020] In Figure 2 an example of the operation of the buffer circuit 114, under the control of the controller 112, the value of SW increases based on the switching behavior of the switch circuit 108 and the energy storage component 110. In response to the value of SW increasing to exceed the value of a target voltage (Vtrg), a signal (V1) provided at the output of the comparator 208 has an asserted value, such as a value of logic 1. Otherwise, the signal provided at the output of the comparator 208 has a de-asserted value, such as a value of logic 0 (e.g., in response to the value of SW being less than Vtrg). As the value of SW increases, the current flowing through the buffer transistor 202 also increases. In response to the value of the current flowing through the buffer transistor 202 increasing to exceed the value of a bias current (Ib) provided via the bias source 218, a signal (V2) provided at the output of the comparator 216 has an asserted value, such as a value of logic 1. Otherwise, the signal provided at the output of the comparator 216 has a de-asserted value, such as a value of logic 0 (e.g., in response to the value of the current flowing through the buffer transistor 202 being less than Ib). In some examples, the bias source 218 is a current source that provides Ib. In other examples, the bias source 218 is a resistor coupled between a voltage source (not shown) and the comparator 216.

[0021] Based on the signals provided by comparator 208 and comparator 216, control circuitry 210 determines signal (V3) and provides the signal to the gate of transistor 212 to control the conductivity of transistor 212. Transistor 212 and transistor 214, together with buffer resistor 204, control the resistance provided at the gate of buffer transistor 202 and thus control turning buffer transistor 202 on or off. For example, in response to V2 having an asserted value, the gate-to-source voltage (Vgs) of transistor 214 has a high enough value to turn transistor 214 on and allow current to flow between its drain and source. During the time transistor 214 is on, current is drawn from the gate of buffer transistor 202 through buffer resistor 204 and transistor 214, discharging the gate voltage of buffer transistor 202 to ground terminal 120. In response to V2 transitioning to have a de-asserted value, transistor 214 turns off and control circuitry 210 provides V3 having an asserted value. In response to V3 having an asserted value, the Vgs of transistor 212 has a high enough value to turn transistor 212 on and allow current to flow between its drain and source, holding the gate of buffer transistor 202 at ground potential (e.g., the potential provided at ground terminal 120).

[0022] Figure 3 is a timing diagram 300 of signals in a buffer circuit according to various examples. In some examples, diagram 300 depicts signals that may be provided in Figure 2 buffer circuit 114. Diagram 300 includes SW, Vtrg, V1, V2, V3, and the resistance (Rg) of buffer resistor 204 as seen at the gate of buffer transistor 202.

[0023] As shown in diagram 300 and as described above with respect to Figure 2As described, in response to the value of SW increasing beyond Vtrg at time t1, V1 is asserted. Similarly, in response to the current flowing through buffer transistor 202 increasing beyond Ib (both not shown), V2 is asserted at time t2. In response to the assertion of V2, transistor 214 becomes conductive, drawing current from the gate of buffer transistor 202 through buffer resistor 204 and transistor 214. Based on the combinational logic of control circuitry 210, V3 is determined based on V1 and V2, where the conductivity of transistor 212 is controlled according to V3. In response to current being drawn from the gate of buffer transistor 202 through buffer resistor 204 and transistor 214, the current flowing through buffer transistor 202 decreases. In response to the value of the current flowing through buffer transistor 202 decreasing below the value of Ib at time t3, V2 is deasserted and transistor 214 turns off. In response to the deassertion of V2 (e.g., the occurrence of a falling edge in V2) and V1 having an asserted value, V3 becomes asserted and transistor 212 turns on, thereby holding the gate of buffer transistor 202 at ground potential, as described above with respect to Figure 2 as described.

[0024] Figure 4is a schematic diagram of a buffer circuit 114 according to various examples. In an example implementation, the buffer circuit 114 includes a buffer transistor 402, a buffer resistor 404, and a buffer controller 406. The buffer controller 406 includes a transistor 408, control circuitry 410, logic circuitry 412, a transistor 414, a transistor 416, a transistor 418, a bias source 420, and logic circuitry 422. In an example architecture of the buffer circuit 114, the buffer transistor 402 has a drain coupled to a switch node 118, a source coupled to a ground terminal 120, and a gate. The buffer resistor 404 is coupled between the gate of the buffer transistor 402 and the buffer controller 406. The transistor 408 has a drain coupled to the switch node 118, a gate coupled to a power voltage terminal 424, and a source. The control circuitry 410 has a data input coupled to the source of the transistor 408, a reset input coupled to the source of the transistor 408, a clock input, and an inverted data output. In some examples, the control circuitry 410 is implemented as a latch, such as a D flip-flop. The logic circuitry 412 has a first input coupled to the source of the transistor 408, a second input coupled to the inverted data output of the control circuitry 410, and an output. In some examples, the logic circuitry 412 is a NAND digital logic gate or a circuit capable of performing a NAND operation. The transistor 414 has a drain coupled to the gate of the buffer transistor 402, a source coupled to the ground terminal 120, and a gate coupled to the output of the logic circuitry 412. The transistor 416 has a drain coupled to the buffer resistor 404 (e.g., coupled to the gate of the buffer transistor 402 through the buffer resistor 404), a source coupled to the ground terminal 120, and a gate. The transistor 418 has a gate coupled to the gate of the buffer transistor 402, a source coupled to the ground terminal 120, and a drain coupled to the clock input of the control circuitry 410. The bias source 420 is coupled between the power voltage terminal 424 and the drain of the transistor 418. The logic circuitry 422 has an input coupled to the drain of the transistor 418 and an output coupled to the gate of the transistor 416. In some examples, the logic circuitry 422 is a NOT digital logic gate (e.g., an inverter) or a circuit capable of performing a NOT (e.g., inversion) operation.

[0025] In Figure 4In an example of the operation of the buffer circuit 114, in response to SW having a low value, such as a value of logic 0, the voltage (V1) provided at the source of transistor 408 also has a low value. In some examples, the supply voltage (VCC) provided at the supply voltage terminal 424 has a value sufficiently greater than the value of SW to keep transistor 408 in a conductive state, such that a signal having a value approximately the same as that of SW is provided based on SW at the source of transistor 408. The low value of V1 causes the control circuitry 410 to enter a reset mode and provide a voltage (V2) having a low value at the inverted data output. Based on both V1 and V2 having low values, the logic circuit 412 provides a voltage (V3) having a high value at the output of the logic circuit 412. The high value of V3 causes transistor 414 to become conductive, thereby drawing current from the gate of buffer transistor 402 to the ground terminal 120. The current drawn from the gate of buffer transistor 402 is also drawn from the gate of transistor 418, thereby turning off transistor 418 and rendering it non-conductive between its drain and source. The bias current (Ib) provided by the bias source 420 has a value large enough such that the voltage (V4) present at the input of the logic circuit 422 has a high value, and correspondingly, the voltage (V5) provided at the output of the logic circuit 422 has a low value. The low value of V5 is not sufficient to cause transistor 416 to become conductive between its drain and source, thereby turning off transistor 416. Because transistor 416 is turned off, the buffer resistor 404 is part of an open circuit and has no effect on the gate resistance of buffer transistor 402. Thus, the gate resistance of buffer transistor 402 is controlled via the coupling through transistor 414 between the gate of buffer transistor 402 and ground, such that the gate resistance of buffer transistor 402 is approximately zero.

[0026] In response to an increase in the value of SW, the value of V1 increases proportionally to SW. In response to the value of V1 increasing from a low value to a high value, the logic circuit 412 provides V3 with a low value. The low value of V3 turns off the transistor 414, rendering it non-conductive between its drain and source. As described above, the transistor 416 is also non-conductive, causing the gate resistance of the buffer transistor 402 to have a relatively large resistance, approximately infinite, since the gate of the buffer transistor 402 is a floating node (e.g., a high-impedance node with an unknown or uncontrolled value). As the value of SW continues to increase, the gate-to-drain capacitance coupling of the buffer transistor 402 turns on the buffer transistor 402 and renders it conductive between its source and drain. The voltage generated by the gate-to-drain capacitance coupling at the gate of the buffer transistor 402 is also provided at the gate of the transistor 418, which turns on the transistor 418 and renders it conductive between its drain and source. Ib is absorbed through the transistor 418 to the ground terminal 120, causing V4 to have a low value and, correspondingly, V5 to have a high value. The high value of V5 turns on the transistor 416, causing the gate resistance of the buffer transistor 402 to be approximately equal to the resistance of the buffer resistor 404.

[0027] The buffer resistor 404 absorbs current from the gate of the buffer transistor 402 until the voltage at the gate of the buffer transistor 402 is insufficient to maintain the buffer transistor 402 in a conductive state and the buffer transistor 402 turns off. Correspondingly, the transistor 418 also turns off. In response to the transistor 418 turning off, Ib again causes V4 to have a high value and, correspondingly, V5 to have a low value, as described above. Also as described above, the low value of V5 turns off the transistor 416 and eliminates the effect of the buffer resistor 404 on the gate resistance of the buffer transistor 402. The transition of V4 from a low value to a high value also clocks the control circuitry 410, causing the control circuitry 410 to provide V2 with a low value. Based on the high value of V1 and the low value of V2, the logic circuit 412 again provides V3 with a high value, turning on the transistor 414, as described above. The operation of the buffer circuit 114 continues as described above after the transistor 414 turns on until a transient in SW decreases such that SW no longer increases to a value sufficient to turn on the buffer transistor 402 due to the gate-to-drain capacitance coupling of the buffer transistor 402.

[0028] Figure 5 is a timing diagram 500 of signals in a buffer circuit according to various examples. In some examples, the diagram 500 depicts signals that may be provided in Figure 4 the buffer circuit 114. The diagram 500 includes SW, Vtrg, V1, V2, V3, V4, and V5, as well as the resistance (Rg) of the buffer resistor 404 as seen at the gate of the buffer transistor 402.

[0029] As shown in FIG. 500 and as described above with respect to Figure 4 Upon the value of SW increasing above Vtrg at time t1, V1 is asserted. V2 has a value determined based on the operation of control circuitry 410 such that the inverted value of the value of V1 received by control circuitry 410 simultaneously with the rising edge in V4 is provided as the value of V2. In response to both V1 and V2 having asserted values, V3 is provided with a de-asserted value. In response to either V1 or V2 or both V1 and V2 having de-asserted values, V3 is provided with an asserted value. In response to the current flowing through buffer transistor 402 increasing above Ib (both not shown) at time t2, V4 is de-asserted. In response to the de-assertion of V4, V5 is provided with an asserted value and vice versa such that V4 and V5 have inverted values. In response to the assertion of V5, transistor 416 becomes conductive, drawing current from the gate of buffer transistor 402 through buffer resistor 404 and transistor 416. In response to the current being drawn from the gate of buffer transistor 402 through buffer resistor 404 and transistor 416, the current flowing through buffer transistor 402 decreases. In response to the value of the current flowing through buffer transistor 402 decreasing below the value of Ib at time t3, V4 is asserted, V5 is de-asserted, and transistor 416 turns off. In response to the de-assertion of V5 (e.g., the occurrence of a falling edge in V5) and either or both of V1 or V2 having de-asserted values, V3 becomes asserted and transistor 414 turns on, thereby holding the gate of buffer transistor 402 at ground potential, as described above with respect to Figure 4 described.

[0030] Figure 6Schematic diagram of buffer circuit 114 according to various examples. In an example implementation, buffer circuit 114 includes buffer transistor 602, buffer resistor 604, and buffer controller 606. Buffer controller 606 includes transistor 608, resistor 610, capacitor 612, resistor 614, logic circuit 616, transistor 618, transistor 620, logic circuit 622, transistor 624, and resistor 626. In an example architecture of buffer circuit 114, buffer transistor 602 has a drain coupled to switch node 118, a source coupled to ground terminal 120, and a gate. Buffer resistor 604 is coupled between the gate of buffer transistor 602 and buffer controller 606. Transistor 608 has a drain coupled to switch node 118, a gate coupled to ground terminal 120 through resistor 610, and a source. Capacitor 612 and resistor 614 are each coupled between the source of transistor 608 and ground terminal 120. Logic circuit 616 has an input and an output coupled to the source of transistor 608. In some examples, logic circuit 616 is a NOT digital logic gate (e.g., an inverter) or a circuit capable of performing a NOT (e.g., inversion) operation. Transistor 618 has a drain coupled to the source of buffer transistor 602, a gate coupled to the output of logic circuit 616, and a source coupled to ground terminal 120. Transistor 620 has a drain coupled to buffer resistor 604 (e.g., coupled to the gate of buffer transistor 602 through buffer resistor 604), a source coupled to ground terminal 120, and a gate. Logic circuit 622 has an output and an input coupled to the gate of transistor 620. In some examples, logic circuit 622 is a NOT digital logic gate (e.g., an inverter) or a circuit capable of performing a NOT (e.g., inversion) operation. Transistor 624 has a gate coupled to the gate of buffer transistor 602, a source coupled to ground terminal 120, and a drain coupled to power supply voltage terminal 628 through resistor 626.

[0031] In Figure 6 an example of the operation of buffer circuit 114, in response to SW having a low value, e.g., a value of logic 0, the gate of transistor 608 is held at ground potential through resistor 610, such that transistor 608 is turned off to make V3 have a low value and make V4 have a high value, e.g., a value of logic 1. Similarly, buffer transistor 602 is turned off, transistor 624 is turned off, V1 is held at a high value through resistor 626, and V2 has a low value. The low value of V2 turns off transistor 620. Conversely, the high value of V4 turns on transistor 618, thereby holding the gate of buffer transistor 602 at ground potential to keep buffer transistor 602 turned off.

[0032] In response to the value of SW increasing to a high value, the drain-to-gate capacitance coupling causes V5 to increase, thus turning on transistor 608. In response to transistor 608 turning on, V3 has an asserted value and V4 has a de-asserted value, thus turning off transistor 618. The drain-to-gate capacitance coupling of buffer transistor 602 also causes energy to be coupled from switch node 118 to the gate of buffer transistor 602, thus turning on buffer transistor 602 and drawing current from switch node 118. The energy provided at the gate of buffer transistor 602 is also provided at the gate of transistor 624, thus turning on transistor 624, pulling V1 down to a low value, and correspondingly pulling V2 to a high value. The high value of V2 causes transistor 620 to transition. In response to transistor 620 turning on, the gate resistance of buffer transistor 602 (e.g., the resistance seen at the gate of buffer transistor 602) is approximately equal to the resistance of buffer resistor 604. The current at the gate of buffer transistor 602 is absorbed to ground terminal 120 through buffer resistor 604 and transistor 620, thus slowly reducing the current at the gate of buffer transistor 602 until buffer transistor 602 and transistor 624 turn off.

[0033] The value of V5 decreases, and the current discharges to ground terminal 120 through resistor 610 until the value of V5 is insufficient to maintain transistor 608 in a conducting state and transistor 608 turns off. In response to transistor 608 turning off, V3 begins to discharge to ground terminal 120 through resistor 614 at a rate determined by the capacitance of capacitor 612 and the resistance of resistor 614. In response to the value of V3 decreasing below a threshold to transition from a high value to a low value, V4 is asserted to a high value and transistor 618 turns on, as described above, and the gate of buffer transistor 602 is pulled down to ground potential. Similarly, in response to transistor 624 turning off, V1 is pulled up to a high value through resistor 626, thus causing V2 to have a low value and transistor 620 to turn off.

[0034] Figure 7 is a timing diagram 700 of signals in a buffer circuit according to various examples. In some examples, diagram 700 represents signals that can be provided in the Figure 6 buffer circuit 114. Diagram 700 includes SW, Vtrg, V1, V2, V3, V4, and V5, as well as the resistance (Rg) of buffer resistor 604 seen at the gate of buffer transistor 602.

[0035] As shown in diagram 700 and as described above with respect to Figure 6As described, in response to an increase in the value of SW, the values of V3 and V5 increase. In response to the value of SW increasing to exceed Vtrg at time t1, V4 is de-asserted. In response to the de-assertion of V4, the gate of buffer transistor 602 is regarded as a high-impedance floating node. In response to a further increase in the value of SW, at time t2, V1 is de-asserted and V2 is asserted. Also at time t2, buffer transistor 602 turns on to sink the current of SW to ground terminal 120. In response to the value of SW decreasing and V5 discharging and decreasing to a low value as described above, V3 starts to discharge. In response to the assertion of V2, transistor 620 becomes conductive, absorbing current from the gate of buffer transistor 602 through buffer resistor 604 and transistor 620 until the time when buffer transistor 602 and transistor 624 turn off, thereby causing V1 to be asserted and V2 to be de-asserted at time t3. In response to the de-assertion of V2, transistor 620 turns off. Also at t3, in response to V3 discharging to a value less than the threshold value for a low value, V4 is asserted to a high value. In response to the assertion of V4, transistor 618 turns on, thereby holding the gate of buffer transistor 602 at the ground potential, as described above regarding Figure 6 described.

[0036] Figure 8 is a timing diagram 800 of signals in a system according to various examples. In some examples, diagram 800 represents signals in system 100, including signal 802 of the SW voltage over time for a system including a buffer circuit (e.g., buffer circuit 114) based on the teachings of this specification, signal 804 of the SW voltage over time for a system including a buffer circuit not according to the teachings of this specification, and signal 806 of the SW voltage over time for a system without a buffer circuit. In diagram 800, the vertical axis represents voltage in volts (V) and the horizontal axis represents time in nanoseconds (ns).

[0037] As shown by comparing signals 804, 806 with signal 802, the amplitude of SW is reduced by implementing a buffer circuit coupled to switch node 118. As shown by comparing signal 804 with signal 806, buffer circuit 114 according to this specification has a faster transition rate than other buffer circuit architectures and reduces the amplitude of SW faster than other buffer circuit architectures.

[0038] In this specification, the term "coupled" may cover connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through intermediate component C such that device B is controlled by device A via the control signal provided by device A.

[0039] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer to perform the function at the time of manufacture, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed by firmware and / or software programming of the device, by the construction and / or layout of the hardware components and interconnects of the device, or by a combination thereof.

[0040] A circuit or device described herein as including certain components may alternatively be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0041] Although certain components may be described herein as belonging to a particular process technology, these components may be swapped with components of other process technologies. The circuits described herein may be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0042] The use of the phrase "ground voltage potential" in the foregoing description encompasses chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximate", or "substantially" preceding a parameter means + / - 10% of said parameter. Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. A device, comprising: A first transistor having a first control terminal, wherein the first transistor is coupled between a power terminal and a ground terminal; A second transistor having a second control terminal, wherein the second transistor is coupled between the first control terminal and the ground terminal; A resistor; A third transistor having a third control terminal, wherein the third transistor is coupled between the resistor and the ground terminal, and the resistor is coupled between the first control terminal and the third transistor; And A circuit system having a first input, a second input, a first output, and a second output, wherein the first input is coupled to the power terminal, the second input is coupled to the first control terminal, the first output is coupled to the second control terminal, and the second output is coupled to the third control terminal.

2. The device according to claim 1, wherein the circuit system comprises a third input and a fourth input, wherein the third input is a target voltage input, and the fourth input is a bias current input.

3. The device according to claim 2, wherein the circuit system comprises: A first comparator having a first comparator output, a first comparator input, and a second comparator input, wherein the first comparator input is coupled to the power terminal, and the second comparator input is coupled to the third input; A second comparator having a second comparator output, a third comparator input, and a fourth comparator input, wherein the third comparator input is coupled to the first control terminal, and the fourth comparator input is coupled to the fourth input; And A control circuit system having a control circuit system output, a first control circuit system input, and a second control circuit system input, wherein the first control circuit system input is coupled to the first comparator output, the second control circuit system input is coupled to the second comparator output, and the control circuit system output is coupled to the second control terminal.

4. The device according to claim 3, wherein the circuit system is configured to: Couple the first control terminal to the ground terminal through the second transistor during a first time period; and Couple the first control terminal to the ground terminal through the resistor and the third transistor during a second time period.

5. The device according to claim 4, wherein in order to couple the first control terminal to the ground terminal during the first time period, the circuit system is configured to: Compare a switching voltage provided at the power terminal with a target voltage provided at the target voltage input to provide a first comparison result; Compare a current provided at the first control terminal with a bias current provided at the bias current input to provide a second comparison result; And Control the first transistor to couple the first control terminal to the ground terminal in response to the first comparison result having an asserted value and the second comparison result having a de-asserted value.

6. The apparatus according to claim 4, wherein to couple the first control terminal to the ground terminal during the second time period, the circuitry is configured to: Compare the switching voltage provided at the power terminal with the target voltage provided at the target voltage input to provide a first comparison result; Compare the current provided at the first control terminal with the bias current provided at the bias current input to provide a second comparison result; And In response to the second comparison result having an asserted value, control the third transistor to couple the first control terminal to the ground terminal through the resistor.

7. The apparatus according to claim 6, wherein in response to the second comparison result having the asserted value, the control circuitry is configured to provide a de-assert signal at the second control terminal.

8. The apparatus according to claim 1, wherein the circuitry comprises: A fourth transistor having a fourth control terminal, wherein the fourth transistor is coupled between the power terminal and a first node, and the fourth control terminal is coupled to a voltage supply terminal; A control circuitry having a control circuitry output and first, second, and third control circuitry inputs, wherein the first and second control circuitry inputs are coupled to the first node; A first logic circuit having a first logic output and first and second logic inputs, wherein the first logic input is coupled to the first node, the second logic input is coupled to the control circuitry output, and the first logic output is coupled to the second control terminal; A fifth transistor having a fifth control terminal, wherein the fifth control terminal is coupled to the first control terminal, and the fifth transistor is coupled between a bias current source and the ground terminal; And A second logic circuit having a third logic input and a second logic output, wherein the third logic input is coupled to the bias current source and the third control circuitry input, and the second logic output is coupled to the third control terminal.

9. The apparatus according to claim 8, wherein the control circuitry is a latch, wherein the first control circuitry input is a reset input, the second control circuitry input is a data input, the third control circuitry input is a clock input, and the control circuitry output is an inverted data output.

10. The apparatus according to claim 8, wherein the first logic circuit is a NAND logic circuit.

11. The apparatus according to claim 8, wherein the second logic circuit is an inverter.

12. The apparatus according to claim 8, wherein the circuitry comprises the bias current source, and the bias current source is coupled between the voltage supply terminal and the fifth transistor.

13. The apparatus according to claim 8, wherein the circuitry is configured to: During a first time period, couple the first control terminal to the ground terminal via the second transistor; and During a second time period, couple the first control terminal to the ground terminal via the resistor and the third transistor.

14. An apparatus comprising: A transistor having a control terminal, wherein the transistor is coupled between a power terminal and a ground terminal; A resistor; And A controller having a first controller input, a second controller input, a first controller output, and a second controller output, wherein the first controller input is coupled to the power terminal, the second controller input is coupled to the control terminal, the first controller output is coupled to the control terminal, and the resistor is coupled between the control terminal and the second controller output.

15. The apparatus of claim 14, wherein the controller is configured to: Couple the control terminal to the ground terminal during a first time period; and Couple the control terminal to the ground terminal via the resistor during a second time period.

16. The apparatus of claim 15, wherein the controller is configured to: Compare a switching voltage provided at the power terminal with a target voltage to provide a first comparison result; Compare a current provided at the control terminal with a bias current to provide a second comparison result; In response to the first comparison result having an asserted value and the second comparison result having a de-asserted value, couple the control terminal to the ground terminal; And In response to the second comparison result having an asserted value, couple the control terminal to the ground terminal via the resistor.

17. A system comprising: A switching regulator having a regulator input and a switching node, the regulator input being coupled to a supply voltage terminal; And A buffer circuit coupled to the switching node, the buffer circuit comprising: A first transistor having a first control terminal, wherein the first transistor is coupled between a power terminal and a ground terminal; A resistor; And A buffer controller comprising: A second transistor having a second control terminal, wherein the second transistor is coupled between the first control terminal and the ground terminal; A third transistor having a third control terminal, wherein the third transistor is coupled between the resistor and the ground terminal, and the resistor is coupled between the first control terminal and the third transistor; And A circuitry having a first input, a second input, a first output, and a second output, wherein the first input is coupled to the power terminal, the second input is coupled to the first control terminal, the first output is coupled to the second control terminal, and the second output is coupled to the third control terminal.

18. The system of claim 17, wherein the circuitry of the buffer controller comprises: A first comparator having a first comparator output, and a first comparator input and a second comparator input, wherein the first comparator input is coupled to the power terminal, and the second comparator input is coupled to a target voltage input; A second comparator having a second comparator output, and a third comparator input and a fourth comparator input, wherein the third comparator input is coupled to the first control terminal, and the fourth comparator input is coupled to a bias current input; And A control circuit system having a control circuit system output, and a first control circuit system input and a second control circuit system input, wherein the first control circuit system input is coupled to the first comparator output, the second control circuit system input is coupled to the second comparator output, and the control circuit system output is coupled to the second control terminal.

19. The system of claim 17, wherein the circuitry of the buffer controller comprises: A fourth transistor having a fourth control terminal, wherein the fourth transistor is coupled between the power terminal and a first node, and the fourth control terminal is coupled to a voltage supply terminal; A control circuit system having a control circuit system output, and a first control circuit system input, a second control circuit system input, and a third control circuit system input, wherein the first control circuit system input and the second control circuit system input are coupled to the first node; A first logic circuit having a first logic output, and a first logic input and a second logic input, wherein the first logic input is coupled to the first node, the second logic input is coupled to the control circuit system output, and the first logic output is coupled to the second control terminal; A fifth transistor having a fifth control terminal, wherein the fifth control terminal is coupled to the first control terminal, and the fifth transistor is coupled between the bias current input and the ground terminal; And A second logic circuit having a third logic input and a second logic output, the third logic input being coupled to the bias current input and the third control circuit system input, and the second logic output being coupled to the third control terminal.

20. The system of claim 17, wherein the circuitry of the buffer controller is configured to: Couple the first control terminal to the ground terminal through the second transistor during a first time period; and Couple the first control terminal to the ground terminal through the resistor and the third transistor during a second time period.

Images