UFS chip testing device and UFS chip testing system

Abstract

The invention discloses a UFS chip testing device and a UFS chip testing system. The UFS chip testing device comprises a first circuit board; the first high-speed connector is arranged on the first circuit board, and the first high-speed connector is configured to send or receive an MIPI signal; and the UFS chip is arranged on the first circuit board and is connected with the first high-speed connector. Through the above mode, the UFS chip is connected through the high-speed connector and the high-speed line, so that long-distance high-speed transmission of the MIPI signal is realized, and high and low temperature tests of the UFS chip and UFS protocol analysis under the high and low temperature tests are facilitated.

Description

Technical Field

[0001] This application relates to the technical field of chip testing, and particularly relates to a UFS chip testing device and a UFS chip testing system. Background Art

[0002] UFS (Universal Flash Storage) is a universal flash storage standard, and its design goal is to provide higher performance and lower power consumption. UFS is superior to eMMC in terms of continuous read and write speed, random read and write speed, and energy efficiency.

[0003] When testing a UFS chip, it is generally necessary to place the UFS chip to be tested in an operating environment. For example, it is necessary to install the UFS chip to be tested on a platform board to be tested. Taking a mobile phone UFS chip as an example, it is necessary to install the chip to be tested on the mobile phone board to be tested.

[0004] Currently, when it is necessary to connect the UFS MIPI signal to a protocol analyzer on a platform board to analyze the UFS protocol, due to board space limitations and signal integrity issues, it is inconvenient to use the protocol analyzer. In addition, when the UFS chip is tested and analyzed in a high-temperature or low-temperature environment, the operating temperature supported by the protocol analyzer probe is not high. Therefore, it is necessary to separate the UFS chip from the UFS platform board to be tested and extend the UFS MIPI signal for a certain distance. Since the UFS MIPI signal is a high-speed signal, if the distance is too long, the signal loss will be too large and the UFS will not work properly. If the extended distance is too short, it cannot meet the requirements of protocol analysis in the high and low temperature chamber test environment. Summary of the Invention

[0005] To solve the above problems, this application provides a UFS chip testing device, which can realize long-distance high-speed transmission of MIPI signals, facilitate high and low temperature testing of UFS chips and UFS protocol analysis under high and low temperature testing.

[0006] One technical solution adopted by this application is: to provide a UFS chip testing device. In one embodiment, the UFS chip testing device includes: a first circuit board; a first high-speed connector disposed on the first circuit board, and the first high-speed connector is configured to send or receive MIPI signals; a UFS chip disposed on the first circuit board and connected to the first high-speed connector.

[0007] In another embodiment, the UFS chip testing device includes: a first circuit board; a first high-speed connector disposed on the first circuit board; a UFS chip disposed on the first circuit board and connected to the first high-speed connector; a second circuit board; a second high-speed connector disposed on the second circuit board, and the first high-speed connector is connected to the second high-speed connector through a high-speed line; wherein, the second circuit board is used to be mounted on a platform circuit board so that the second high-speed connector is connected to a host chip on the platform circuit board, and the first high-speed connector, the second high-speed connector and the UFS chip form a transmission channel for MIPI signals.

[0008] In one embodiment, a first resistor matching module is disposed on the first circuit board, and the first high-speed connector, the first resistor matching module and the UFS chip are connected in sequence, and the first high-speed connector, the first resistor matching module and the UFS chip form a transmission channel for MIPI signals.

[0009] In one embodiment, the first high-speed connector is connected to an external second high-speed connector to send or receive MIPI signals, and the UFS chip is connected to the second high-speed connector; wherein, the first high-speed connector, the second high-speed connector and the UFS chip form a transmission channel for clock signals and reset signals, and the second high-speed connector and the UFS chip form a transmission channel for power supply signals.

[0010] In one embodiment, conductive contacts are disposed on the first circuit board, and the conductive contacts are connected to the second high-speed connector and the UFS chip.

[0011] In one embodiment, the first resistor matching module is connected to the first high-speed connector through 4 pairs of differential signal lines, and is connected to the UFS chip through 4 pairs of differential signal lines. The first resistor matching module includes 8 first resistor units, and each first resistor unit is connected to the first high-speed connector through 1 differential signal line and is connected to the UFS chip through 1 differential signal line.

[0012] In one embodiment, the first resistor unit includes a first resistor and a second resistor. The first end of the first resistor is connected to the first high-speed connector through 1 differential signal line, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the UFS chip through 1 differential signal line.

[0013] In one embodiment, a second resistor matching module and a first SMP connector are disposed on the first circuit board.

[0014] In one embodiment, the first high-speed connector, the second resistor matching module and the UFS chip are connected in sequence, and the first high-speed connector, the second resistor matching module and the UFS chip form a transmission channel for MIPI signals.

[0015] In one embodiment, a first SMP connector is connected to a second resistor matching module. The first SMP connector is configured to be connected to an external UFS protocol analyzer, and the UFS protocol analyzer is configured to obtain a MIPI signal from the first SMP connector to perform UFS protocol analysis on the MIPI signal.

[0016] In one embodiment, the second resistor matching module is connected to a first high-speed connector through 4 pairs of differential signal lines, connected to a UFS chip through 4 pairs of differential signal lines, and connected to the first SMP connector through 4 pairs of differential signal lines. The second resistor matching module includes 8 second resistor units, and each second resistor unit is connected to the first high-speed connector through 1 differential signal line, connected to the UFS chip through 1 differential signal line, and connected to the first SMP connector through 1 differential signal line.

[0017] In one embodiment, the second resistor unit includes a third resistor, a fourth resistor, and a fifth resistor. The first end of the third resistor is connected to the first high-speed connector through 1 differential signal line. The second end of the third resistor is connected to the first ends of the fourth resistor and the fifth resistor. The second end of the fourth resistor is connected to the UFS chip through 1 differential signal line. The second end of the fifth resistor is connected to the first SMP connector through 1 differential signal line.

[0018] In one embodiment, the UFS chip test device further includes a third circuit board. A third high-speed connector, a third resistor matching module, and a fourth high-speed connector are sequentially disposed on the third circuit board. The third high-speed connector is configured to transmit or receive a MIPI signal, and the fourth high-speed connector is connected to the first high-speed connector through a high-speed line.

[0019] In one embodiment, the third high-speed connector, the third resistor matching module, the fourth high-speed connector, the first high-speed connector, and the UFS chip form a transmission channel for the MIPI signal.

[0020] In one embodiment, a second SMP connector is further disposed on the third circuit board. The second SMP connector is connected to the third resistor matching module. The second SMP connector is configured to be connected to an external UFS protocol analyzer, and the UFS protocol analyzer is configured to obtain a MIPI signal from the second SMP connector to perform UFS protocol analysis on the MIPI signal.

[0021] The present application further provides a chip test system, which includes the platform circuit board and the UFS chip test device as described above.

[0022] The UFS chip testing device provided by this application includes: a first circuit board; a first high-speed connector disposed on the first circuit board, the first high-speed connector being configured to transmit or receive MIPI signals; a UFS chip disposed on the first circuit board and connected to the first high-speed connector. In this way, the UFS chip is connected through a high-speed connector and a high-speed line. Compared with the traditional FPC connection method between circuit boards, it not only realizes the long-distance high-speed transmission of MIPI signals, but also adopts the signal transmission method of high-speed connectors and high-speed lines, greatly reducing the requirements for the test environment, facilitating placing the platform circuit board or the first circuit board in any required test environment, and facilitating the realization of high and low temperature tests of the UFS chip and UFS protocol analysis under high and low temperature tests. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required for description in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0024] Among them:

[0025] Figure 1 is a schematic structural diagram of the first embodiment of the UFS chip testing device provided by this application;

[0026] Figure 2 is a schematic structural diagram of the second embodiment of the UFS chip testing device provided by this application;

[0027] Figure 3 is a schematic structural diagram of the third embodiment of the UFS chip testing device provided by this application;

[0028] Figure 4 is a schematic structural diagram of the fourth embodiment of the UFS chip testing device provided by this application;

[0029] Figure 5 is a schematic structural diagram of the fifth embodiment of the UFS chip testing device provided by this application;

[0030] Figure 6 is a schematic structural diagram of an embodiment of the UFS chip testing system provided by this application. Detailed Embodiments

[0031] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. Additionally, it should be noted that for the sake of description, only parts related to the present application rather than all structures are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0032] The terms "first", "second", etc. in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0033] Referring to "embodiment" in this context means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0034] Refer to Figure 1 , Figure 1 is a schematic structural diagram of the first embodiment of the UFS chip test device provided by the present application. The UFS chip test device 1000 includes a first circuit board 100, a first high-speed connector 110, and a UFS chip.

[0035] Among them, the first high-speed connector 110 is disposed on the first circuit board 100, and the first high-speed connector 110 is configured to send or receive MIPI signals; the UFS chip is disposed on the first circuit board 100 and is connected to the first high-speed connector 110.

[0036] Among them, the UFS chip is a flash memory chip, a storage protocol based on serial communication, and a device for storing data. The MIPI signal is a high-speed, low-power serial communication protocol. The UFS chip uses the MIPI protocol as the communication protocol when transmitting data to achieve fast and stable data transmission.

[0037] Optionally, the circuit board used for the first circuit board 100 is a PCB board, which is used for soldering high-speed connectors, SMP connectors, UFS chips, etc.

[0038] Optionally, the high-speed connector adopted by the first high-speed connector 110 is used to connect the UFS chip and transmit data. Its transmission rate is faster than that of ordinary connectors, and it can ensure the stability and reliability of data transmission, such as UFS connectors, Fakra connectors, etc. High-speed connectors are generally connected by high-speed lines. A high-speed line is a line used for high-speed data transmission and can be used for the transmission of high-speed signals such as MIPI. The high-speed line has high stability and reliability, can ensure the stability and integrity of data transmission, and also has good anti-interference ability, which can reduce the impact of external interference on data transmission. Therefore, the environmental requirements for the UFS to perform high and low temperature tests can be reduced, and long-distance transmission of MIPI signals can be achieved.

[0039] It can be understood that the high-speed connector receives and sends MIPI signals, and can transmit the MIPI signals to the UFS chip quickly, stably and with low loss, so that the UFS chip can complete the test based on the MIPI signals. At the same time, the protocol analyzer can also capture stable MIPI signals for UFS protocol analysis.

[0040] Specifically, the MIPI high-speed signal, clock signal and reset signal are transmitted to the first high-speed connector 110 through the high-speed line, and then the first high-speed connector 110 transmits the MIPI high-speed signal to the UFS chip to realize the high and low temperature chamber test or UFS protocol analysis of the UFS chip.

[0041] In one embodiment, the high-speed line can be an ultra-low skew twinaxial cable for the transmission of MIPI signals, and the signal link loss can be adjusted by replacing high-speed lines of different lengths. In other embodiments, the high-speed line can also be other cables with lower loss and can support signal extension to a longer length.

[0042] The UFS chip test device provided in this embodiment includes: a first circuit board; a first high-speed connector disposed on the first circuit board, and the first high-speed connector is configured to send or receive MIPI signals; a UFS chip disposed on the first circuit board and connected to the first high-speed connector. In the above manner, the UFS chip is connected through the high-speed connector and the high-speed line. Compared with the traditional FPC flexible board connection method between circuit boards, not only the long-distance high-speed transmission of MIPI signals is realized, but also the signal transmission method using the high-speed connector and the high-speed line greatly reduces the requirements for the test environment, facilitates placing the first circuit board in any required test environment, and facilitates the realization of the high and low temperature test of the UFS chip and the UFS protocol analysis under high and low temperature tests.

[0043] Refer to Figure 2 , Figure 2It is a schematic structural diagram of the second embodiment of the UFS chip testing device provided by this application. The UFS chip testing device 1000 includes a first circuit board 100, a first high-speed connector 110, and a UFS chip.

[0044] Among them, the first high-speed connector 110 is disposed on the first circuit board 100, and the first high-speed connector 110 is configured to transmit or receive MIPI signals; the UFS chip is disposed on the first circuit board 100 and is connected to the first high-speed connector 110.

[0045] Figure 2 The shown UFS chip testing device 1000 and Figure 1 The main difference between the shown UFS chip testing device 1000 is that a first resistor matching module 120 is added. Therefore, the first resistor matching module 120 will be mainly described below. For other components in the UFS chip testing device 1000, please refer to Figure 1 the relevant descriptions of the shown embodiments, such as Figure 2 the first high-speed connector 110 in Figure 1 can refer to the description of the first high-speed connector 110 in

[0046] Optionally, a first resistor matching module 120 is disposed on the first circuit board 100. The first high-speed connector 110, the first resistor matching module 120, and the UFS chip are connected in sequence. The first high-speed connector 110, the first resistor matching module 120, and the UFS chip form a transmission channel for MIPI signals.

[0047] Among them, the function of the resistor matching module is to adjust the impedance of the signal to match the impedance of the transmission path, thereby reducing signal reflection and distortion. The transmission of MIPI signals requires passing through multiple chips and circuits, so the impedance of MIPI signals will change. If the impedance of the MIPI signal does not match the transmission path, it will cause signal reflection and distortion, thus affecting the transmission quality and stability of the signal. By adding a resistor matching module, it can ensure more stable and reliable signal transmission between the high-speed connector and the UFS chip.

[0048] Specifically, the first resistor matching module 120 is connected to the first high-speed connector 110 through 4 pairs of differential signal lines (not shown in the figure), and is connected to the UFS chip through 4 pairs of differential signal lines (not shown in the figure). The first resistor matching module 120 includes 8 first resistor units 221 (only one first resistor unit is shown in the figure). Each first resistor unit 221 is connected to the first high-speed connector 110 through 1 differential signal line and is connected to the UFS chip through 1 differential signal line.

[0049] Optionally, the first resistor unit 121 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the first high-speed connector 110 through one differential signal line, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the UFS chip through one differential signal line.

[0050] Optionally, the first high-speed connector 110 is connected to an external second high-speed connector to transmit or receive MIPI signals. The UFS chip is connected to the second high-speed connector. Among them, the first high-speed connector 110, the second high-speed connector, and the UFS chip form a transmission channel for clock signals and reset signals, and the second high-speed connector and the UFS chip form a transmission channel for power signals.

[0051] In one embodiment, the second high-speed connector can be a high-density double-row pin high-speed connector with a size of 7.21mm * 12.46mm and a pin pitch of 0.635mm. The differential impedance of the second high-speed connector is designed to be 100 ohms, matching the 100-ohm impedance of the high-speed line.

[0052] Optionally, conductive contacts are provided on the first circuit board 100, and the conductive contacts are connected to the second high-speed connector and the UFS chip.

[0053] Specifically, the power signal is transmitted to the UFS chip through the conductive contacts. The second high-speed connector is provided with differential signal pins for the transmission of MIPI high-speed signals, clock signals, and reset signals. The first resistor matching module 120 is used for impedance matching of the MIPI signals transmitted between the high-speed line and the UFS chip to reduce the loss of MIPI signals during high-speed transmission and realize the testing of the UFS chip in high and low temperature environments.

[0054] In one embodiment, the second high-speed connector is provided with 8 pairs of differential signal pins. Among them, 4 pairs of differential signal pins are used for connecting MIPI high-speed signals, 1 pair of differential signal pins is used for connecting the clock signal and the ground signal, 1 pair of differential signal pins is used for connecting the reset signal and the ground signal, and the remaining 2 pairs of differential signal pins are not connected to signals or grounded. The clock signal and the reset signal of the UFS chip are connected through the traces on the circuit board; the first resistor R1 and the second resistor R2 can be zero-ohm resistors, which can achieve impedance matching without causing obvious loss to the high-speed signals; the conductive contacts can be multiple groups of pin headers. The first end of the pin headers is connected to the external power supply welding point through a power supply jumper wire, and the second end of the pin headers is connected to the UFS chip through the traces on the first circuit board 100 for the transmission of power signals.

[0055] In an application scenario, the second high-speed connector is placed in a normal temperature environment, and the first circuit board 100 is placed in a high and low temperature chamber with a wall thickness of 8 - 10 CM for UFS chip high and low temperature testing. Since the first circuit board and the second high-speed connector are connected by a high-speed line, the high-speed line can be extended to more than 15 CM. At this time, the MIPI signal will not be greatly attenuated. By changing the temperature in the high and low temperature chamber, the UFS chip can be tested at high and low temperatures.

[0056] Refer to Figure 3 , Figure 3 FIG. is a schematic structural diagram of a third embodiment of the UFS chip testing device provided by the present application. The UFS chip testing device 1000 includes a first circuit board 100, a first high-speed connector 110, and a UFS chip.

[0057] Among them, the first high-speed connector 110 is disposed on the first circuit board 100, and the first high-speed connector 110 is configured to transmit or receive MIPI signals; the UFS chip is disposed on the first circuit board 100 and is connected to the first high-speed connector 110.

[0058] Figure 3 The UFS chip testing device 1000 shown in Figure 2 The main difference between the UFS chip testing device 1000 shown in and the UFS chip testing device 1000 is that a second resistor matching module 130 and a first SMP connector are added. Therefore, the second resistor matching module 130 and the first SMP connector will be mainly described below. For other components in the UFS chip testing device 1000, please refer to Figure 2 the relevant description of the embodiment shown in, for example Figure 3 the first resistor matching module 120 in can be referred to Figure 2 the description of the first resistor matching module 120 in, which will not be elaborated here.

[0059] Optionally, a second resistor matching module 130 and a first SMP connector are disposed on the first circuit board 100. The first high-speed connector 110, the second resistor matching module 130, and the UFS chip are connected in sequence. The first high-speed connector 110, the second high-speed connector, the second resistor matching module 130, and the UFS chip form a transmission channel for MIPI signals.

[0060] Among them, the SMP connector is a type of small coaxial connector, which is an improved model of the SMA connector. The SMP connector has a smaller size and a higher frequency bandwidth, is suitable for high-frequency and high-speed digital communication systems, and has a wide temperature operating range. It can work within a wide temperature range and can adapt to the temperature environment during high and low temperature testing of the UFS chip.

[0061] Optionally, the first SMP connector is connected to the second resistor matching module 130. The first SMP connector is configured to be connected to an external UFS protocol analyzer, which is used to obtain MIPI signals from the first SMP connector for UFS protocol analysis of the MIPI signals.

[0062] Optionally, the second resistor matching module 130 is connected to the first high-speed connector 110 through 4 pairs of differential signal lines (not shown in the figure), connected to the UFS chip through 4 pairs of differential signal lines (not shown in the figure), and connected to the first SMP connector through 4 pairs of differential signal lines (not shown in the figure). The second resistor matching module 130 includes 8 second resistor units 231 (only one second resistor unit is shown in the figure). Each second resistor unit 231 is connected to the first high-speed connector 110 through 1 differential signal line, connected to the UFS chip through 1 differential signal line, and connected to the first SMP connector through 1 differential signal line.

[0063] Optionally, the second resistor unit 131 includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first end of the third resistor R3 is connected to the first high-speed connector 110 through 1 differential signal line. The second end of the third resistor R3 is connected to the first ends of the fourth resistor R4 and the fifth resistor R5. The second end of the fourth resistor R4 is connected to the UFS chip through 1 differential signal line. The second end of the fifth resistor R5 is connected to the first SMP connector through 1 differential signal line.

[0064] In one embodiment, the second resistor matching module 130 and the first resistor matching module 120 can be two independent and different resistor matching modules. In another embodiment, the second resistor matching module 130 and the first resistor matching module 120 can also be the same resistor matching module. This resistor matching module can form different resistor matching circuits through means such as switch switching. For example, one end of the first resistor of the resistor matching module is connected to the second resistor, and a single-pole double-throw switch is respectively connected to the connection node of the first resistor and the second resistor and the third resistor. The other end of the first resistor of this resistor matching module is connected to the first high-speed connector 110. By simply switching the switch state of the single-pole double-throw switch, the switching between the second resistor matching module 130 and the first resistor matching module 120 can be achieved.

[0065] Specifically, the second resistor matching module 130 is used for impedance matching of MIPI signals to reduce losses in MIPI signal transmission. The first SMP connector is used to connect to an external protocol analyzer, which is used to capture MIPI signals of the MIPI link and transmit them to the protocol analyzer, enabling UFS protocol analysis when the UFS chip is tested in high and low temperature environments, or UFS protocol analysis when the UFS is placed in a normal temperature environment.

[0066] Refer toFigure 4 , Figure 4 is a schematic structural diagram of the fourth embodiment of the UFS chip test device provided by this application. The UFS chip test device 1000 includes a first circuit board 100, a first high-speed connector 110, and a UFS chip.

[0067] Among them, the first high-speed connector 110 is disposed on the first circuit board 100, and the first high-speed connector 110 is configured to transmit or receive MIPI signals; the UFS chip is disposed on the first circuit board 100 and is connected to the first high-speed connector 110.

[0068] Figure 4 The shown UFS chip test device 1000 and Figure 3 The main difference between the shown UFS chip test device 1000 is that a third circuit board 300 is added. Therefore, the third circuit board 300 will be mainly described below. For other components in the UFS chip test device 1000, please refer to Figure 3 the relevant descriptions of the shown embodiments, such as Figure 4 the second resistor matching module 130 in Figure 3 the description of the second resistor matching module 130, which will not be elaborated here.

[0069] Optionally, the UFS chip test device 1000 further includes a third circuit board 300. A third high-speed connector 310, a third resistor matching module 320, and a fourth high-speed connector 330 are sequentially disposed on the third circuit board 300. The third high-speed connector 310 is connected to the second high-speed connector through a high-speed line, and the fourth high-speed connector 330 is connected to the first high-speed connector 110 through a high-speed line.

[0070] Optionally, the first high-speed connector 110, the third high-speed connector 310, the third resistor matching module 320, the fourth high-speed connector 330, the second high-speed connector, and the UFS chip form a transmission channel for MIPI signals.

[0071] Optionally, a second SMP connector is further disposed on the third circuit board 300. The second SMP connector is connected to the third resistor matching module 320. The second SMP connector is configured to connect to an external UFS protocol analyzer, and the UFS protocol analyzer is used to obtain MIPI signals from the second SMP connector to perform UFS protocol analysis on the MIPI signals.

[0072] Specifically, data containing MIPI signals is transmitted to the second high-speed connector. The second high-speed connector transmits MIPI high-speed signals, clock signals, and reset signals to the third high-speed connector 310 through high-speed lines. The third high-speed connector 310 transmits the clock signal and the reset signal to the fourth high-speed connector 330. After the MIPI high-speed signal is impedance-matched through the third resistor matching module 320, the fourth high-speed connector 330 transmits the MIPI high-speed signal, the clock signal, and the reset signal to the first high-speed connector 110. The first high-speed connector 110 transmits the clock signal and the reset signal to the UFS chip. The MIPI high-speed signal is transmitted to the UFS chip after passing through the first resistor matching module 120, realizing the high and low temperature chamber test of the UFS chip or the UFS protocol analysis.

[0073] In one embodiment, the third resistor matching module 320 and the second resistor matching module 130 can be two independent and identical resistor matching modules. The third circuit board 300 can be placed outside the temperature chamber and connected to a protocol analyzer, which is more convenient for protocol analysis during high and low temperature chamber tests.

[0074] Refer to Figure 5 , Figure 5 FIG. is a schematic structural diagram of the fifth embodiment of the UFS chip test device provided by the present application. The UFS chip test device 1000 includes a first circuit board 100, a first high-speed connector 110, a UFS chip, a second circuit board 200, and a second high-speed connector 210.

[0075] Among them, the first high-speed connector 110 is arranged on the first circuit board 100; the UFS chip is arranged on the first circuit board 100 and is connected to the first high-speed connector 110; the second high-speed connector 210 is arranged on the second circuit board 200, and the first high-speed connector 110 is connected to the second high-speed connector 210 through a high-speed line; among them, the second circuit board 200 is used to be installed on the platform circuit board so that the second high-speed connector 210 is connected to the host chip on the platform circuit board, and the first high-speed connector 110, the second high-speed connector 210, and the UFS chip form a transmission channel for MIPI signals.

[0076] Among them, the platform circuit board refers to a PCB board used for UFS testing and verification. The PCB board can be installed with UFS modules, processors, etc., such as a mobile phone board. In other embodiments, the platform circuit board can be other board cards with data transmission and communication capabilities.

[0077] Among them, the host chip is a chip used to connect to the UFS storage device. It acts as an interface between the host and the UFS storage device, has high-speed data transmission capabilities, and can achieve fast data transmission with the UFS storage device.

[0078] Specifically, the host chip is used to manage the data transmission and connection of the UFS chip, and at the same time provide sufficient current or voltage to drive the second high-speed connector 210 to work properly. The second high-speed connector 210 transmits MIPI high-speed signals, clock signals and reset signals to the first high-speed connector 110 through high-speed lines, and then the first high-speed connector 110 transmits the MIPI high-speed signals to the UFS chip to implement high and low temperature chamber testing or UFS protocol analysis of the UFS chip.

[0079] When the UFS chip test device of this embodiment is applied to a UFS chip test system, it is connected to the UFS chip through high-speed connectors and high-speed lines, which not only realizes the long-distance high-speed transmission of MIPI signals, but also adopts the signal transmission method of high-speed connectors and high-speed lines, greatly reducing the requirements for the test environment, facilitating placing the first circuit board in any required test environment, and facilitating the implementation of high and low temperature testing of the UFS chip and UFS protocol analysis under high and low temperature testing.

[0080] Refer to Figure 6 , Figure 6 is a schematic structural diagram of an embodiment of a UFS chip test system provided by this application. The UFS chip test system includes a platform circuit board 2000 and a UFS chip test device 1000.

[0081] Among them, a host chip is provided on the platform circuit board 2000; the UFS chip test device 1000 is as described in the above embodiment and will not be elaborated here.

[0082] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A UFS chip testing device, characterized in that, The UFS chip testing device includes: A first circuit board; A first high-speed connector disposed on the first circuit board, the first high-speed connector being configured to transmit or receive MIPI signals; A UFS chip disposed on the first circuit board and connected to the first high-speed connector.

2. The UFS chip testing device according to claim 1, characterized in that, A first resistor matching module is disposed on the first circuit board, and the first high-speed connector, the first resistor matching module, and the UFS chip are connected in sequence, and the first high-speed connector, the first resistor matching module, and the UFS chip form a transmission channel for MIPI signals.

3. The UFS chip testing device according to claim 2, wherein The first high-speed connector is connected to an external second high-speed connector to transmit or receive MIPI signals, and the UFS chip is connected to the second high-speed connector; Wherein, the first high-speed connector, the second high-speed connector, and the UFS chip form a transmission channel for clock signals and reset signals, and the second high-speed connector and the UFS chip form a transmission channel for power supply signals.

4. The UFS chip testing device according to claim 3, wherein, Conductive contacts are disposed on the first circuit board, and the conductive contacts are connected to the second high-speed connector and the UFS chip.

5. The UFS chip testing device according to claim 2, wherein The first resistor matching module is connected to the first high-speed connector through 4 pairs of differential signal lines, and is connected to the UFS chip through 4 pairs of differential signal lines. The first resistor matching module includes 8 first resistor units, and each first resistor unit is connected to the first high-speed connector through 1 differential signal line, and is connected to the UFS chip through 1 differential signal line; The first resistor unit includes a first resistor and a second resistor. The first end of the first resistor is connected to the first high-speed connector through 1 differential signal line, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the UFS chip through 1 differential signal line.

6. The UFS chip testing device according to claim 1, wherein A second resistor matching module and a first SMP connector are disposed on the first circuit board; The first high-speed connector, the second resistor matching module, and the UFS chip are connected in sequence, and the first high-speed connector, the second resistor matching module, and the UFS chip form a transmission channel for MIPI signals; The first SMP connector is connected to the second resistor matching module, and the first SMP connector is configured to be connected to an external UFS protocol analyzer, and the UFS protocol analyzer is used to obtain MIPI signals from the first SMP connector to perform UFS protocol analysis on the MIPI signals.

7. The UFS chip testing device according to claim 6, wherein, The second resistor matching module is connected to the first high-speed connector through 4 pairs of differential signal lines, is connected to the UFS chip through 4 pairs of differential signal lines, and is connected to the first SMP connector through 4 pairs of differential signal lines. The second resistor matching module includes 8 second resistor units, and each second resistor unit is connected to the first high-speed connector through 1 differential signal line, is connected to the UFS chip through 1 differential signal line, and is connected to the first SMP connector through 1 differential signal line; The second resistor unit includes a third resistor, a fourth resistor, and a fifth resistor. The first end of the third resistor is connected to the first high-speed connector through one differential signal line. The second end of the third resistor is connected to the first end of the fourth resistor and the first end of the fifth resistor. The second end of the fourth resistor is connected to the UFS chip through one differential signal line. The second end of the fifth resistor is connected to the first SMP connector through one differential signal line.

8. The UFS chip testing device according to claim 1, characterized in that, The UFS chip testing device further includes a third circuit board, on which a third high-speed connector, a third resistor matching module, and a fourth high-speed connector are sequentially connected. The third high-speed connector is configured to transmit or receive MIPI signals. The fourth high-speed connector is connected to the first high-speed connector through a high-speed line. Among them, the third high-speed connector, the third resistor matching module, the fourth high-speed connector, the first high-speed connector, and the UFS chip form a transmission channel for MIPI signals.

9. The UFS chip testing device according to claim 8, wherein, A second SMP connector is further provided on the third circuit board. The second SMP connector is connected to the third resistor matching module. The second SMP connector is configured to be connected to an external UFS protocol analyzer, and the UFS protocol analyzer is used to obtain MIPI signals from the second SMP connector to perform UFS protocol analysis on the MIPI signals.

10. A UFS chip testing device, characterized in that, The UFS chip testing device includes: A first circuit board; A first high-speed connector, provided on the first circuit board; A UFS chip, provided on the first circuit board and connected to the first high-speed connector; A second circuit board; A second high-speed connector, provided on the second circuit board. The first high-speed connector is connected to the second high-speed connector through a high-speed line. Among them, the second circuit board is used to be installed on the platform circuit board so that the second high-speed connector is connected to the host chip on the platform circuit board. The first high-speed connector, the second high-speed connector, and the UFS chip form a transmission channel for MIPI signals.

11. A UFS chip testing system, characterized in that, The UFS chip testing system includes: A platform circuit board, on which a host chip is provided; A UFS chip testing device, where the UFS chip testing device is the UFS chip testing device according to any one of claims 1-10.

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