Maximum power point tracking algorithm circuit for piezoelectric energy collection

Abstract

The invention discloses a maximum power point tracking algorithm circuit for piezoelectric energy collection, which is characterized in that the output end of a piezoelectric energy source is connected with the first signal input end and the second signal input end of a rectifier, and the output end of the rectifier is connected with the input ends of a rectifier conduction time duty ratio detection circuit and a buck-boost impedance matching converter; the output end of the rectifier conduction time duty ratio detection circuit is connected with the input end of the interval approximation algorithm circuit module, the output end of the interval approximation algorithm circuit module is connected with the control end of the buck-boost impedance matching converter, and the input end of the energy storage module is connected with the output end of the buck-boost impedance matching converter. According to the circuit, whether the output of the voltage power supply is at the maximum power point can be judged by judging whether the conduction duty ratio of the rectifier reaches 50%, and the impedance matching circuit is controlled to track the maximum power point through an interval search algorithm.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management for piezoelectric energy harvesting, and relates to a maximum power point tracking algorithm circuit for piezoelectric energy harvesting. Background Art

[0002] With the progress of microelectronic technology, it has promoted the development of today's society towards informatization and intelligence. Technologies such as wireless devices, portable devices, wearable devices, and the Internet of Things have been widely applied and have extended to all aspects of our lives. As time goes by, the application scope of wireless sensor networks (WSNs) is also constantly expanding, such as in the fields of bridge monitoring, biomedical detection, hazard monitoring, and weather stations. These applications not only demonstrate the broad prospects of WSNs but also further drive the rapid growth of the demand for microelectronic systems.

[0003] However, with the widespread application of microelectronic systems, their power supply problems have gradually attracted attention. For a long time, chemical batteries, as a direct and effective power supply method, have been widely used in various electronic devices. However, problems such as insufficient battery life, large volume, and heat generation make chemical batteries face many challenges in practical applications. More seriously, discarded chemical batteries will also cause environmental pollution and pose a threat to ecological safety. Especially in implantable electronic devices, the cumbersome degree and safety risks of battery replacement have become key factors restricting their development. Therefore, finding a safer and more reliable power supply method has become an urgent need.

[0004] In this context, self-powered power technology has emerged. This technology can extract energy from the environment and efficiently convert it into electrical energy to provide a stable and sustainable power supply for microelectronic systems. Compared with traditional chemical batteries, self-powered power has the advantages of a longer service life, no need for frequent replacement, and no pollution. With technological progress, the power consumption of microelectronic systems has been reduced to the micro-watt level, and the feasibility of using environmental energy to power them has been further improved. This way of extracting energy from the environment and converting it into electrical energy not only solves the problems existing in traditional power supply methods but also provides new possibilities for the sustainable development of microelectronic systems.

[0005] Different environmental energies have different characteristics, and there are significant differences in the sources, power densities, and energy source characteristics of these energies. The energy harvesting of heat energy is based on the thermoelectric effect, using temperature differences to generate electrical energy, and a startup circuit is required. This technology is suitable for environments close to the body or with temperature differences. For example, when close to the human body, the energy level is approximately 25 μW / cm 2 or so; while in general industrial environments with temperature differences, the energy level can reach 1 - 10 mW / cm 2However, the main disadvantage of this technology is that the transducer is large in both weight and volume, making it very difficult to miniaturize. There is a large difference in the energy density of photovoltaic energy between indoors and outdoors. The energy density of radio frequency energy is small, the output voltage is low, and the energy that can be collected is weak. The piezoelectric energy converter is small in volume and moderate in power density, making it suitable for energy harvesting applications.

[0006] The research on piezoelectric energy harvesting systems mainly includes piezoelectric conversion devices and energy harvesting circuit systems. The energy harvesting circuit system usually consists of a rectifier and interface circuit, a maximum power point tracking circuit, an impedance matching circuit, and an energy storage module. Since the piezoelectric energy source is a micro energy source, it is necessary to study highly efficient rectifiers and interface circuits. In order to be able to collect the maximum power in real time, the research on the maximum power point tracking circuit is also a key issue.

[0007] Common maximum power point tracking algorithms include: open circuit voltage method, perturbation and observation method (Perturbation and Observation, P&O), and incremental conductance method. Both the perturbation and observation method and the incremental conductance method require real-time calculation of the output power, which means that voltage and current need to be detected, thus having a relatively complex control circuit. The open circuit voltage method has the following limitations. Periodically disconnecting the piezoelectric power source to measure V MPP will cause energy waste, and the inherent delay in sensing the change of V MPP will reduce the overall tracking speed. System parameters such as inductance, parasitic resistance, and capacitance are very likely to affect η F , thus requiring an update of V MPP . Summary of the Invention

[0008] The object of the present invention is to overcome the above-mentioned disadvantages of the prior art and provide a maximum power point tracking algorithm circuit for piezoelectric energy harvesting. This circuit can judge whether the piezoelectric power source output is at the maximum power point by determining whether the duty cycle of the rectifier conduction has reached 50%, and control the impedance matching circuit to perform maximum power point tracking through an interval search algorithm.

[0009] To achieve the above object, the maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to the present invention includes a piezoelectric energy source, a P-SSHI rectifier, a rectifier conduction time duty cycle detection circuit, a buck-boost impedance matching converter, an interval approximation algorithm circuit module, and an energy storage module. Among them, the output end of the piezoelectric energy source is connected to the first signal input end and the second signal input end of the rectifier. The output end of the rectifier is connected to the rectifier conduction time duty cycle detection circuit and the input of the buck-boost impedance matching converter. The output end of the rectifier conduction time duty cycle detection circuit is connected to the input end of the interval approximation algorithm circuit module. The output end of the interval approximation algorithm circuit module is connected to the control end of the buck-boost impedance matching converter. The input end of the energy storage module is connected to the output end of the buck-boost impedance matching converter.

[0010] Further, the rectifier includes a first signal input end, a second signal input end, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first diode, a second diode, a first comparator, a second comparator, a first switch, a first inductor, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a first buffer, a second buffer, a third buffer, a first inverter, a first AND gate, a pre-resistor, a first capacitor, and a second capacitor;

[0011] The first signal input terminal and the second signal input terminal are connected to the output terminal of the piezoelectric energy source. The first signal input terminal is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the first NMOS transistor, the negative electrode of the first diode, one end of the first switch, and the negative input terminal of the first comparator. The second signal input terminal is connected to one end of the first inductor, the drain of the second PMOS transistor, the gate of the first PMOS transistor, the drain of the second NMOS transistor, the negative electrode of the second diode, and the negative input terminal of the second comparator. The source of the first PMOS transistor is connected to the source of the second PMOS transistor and one end of the second capacitor. The other end of the first switch is connected to the other end of the first inductor. The output terminal of the first comparator is connected to the input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the input terminal of the second NAND gate and the input terminal of the first buffer. The output terminal of the second comparator is connected to the input terminal of the second NAND gate. The output terminal of the second NAND gate is connected to the input terminal of the first NAND gate and the input terminal of the second buffer. The output signal terminals of the first buffer and the second buffer are connected to the two input terminals of the third NAND gate. The output terminal of the third NAND gate and the enable signal are connected to the input terminal of the fourth NAND gate. The output terminal of the fourth NAND gate is connected to one end of the pre-resistor and the input terminal of the first AND gate. The other end of the pre-resistor is connected to one end of the first capacitor and the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the first AND gate. The output terminal of the first AND gate is connected to the input of the third buffer. The output terminal of the third buffer generates the signal V SW Control the first switch. The sources of the first NMOS transistor and the second NMOS transistor, the positive electrodes of the first diode and the second diode, the positive input terminals of the first comparator and the second comparator, the other end of the first capacitor, and the other end of the second capacitor are all grounded.

[0012] Further, the rectifier conduction time duty cycle detection circuit includes a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second switch, a third switch, a tenth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a first current source, a second current source, a third current source, a fourth current source, a third signal input terminal, a first signal output terminal, and a second signal output terminal;

[0013] One end of the first current source is connected to one end of the second switch. The other end of the second switch is connected to one end of the third switch and one end of the third capacitor. The other end of the third switch and the other end of the third capacitor are grounded. One end of the second current source is connected to one end of the fourth switch. The other end of the fourth switch is connected to one end of the fifth switch and one end of the fourth capacitor. The other end of the fifth switch and the other end of the fourth capacitor are grounded. One end of the third current source is connected to one end of the sixth switch. The other end of the sixth switch is connected to one end of the seventh switch and one end of the fifth capacitor. The other end of the seventh switch and the other end of the fifth capacitor are grounded. One end of the fourth current source is connected to one end of the eighth switch. The other end of the eighth switch is connected to one end of the ninth switch and one end of the sixth capacitor. The other end of the ninth switch and the other end of the sixth capacitor are grounded;

[0014] The output signal terminal of the first buffer is connected to the control terminals of the third switch, the fifth switch, the seventh switch and the ninth switch;

[0015] The output signal terminal of the second buffer is connected to the control terminal of the eighth switch;

[0016] The third signal input terminal is connected to the control terminals of the second switch, the fourth switch and the sixth switch;

[0017] The first signal output terminal is connected to the line between the second switch and the third switch. The second signal output terminal is connected to the line between the fourth switch and the fifth switch. The first signal output terminal and the second signal output terminal are connected to the interval approximation algorithm circuit module.

[0018] Further, the buck-boost impedance matching converter includes a voltage output terminal, a fourth signal input terminal, a fifth signal input terminal, a first power PMOS transistor, a second power PMOS transistor, a first power NMOS transistor, a second power NMOS transistor, a second inductor, a hysteresis comparator, an oscillator, a dead zone and driver stage, a ZCD circuit, a seventh capacitor, a first resistor, a second resistor and a third resistor;

[0019] The fourth signal input terminal is connected to the left end of the inductor through the first power PMOS transistor. The right end of the second inductor is connected to the voltage output terminal, one end of the seventh capacitor, one end of the first resistor, and one end of the second resistor through the second power PMOS transistor. The left end of the second inductor is connected to the ground through the first power NMOS transistor. The right end of the second inductor is connected to the ground through the second power NMOS transistor. The fifth signal input terminal is connected to the positive input terminal of the hysteresis comparator. The negative input terminal of the hysteresis comparator is connected to the other end of the second resistor and one end of the third resistor. The other end of the third resistor is grounded. The output terminal of the hysteresis comparator is connected to the input terminal of the dead zone and driver stage. The output terminal of the oscillator is connected to the input terminal of the dead zone and driver stage. The output terminal of the dead zone and driver stage is connected to the gates of the first power PMOS transistor, the second power PMOS transistor, the first power NMOS transistor, and the second power NMOS transistor. Both ends of the second power PMOS transistor are connected to the input terminal of the ZCD circuit. The output terminal of the ZCD circuit is connected to the input terminal of the dead zone and driver stage. The voltage output terminal is connected to the energy storage module.

[0020] Further, the interval approximation algorithm circuit module includes a logic control module, a first register, a second register, a first D flip-flop, a first exclusive OR gate, a first multiplexer, a first input signal terminal, a second input signal terminal, and a first output signal terminal;

[0021] The first signal output terminal and the second signal output terminal are connected to the input terminal of the logic control module. The output terminal of the logic control module is connected to the input terminals of the first register and the first D flip-flop. The first input signal terminal and the second input signal terminal are connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop and the second input signal terminal are connected to the input terminal of the first exclusive OR gate. The output terminal of the first exclusive OR gate is connected to the input terminal of the first multiplexer. The output terminal of the first multiplexer is connected to the input terminal of the first register. The first output signal is connected to the input terminal of the second register. The output terminals of the first register and the second register are connected to the input terminal of the first multiplexer. The sum of the output signals of the first register and the second register is divided by 2 as the output signal of the first output signal terminal and is connected to the fourth signal input terminal.

[0022] Further, the energy storage module is a capacitor.

[0023] Further, the energy storage module is a battery.

[0024] Further, it is judged whether it is at the maximum power point by whether the conduction duty cycle of the rectifier has reached 50%, and the interval approximation algorithm control circuit is used for maximum power point tracking.

[0025] The present invention has the following beneficial effects:

[0026] When the maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to the present invention is in specific operation, it determines whether it is at the maximum power point by whether the conduction duty cycle of the rectifier has reached 50%, and adopts the interval approximation algorithm circuit module for maximum power point tracking. The interval approximation algorithm can achieve MPPT through 9 tracking cycles, and the peak MPPT efficiency can reach 98%. The conduction time modulation MPPT algorithm has multiple advantages. It is independent of the open-circuit voltage V OC and the turnover efficiency η F and does not require calibration; the piezoelectric power source and the rectifier are continuously connected, which will not cause energy waste, can achieve continuous and automatic MPPT, and has strong robustness to duty cycle errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings forming a part of this invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0028] Figure 1 is a schematic structural diagram of the present invention;

[0029] Figure 2 is a circuit diagram of the rectifier;

[0030] Figure 3 is a topological diagram of the rectifier conduction time duty cycle detection circuit;

[0031] Figure 4 is a circuit diagram of the buck-boost impedance matching converter;

[0032] Figure 5 is a topological diagram of the interval approximation algorithm circuit module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] In the description of the present invention, it should be understood that the terms "including" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0035] It should also be understood that the terms used in the description of the present invention are merely for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the description of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0036] It should be further understood that the term "and / or" used in the description of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally represents an "or" relationship between the contextually related objects.

[0037] It should be understood that although terms such as first, second, third, etc. may be used in the embodiments of the present invention to describe preset ranges and the like, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0038] Depending on the context, the word "if" as used herein can be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0039] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the present invention described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0040] Various structural schematic diagrams according to the disclosed embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where certain details are enlarged for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0041] Referring to Figure 1 , the maximum power point tracking algorithm circuit based on conduction time modulation for piezoelectric energy harvesting according to the present invention includes a piezoelectric energy source, a P-SSHI rectifier 1, a rectifier conduction time duty cycle detection circuit 2, a buck-boost impedance matching converter 3, an interval approximation algorithm circuit module 4, and an energy storage module 5. Among them, the output end of the piezoelectric energy source is connected to the first signal input terminal V AC1 and the second signal input terminal V AC2 of the rectifier 1. The output end of the rectifier 1 is connected to the rectifier conduction time duty cycle detection circuit 2 and the input of the buck-boost impedance matching converter 3. The output end of the rectifier conduction time duty cycle detection circuit 2 is connected to the input end of the interval approximation algorithm circuit module 4. The output end of the interval approximation algorithm circuit module 4 is connected to the control end of the buck-boost impedance matching converter 3. The input end of the energy storage module 5 is connected to the output end of the buck-boost impedance matching converter 3.

[0042] In order to efficiently convert the AC energy of the voltage source into DC energy, referring to Figure 2 , the rectifier 1 includes a first signal input terminal V AC1 , a second signal input terminal V AC2 , a first PMOS transistor M P1 , a second PMOS transistor M P2 , a first NMOS transistor M N1 , a second NMOS transistor M N2 , a first diode D1, a second diode D2, a first comparator CMP1, a second comparator CMP2, a first switch SW, a first inductor L, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a first buffer Buffer1, a second buffer Buffer2, a third buffer Buffer3, a first inverter INV1, a first AND gate AND1, a pre-resistor R D , a first capacitor C D and a second capacitor C REC ;

[0043] The first signal input terminal V AC1 and the second signal input terminal V AC2 are connected to the output terminal of the piezoelectric energy source. The first signal input terminal V AC1 is connected to the drain of the first PMOS transistor M P1 , the gate of the second PMOS transistor M P2 , the drain of the first NMOS transistor M N1 , the negative electrode of the first diode D1, one end of the first switch SW, and the negative input terminal of the first comparator CMP1. The second signal input terminal V AC2 is connected to one end of the first inductor L, the drain of the second PMOS transistor M P2 , the gate of the first PMOS transistor M P1 , the drain of the second NMOS transistor M N2 , the negative electrode of the second diode D2, and the negative input terminal of the second comparator CMP2. The source of the first PMOS transistor M P1 is connected to the source of the second PMOS transistor M P2 and one end of the second capacitor C REC . The other end of the first switch SW is connected to the other end of the first inductor L. The output terminal of the first comparator CMP1 is connected to the input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the input terminal of the second NAND gate NAND2 and the input terminal of the first buffer Buffer1. The output terminal of the second comparator CMP2 is connected to the input terminal of the second NAND gate NAND2. The output terminal of the second NAND gate NAND2 is connected to the input terminal of the first NAND gate NAND1 and the input terminal of the second buffer Buffer2. The output signal terminal V C1 of the first buffer Buffer1 and the output signal terminal V C2 of the second buffer Buffer2 are connected to the two input terminals of the third NAND gate NAND3. The output terminal of the third NAND gate NAND3 and the enable signal EN are connected to the input terminal of the fourth NAND gate NAND4. The output terminal of the fourth NAND gate NAND4 is connected to one end of the pre-resistor R D and the input terminal of the first AND gate AND1. The other end of the pre-resistor R D is connected to one end of the first capacitor C D and the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 is connected to the input terminal of the first AND gate AND1. The output terminal of the first AND gate AND1 is connected to the input of the third buffer Buffer3. The output terminal of the third buffer Buffer3 generates a signal V SW to control the first switch SW. The source of the first NMOS transistor M N1 is connected to the source of the second NMOS transistor M N2The source electrode, the positive electrode of the first diode D1, the positive electrode of the second diode D2, the positive input terminal of the first comparator CMP1, the positive input terminal of the second comparator CMP2, the other end of the first capacitor C D and the other end of the second capacitor C REC are all grounded.

[0044] In the startup phase, if the output voltage VREC is low and the comparator cannot work properly, the body diodes of the two NMOS transistors and the two PMOS transistors form a passive cross-coupled rectifier at this time. The power loss of the diodes makes the efficiency of the rectifier 1 low at this time. However, the system sets that the operating voltage of the control circuit of the buck-boost impedance matching converter 3 is higher than that of the comparator. Therefore, the buck-boost impedance matching converter 3 does not start working at this time, and there is no energy transfer in the whole circuit. The efficiency of the rectifier 1 does not affect the overall energy transfer efficiency. Such a design does not require adding an additional auxiliary circuit. The rectifier 1 can achieve self-startup and does not affect the system efficiency in the energy transfer phase at the same time.

[0045] To obtain the maximum power transfer, it is necessary to detect the duty cycle of the conduction time of the rectifier 1. Refer to Figure 3 , the rectifier conduction time duty cycle detection circuit 2 includes a third capacitor C H , a fourth capacitor C L , a fifth capacitor C MPP , a sixth capacitor C P , a second switch S1, a third switch S2, a tenth switch S3, a fifth switch S4, a sixth switch S5, a seventh switch S6, an eighth switch S7, a ninth switch S8, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, a third signal input terminal V FAC , a first signal output terminal V MPP_ H and a second signal output terminal V MPP_ L;

[0046] One end of the first current source I1 is connected to one end of the second switch S1. The other end of the second switch S1 is connected to one end of the third switch S2 and one end of the third capacitor C H . The other end of the third switch S2 and the other end of the third capacitor C H are grounded. One end of the second current source I2 is connected to one end of the fourth switch S3. The other end of the fourth switch S3 is connected to one end of the fifth switch S4 and one end of the fourth capacitor C L . The other end of the fifth switch S4 and the other end of the fourth capacitor C L are grounded. One end of the third current source I3 is connected to one end of the sixth switch S5. The other end of the sixth switch S5 is connected to one end of the seventh switch S6 and one end of the fifth capacitor C MPPOne end is connected, and the other end of the seventh switch S6 and the fifth capacitor C MPP The other end is grounded. One end of the fourth current source I4 is connected to one end of the eighth switch S7. The other end of the eighth switch S7 is connected to one end of the ninth switch S8 and the sixth capacitor C P One end is connected, and the other end of the ninth switch S8 and the sixth capacitor C P The other end is grounded; the output signal terminal V of the first buffer Buffer1 C1 Is connected to the control terminals of the third switch S2), the fifth switch S4, the seventh switch S6 and the ninth switch S8; the output signal terminal V of the second buffer Buffer2 C2 Is connected to the control terminal of the eighth switch S7; the third signal input terminal V FAC Is connected to the control terminals of the second switch S1, the fourth switch S3 and the sixth switch S5; the first signal output terminal V MPP_ H is connected to the line between the second switch S1 and the third switch S2, and the second signal output terminal V MPP_ L is connected to the line between the fourth switch S3 and the fifth switch S4, and the first signal output terminal V MPP_ H and the second signal output terminal V MPP_ L is connected to the interval approximation algorithm circuit module 4.

[0047] It includes four parts of duty cycle detection circuits, and the detected duty cycle signals are respectively the real-time conduction duty cycle V of the rectifier 1 PLUS And a signal V with a 50% duty cycle having the same frequency as the voltage source MPP And a signal V with a duty cycle lower than 50% having the same frequency as the voltage source MPP_L And a signal V with a duty cycle higher than 50% having the same frequency as the voltage source MPP_H . Among them, the signal V with a 50% duty cycle having the same frequency as the voltage source MPP Is used to compare with the real-time conduction duty cycle of the rectifier 1 to determine whether it is the maximum power point. The signal V with a duty cycle lower than 50% having the same frequency as the voltage source MPP_L And the signal V with a duty cycle higher than 50% having the same frequency as the voltage source MPP_H Are used to form a window. Once the duty cycle signal V of the real-time conduction time of the rectifier 1 is detected PLUS Is greater than or less than 50%, and after jumping out of the designed interval range, the algorithm control circuit starts a new round of tracking.

[0048] In order to obtain an impedance matching the voltage source, the present invention designs a buck-boost impedance matching converter 3 controlled by PFM to adjust the equivalent impedance. Refer to Figure 4 ,

[0049] The buck-boost impedance matching converter 3 includes a voltage output terminal VOUT and the fourth signal input terminal V IN and the fifth signal input terminal V REF and the first power PMOS transistor M P1 and the second power PMOS transistor M P2 and the first power NMOS transistor M N1 and the second power NMOS transistor M N2 and the second inductor L, hysteresis comparator CMP1, oscillator, dead-time and driver stage, ZCD circuit, and seventh capacitor C LL and the first resistor R L and the second resistor R1 and the third resistor R2;

[0050] The fourth signal input terminal V IN is connected to the left end of the inductor L through the first power PMOS transistor M P1 The right end of the second inductor L is connected to the voltage output terminal V P2 through the second power PMOS transistor M OUT and one end of the seventh capacitor C LL and one end of the first resistor R L and one end of the second resistor R1. The left end of the second inductor L is connected to the ground through the first power NMOS transistor M N1 The right end of the second inductor L is connected to the ground through the second power NMOS transistor M N2 The fifth signal input terminal V REF is connected to the positive input terminal of the hysteresis comparator CMP1. The negative input terminal of the hysteresis comparator CMP1 is connected to the other end of the second resistor R1 and one end of the third resistor R2. The other end of the third resistor R2 is grounded. The output terminal of the hysteresis comparator CMP1 is connected to the input terminal of the dead-time and driver stage. The output terminal of the oscillator is connected to the input terminal of the dead-time and driver stage. The output terminal of the dead-time and driver stage is connected to the gates of the first power PMOS transistor M P1 and the second power PMOS transistor M P2 and the first power NMOS transistor M N1 and the second power NMOS transistor M N2 The two ends of the second power PMOS transistor M P2 are connected to the input terminal of the ZCD circuit. The output terminal of the ZCD circuit is connected to the input terminal of the dead-time and driver stage. The voltage output terminal V OUT is connected to the energy storage module 5. The charging and discharging of the inductor are controlled by connecting four power transistors to the inductor. The hysteresis comparator compares the feedback voltage with the reference voltage to enable the oscillator. The output terminal of the oscillator is connected to the input terminal of the dead-time and driver stage to generate drive signals for controlling the four power transistors. The equivalent impedance of the buck-boost impedance matching converter 3 can be adjusted by adjusting the frequency of the oscillator.

[0051] To achieve the dynamic tracking process of the entire system, referring to Figure 5 , the present invention designs an interval approximation tracking algorithm. The interval approximation algorithm circuit module 4 includes a logic control module, a first register Reg_A, a second register Reg_B, a first D flip-flop, a first exclusive OR gate XOR, a first multiplexer MUX, a first input signal terminal CLK, a second input signal terminal Comp, and a first output signal terminal Out; a first signal output terminal V MPP_ H and a second signal output terminal V MPP_ L are connected to the input terminal of the logic control module. The output terminal of the logic control module is connected to the input terminals of the first register Reg_A and the first D flip-flop. The first input signal terminal CLK and the second input signal terminal Comp are connected to the input terminal of the first D flip-flop. The output terminal of the first D flip-flop and the second input signal terminal Comp are connected to the input terminals of the first exclusive OR gate XOR. The output terminal of the first exclusive OR gate XOR is connected to the input terminal of the first multiplexer MUX. The output terminal of the first multiplexer MUX is connected to the input terminal of the first register Reg_A. The first output signal Out is connected to the input terminal of the second register Reg_B. The output signals of the first register Reg_A and the second register Reg_B are added together and divided by 2 as the output signal of the first output signal terminal Out, and are connected to the fourth signal input terminal V IN . When the algorithm is tracking, it will automatically generate an upper bound and a lower bound, which can change. The part between them is the tracking search range for the next time of the algorithm. After each clock cycle, an average value will be generated for the upper and lower bounds of the previous cycle. By comparing the result of the target value and the real-time tracking value through a comparator, it is decided to assign the average value to the upper bound or the lower bound of the next cycle. When the upper and lower bounds are replaced each time, the search interval will be reduced by half. After multiple times, the upper and lower bounds will become the same and coincide, and the system search ends and starts to stabilize.

[0052] The logic control module judges whether to Set or Reset the register A according to the values of V MPP _L and V MPP _H. The data of the 9-bit binary code register A and register B are the upper and lower bounds of the tracking algorithm, and are changed according to the change of the Select signal for load tracking every cycle. The output signal of the interval approximation algorithm circuit module 4 is the average value of the register A and the register B. The Select signal controls the operation of the interval approximation algorithm and changes its tracking direction. The Select signal is generated by logic through the Comp signal. Comp is the maximum power point voltage V PLUS and the target reference voltage V MPPThe comparison value. During the operation of the interval approximation algorithm, the tracking process is the approach of B to A, and the generation of the Select signal is an exclusive OR logic.

[0053] The specific working process of the present invention is as follows:

[0054] 1) Startup phase: When the system is connected to the piezoelectric power source, the rectifier 1 starts to work, converting AC energy into DC energy. At this time, the internal module does not work until the output voltage of the rectifier 1 reaches the startup voltage.

[0055] 2) Detection stage of the duty cycle of the conduction time of rectifier 1: When the rectifier 1 starts to work normally, the detection of the duty cycle of the conduction time of the rectifier 1 begins to detect the duty cycle of the conduction time of the rectifier 1. A fixed capacitor is charged with a constant current I, and the clock signal controls the switch, thereby controlling the charging time to detect the duty cycle of the clock signal. V FAC is a signal with a 50% duty cycle and the same frequency as the piezoelectric power source. By adjusting the size of the charging capacitor, a voltage V MPP _H higher than 50% duty cycle, a voltage V MPP _L lower than 50% duty cycle, and a voltage V MPP equal to 50% duty cycle are output. V PLUS The voltage is the voltage for detecting the real-time conduction time V CD signal duty cycle of the rectifier, and the obtained voltage signal is output to the interval approximation algorithm circuit module 4.

[0056] 3) Maximum power point tracking stage: When the detection circuit 2 of the duty cycle of the conduction time of the rectifier detects the duty cycle of the conduction time of the rectifier 1, it outputs a voltage signal to the interval approximation algorithm circuit module 4, and the buck-boost impedance matching converter 3 starts to work. By changing the working frequency of the buck-boost impedance matching converter 3, the equivalent input impedance is changed, thereby changing the conduction duty cycle of the rectifier 1. When the internal resistance of the piezoelectric energy source is equal to the equivalent input impedance of the buck-boost impedance matching converter 3, the conduction duty cycle of the rectifier 1 is 50%, and the energy source outputs the maximum power.

[0057] The present invention proposes an MPPT circuit based on conduction time modulation. It judges whether it is at the maximum power point by whether the conduction duty cycle of the rectifier 1 has reached 50%, and designs a piezoelectric energy harvesting system using the rectifier 1. The interval approximation algorithm circuit module 4 is used for maximum power point tracking. The interval approximation algorithm can achieve MPPT through 9 tracking cycles, and the peak MPPT efficiency can reach 98%. The conduction time modulation MPPT algorithm has many advantages: it is related to the open-circuit voltage V OC and the turnover efficiency η FIrrelevant, no calibration required. The voltage source is continuously connected to the rectifier 1 without causing energy waste, enabling continuous and automatic MPPT, simplifying circuit implementation, and having strong robustness to duty cycle errors.

[0058] Other embodiments of the present invention will be readily apparent to those skilled in the art upon consideration of the specification and the disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and examples are only illustrative, and the true scope and spirit of the present invention are pointed out by the following claims.

[0059] It should be understood that the present invention is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

[0060] The above are only the preferred embodiments of the present invention and do not impose any limitations on the present invention. Any simple modifications, changes, and equivalent structural changes made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solutions of the present invention.

Claims

1. A maximum power point tracking algorithm circuit for piezoelectric energy harvesting, characterized in that, It includes a piezoelectric energy source, a P-SSHI rectifier (1), a rectifier conduction time duty cycle detection circuit (2), a buck-boost impedance matching converter (3) and an interval approximation algorithm circuit module (4). Among them, the output end of the piezoelectric energy source is connected to the first signal input end (V AC1 ) and the second signal input end (V AC2 ) of the rectifier (1). The output end of the rectifier (1) is connected to the input of the rectifier conduction time duty cycle detection circuit (2) and the buck-boost impedance matching converter (3). The output end of the rectifier conduction time duty cycle detection circuit (2) is connected to the input end of the interval approximation algorithm circuit module (4). The output end of the interval approximation algorithm circuit module (4) is connected to the control end of the buck-boost impedance matching converter (3).

2. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 1, wherein It further includes an energy storage module (5), and the input end of the energy storage module (5) is connected to the output end of the buck-boost impedance matching converter (3).

3. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 2, wherein The rectifier (1) includes a first signal input terminal (V AC1 ), a second signal input terminal (V AC2 ), a first PMOS transistor (M P1 ), a second PMOS transistor (M P2 ), a first NMOS transistor (M N1 ), a second NMOS transistor (M N2 ), a first diode (D1), a second diode (D2), a first comparator (CMP1), a second comparator (CMP2), a first switch (SW), a first inductor (L), a first NAND gate (NAND1), a second NAND gate (NAND2), a third NAND gate (NAND3), a fourth NAND gate (NAND4), a first buffer (Buffer1), a second buffer (Buffer2), a third buffer (Buffer3), a first inverter (INV1), a first AND gate (AND1), a pre-resistor (R D ), a first capacitor (C D ), and a second capacitor (C REC ); The first signal input terminal (V AC1 ) and the second signal input terminal (V AC2 ) are connected to the output terminal of the piezoelectric energy source. The first signal input terminal (V AC1 ) is connected to the drain of the first PMOS transistor (M P1 ), the gate of the second PMOS transistor (M P2 ), the drain of the first NMOS transistor (M N1 ), the negative electrode of the first diode (D1), one end of the first switch (SW), and the negative input terminal of the first comparator (CMP1). The second signal input terminal (V AC2 ) is connected to one end of the first inductor (L), the drain of the second PMOS transistor (M P2 ), the gate of the first PMOS transistor (M P1 ), the drain of the second NMOS transistor (M N2 ), the negative electrode of the second diode (D2), and the negative input terminal of the second comparator (CMP2). The source of the first PMOS transistor (M P1 ) is connected to the source of the second PMOS transistor (M P2 ) and one end of the second capacitor (C REC ). The other end of the first switch (SW) is connected to the other end of the first inductor (L). The output terminal of the first comparator (CMP1) is connected to the input terminal of the first NAND gate (NAND1). The output terminal of the first NAND gate (NAND1) is connected to the input terminal of the second NAND gate (NAND2) and the input terminal of the first buffer (Buffer1). The output terminal of the second comparator (CMP2) is connected to the input terminal of the second NAND gate (NAND2). The output terminal of the second NAND gate (NAND2) is connected to the input terminal of the first NAND gate (NAND1) and the input terminal of the second buffer (Buffer2). The output signal terminal (V C1 ) of the first buffer (Buffer1) and the output signal terminal (V C2 ) of the second buffer (Buffer2) are connected to the two input terminals of the third NAND gate (NAND3). The output terminal of the third NAND gate (NAND3) and the enable signal (EN) are connected to the input terminal of the fourth NAND gate (NAND4). The output terminal of the fourth NAND gate (NAND4) is connected to one end of the pre-resistor (R D ) and the input terminal of the first AND gate (AND1). The other end of the pre-resistor (R D ) is connected to the first capacitor (C D ) One end of () is connected to the input terminal of the first inverter (INV1). The output terminal of the first inverter (INV1) is connected to the input terminal of the first AND gate (AND1). The output terminal of the first AND gate (AND1) is connected to the input of the third buffer (Buffer3). The output terminal of the third buffer (Buffer3) generates the signal V SW Control the first switch (SW), the first NMOS transistor (M N1 ) The source of () is connected to the source of the second NMOS transistor (M N2 ) The source of (), the positive electrode of the first diode (D1), the positive electrode of the second diode (D2), the positive input terminal of the first comparator (CMP1), and the positive input terminal of the second comparator (CMP2), the first capacitor (C D ) The other end of () and the other end of the second capacitor (C REC ) The other end of () are all grounded.

4. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 3, characterized in that The rectifier conduction time duty cycle detection circuit (2) includes a third capacitor (C H ), a fourth capacitor (C L ), a fifth capacitor (C MPP ), a sixth capacitor (C P ), a second switch (S1), a third switch (S2), a tenth switch (S3), a fifth switch (S4), a sixth switch (S5), a seventh switch (S6), an eighth switch (S7), a ninth switch (S8), a first current source (I1), a second current source (I2), a third current source (I3), a fourth current source (I4), a third signal input terminal (V FAC ), a first signal output terminal (V MPP_ H), and a second signal output terminal (V MPP_ L); One end of the first current source (I1) is connected to one end of the second switch (S1), and the other end of the second switch (S1) is connected to one end of the third switch (S2) and one end of the third capacitor (C H ). One end of the third switch (S2) and one end of the third capacitor (C H ) are grounded. One end of the second current source (I2) is connected to one end of the fourth switch (S3), and the other end of the fourth switch (S3) is connected to one end of the fifth switch (S4) and one end of the fourth capacitor (C L ). One end of the fifth switch (S4) and one end of the fourth capacitor (C L ) are grounded. One end of the third current source (I3) is connected to one end of the sixth switch (S5), and the other end of the sixth switch (S5) is connected to one end of the seventh switch (S6) and one end of the fifth capacitor (C MPP ). One end of the seventh switch (S6) and one end of the fifth capacitor (C MPP ) are grounded. One end of the fourth current source (I4) is connected to one end of the eighth switch (S7), and the other end of the eighth switch (S7) is connected to one end of the ninth switch (S8) and one end of the sixth capacitor (C P ). One end of the ninth switch (S8) and one end of the sixth capacitor (C P ) are grounded; The output signal terminal (V C1 ) of the first buffer (Buffer1) is connected to the control terminals of the third switch (S2), the fifth switch (S4), the seventh switch (S6), and the ninth switch (S8); The output signal terminal (V C2 ) of the second buffer (Buffer2) is connected to the control terminal of the eighth switch (S7); The third signal input terminal (V FAC ) is connected to the control terminals of the second switch (S1), the fourth switch (S3), and the sixth switch (S5); The line between the first signal output terminal (V MPP_ H) and the second switch (S1) and the third switch (S2) is connected. The second signal output terminal (V MPP_ L) is connected to the line between the fourth switch (S3) and the fifth switch (S4). The first signal output terminal (V MPP_ H) and the second signal output terminal (V MPP_ L) are connected to the interval approximation algorithm circuit module (4).

5. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 4, characterized in that The buck-boost impedance matching converter (3) includes a voltage output terminal (V OUT ), a fourth signal input terminal (V IN ), a fifth signal input terminal (V REF ), a first power PMOS transistor (M P1 ), a second power PMOS transistor (M P2 ), a first power NMOS transistor (M N1 ), a second power NMOS transistor (M N2 ), a second inductor (L), a hysteresis comparator (CMP1), an oscillator, a dead-time and driver stage, a ZCD circuit, a seventh capacitor (C LL ), a first resistor (R L ), a second resistor (R1), and a third resistor (R2); The fourth signal input terminal (V IN ) is connected to the left end of an inductor (L) through a first power PMOS transistor (M P1 ). The right end of a second inductor (L) is connected to a voltage output terminal (V P2 ), one end of a seventh capacitor (C OUT ), one end of a first resistor (R LL ), and one end of a second resistor (R1) through a second power PMOS transistor (M L ). The left end of the second inductor (L) is connected to ground through a first power NMOS transistor (M N1 ). The right end of the second inductor (L) is connected to ground through a second power NMOS transistor (M N2 ). A fifth signal input terminal (V REF ) is connected to the positive input terminal of a hysteresis comparator (CMP1). The negative input terminal of the hysteresis comparator (CMP1) is connected to the other end of the second resistor (R1) and one end of a third resistor (R2). The other end of the third resistor (R2) is grounded. The output terminal of the hysteresis comparator (CMP1) is connected to the input terminal of a dead zone and driver stage. The output terminal of an oscillator is connected to the input terminal of the dead zone and driver stage. The output terminal of the dead zone and driver stage is connected to the gates of the first power PMOS transistor (M P1 ), the second power PMOS transistor (M P2 ), the first power NMOS transistor (M N1 ), and the second power NMOS transistor (M N2 ). Both ends of the second power PMOS transistor (M P2 ) are connected to the input terminal of a ZCD circuit. The output terminal of the ZCD circuit is connected to the input terminal of the dead zone and driver stage. The voltage output terminal (V OUT ) is connected to an energy storage module (5).

6. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 5, wherein The interval approximation algorithm circuit module (4) includes a logic control module, a first register (Reg_A), a second register (Reg_B), a first D flip-flop, a first exclusive OR gate (XOR), a first multiplexer (MUX), a first input signal terminal (CLK), a second input signal terminal (Comp), and a first output signal terminal (Out); The first signal output terminal (V MPP_ H) and the second signal output terminal (V MPP_ L) are connected to the input terminal of the logic control module. The output terminal of the logic control module is connected to the input terminals of the first register (Reg_A) and the first D flip-flop. The first input signal terminal (CLK) and the second input signal terminal (Comp) are connected to the input terminals of the first D flip-flop. The output terminal of the first D flip-flop and the second input signal terminal (Comp) are connected to the input terminals of the first exclusive-OR gate (XOR). The output terminal of the first exclusive-OR gate (XOR) is connected to the input terminal of the first multiplexer (MUX). The output terminal of the first multiplexer (MUX) is connected to the input terminal of the first register (Reg_A). The first output signal (Out) is connected to the input terminal of the second register (Reg_B). The output terminals of the first register (Reg_A) and the second register (Reg_B) are connected to the input terminal of the first multiplexer (MUX). The sum of the output signals of the first register (Reg_A) and the second register (Reg_B) is divided by 2 to be used as the output signal of the first output signal terminal (Out), and is connected to the fourth signal input terminal (V IN ).

7. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 1, characterized in that The energy storage module (5) is a capacitor.

8. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 1, characterized in that The energy storage module (5) is a battery.

9. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 1, wherein It is determined whether it is at the maximum power point by whether the conduction duty ratio of the rectifier (1) has reached 50%.

10. The maximum power point tracking algorithm circuit for piezoelectric energy harvesting according to claim 1, characterized in that, The interval approximation algorithm circuit module (4) is used for maximum power point tracking.

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