Multi-path Feiteng CPU cascade management system applied to server

Abstract

The invention belongs to the technical field of servers, and particularly discloses a multi-path Feiteng CPU cascade management system applied to a server. The system comprises a microcontroller unit and a programmable logic unit, the microcontroller unit is connected with each CPU and used for monitoring output information of each CPU in real time, if fault information is analyzed from the output information, the fault CPU is isolated, and the cascade mode of the CPU is switched; the switching module is also used for switching the cascade mode of the CPU according to the cascade mode switching command; the microcontroller unit is also connected with a server power supply, and the power supply output of the server power supply to each CPU is adjusted according to the cascade mode of the CPUs; and the programmable logic unit is connected with the microcontroller unit and is used for adjusting the power-on time sequence of each CPU according to the cascade mode of the CPU selected by the microcontroller unit. By means of the system, online switching of the multi-channel Feiteng CPU cascade mode is achieved.

Description

Technical Field

[0001] This application belongs to the technical field of servers, and more specifically, relates to a multi-way Feiteng CPU cascade management system applied to servers. Background Art

[0002] Feiteng is a high-performance general-purpose CPU design enterprise independently developed in China. Its processors are based on the ARM architecture and are widely used in fields such as government affairs, finance, energy, telecommunications, and cloud computing, and are one of the key solutions for domestic substitution.

[0003] Currently, multi-way Feiteng CPUs are cascaded through a hardware interconnection protocol and firmware configuration to build a high-performance multi-way server system. However, servers based on multi-way Feiteng CPU cascades have the following problems: The operation of switching the cascade mode is too complex, requiring disassembly, programming, and firmware update. Therefore, the online switching of the multi-way Feiteng CPU cascade mode cannot be achieved, and when a certain CPU fails, the mode cannot be switched online to shield the faulty path, easily leading to serious situations such as the entire machine crashing. Summary of the Invention

[0004] In view of the above defects or improvement requirements of the prior art, this application provides a multi-way Feiteng CPU cascade management system applied to servers, aiming to solve the technical problem that existing servers based on multi-way Feiteng CPU cascades cannot achieve online switching of the CPU cascade mode.

[0005] To achieve the above object, this application provides a multi-way Feiteng CPU cascade management system applied to servers, including a microcontroller unit and a programmable logic unit; The microcontroller unit is connected to each CPU, used to monitor the output information of each CPU in real time. If fault information is parsed from the output information, the faulty path CPU is isolated, and the cascade mode of the CPU is switched; it is also used to switch the cascade mode of the CPU according to the received cascade mode switching command; The microcontroller unit is also connected to the server power supply, and adjusts the power output of the server power supply to each CPU according to the cascade mode of the CPU; The programmable logic unit is connected to the microcontroller unit, and is used to adjust the power-on timing of each CPU according to the cascade mode of the CPU selected by the microcontroller unit.

[0006] Preferably, the microcontroller unit monitors the output information of each CPU by means of interrupt data frames. If fault information is parsed from the output information, an interrupt signal is triggered, the current task is paused, the faulty path CPU is isolated, and the cascade mode of the CPU is switched.

[0007] Preferably, a mapping table of fault information and CPU cascade mode is pre - set inside the micro - controller unit. If the micro - controller unit parses fault information from the output information, it finds the CPU cascade mode corresponding to the fault information from the mapping table by looking up the table, and switches the remaining normal CPUs to the corresponding CPU cascade mode.

[0008] Preferably, a Web server is deployed inside the micro - controller unit. Through the Web server, network communication with a remote monitoring unit is realized, the cascade mode switching command of the monitoring unit is received, and the fault information is uploaded to the monitoring unit.

[0009] Preferably, to switch the CPU cascade mode, specifically: the micro - controller unit interrupts the task execution of each CPU, updates the cascade mode to be switched into the firmware of each CPU; the programmable logic unit adjusts the power - on timing of each CPU according to the cascade mode to be switched, and restarts each CPU; the micro - controller unit adjusts the power output of the server power supply to each CPU according to the CPU cascade mode.

[0010] Preferably, the micro - controller unit communicates with other units in a response mode.

[0011] Preferably, the cascade mode includes a performance mode and an energy - saving mode; in the performance mode, all current normal CPUs run at the highest speed; in the energy - saving mode, one CPU works and the other CPUs are in a sleep state.

[0012] Preferably, the micro - controller unit communicates with each CPU, the programmable logic unit, and the server power supply through a bus.

[0013] Preferably, the micro - controller unit is an MCU.

[0014] Preferably, the programmable logic unit is a CPLD.

[0015] Generally speaking, compared with the prior art, the above - mentioned technical solution conceived by this application has the following beneficial effects: (1) By adding a micro - controller unit and a programmable logic unit to the server in this application system, the online switching of the multi - path CPU cascade mode is realized. At the same time, the running status of the multi - path CPU can be detected in real - time. When a fault occurs, the fault can be isolated in time and the cascade mode for dealing with the fault can be switched, improving the high availability of the server.

[0016] (2) A Web server is deployed inside the micro - controller unit in this application system, so that the network remote monitoring unit can manage the multi - path CPU cascade mode of the server.

[0017] (3) In the system of this application, the microcontroller unit monitors the output information of each CPU by interrupting data frames, takes CPU fault handling as the first priority, and can isolate the faulty CPU at the first moment of the fault occurrence, thereby improving the high availability of the server.

[0018] (4) In the system of this application, compared with other microprocessors, the MCU has the characteristics of low power consumption, real-time response, high reliability and hardware-level security, and is suitable for the server's requirements for stable, reliable and low-power operation. It is an ideal choice for assisting the server in managing the multi-way CPU cascading mode; compared with other programmable logic units, the CPLD has the characteristics of low latency, high reliability and non-volatility, and is an ideal choice for assisting the server in power-on timing control. Brief Description of the Drawings

[0019] Figure 1 It is a connection schematic diagram of the multi-way Feiteng CPU cascading management system provided by the embodiment of this application.

[0020] Figure 2 It is a flow schematic diagram of managing the cascading mode according to the CPU operating status provided by the embodiment of this application.

[0021] Figure 3 It is a flow schematic diagram of the multi-way CPU cascading mode switching provided by the embodiment of this application. Specific Embodiments

[0022] In order to make the purpose, technical solutions and advantages of this application clearer, the following further details this application in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0023] The terms "first" and "second" in the specification and claims of this application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first CPU and the second CPU are used to distinguish different CPUs, rather than to describe the specific order of the CPUs.

[0024] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or more advantageous than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0025] In the description of the embodiments of this application, unless otherwise specified, "multi-way" means two or more than two. For example, multi-way CPUs mean two or more than two CPUs, etc. First, introduce the technical terms involved in the embodiments of this application.

[0026] MCU (Microcontroller Unit) is an embedded system core component integrating a processor core, memory, peripheral interfaces, and dedicated functions, and is widely used in the fields of the Internet of Things, industrial control, consumer electronics, etc.

[0027] CPLD (Complex Programmable Logic Device) is a semiconductor device based on programmable logic gate arrays, designed for medium- and low-complexity digital circuits.

[0028] A Web server refers to a software / hardware system that can provide web content services through the HTTP protocol and is an important part of the Internet infrastructure.

[0029] Next, describe the embodiments of this application in combination with the accompanying drawings in the embodiments of this application.

[0030] As Figure 1 shown, the figure is a server adopting the multi-way Feiteng CPU cascading management system of this application, which includes a schematic diagram of the composition of the embodiments of this application, including a microcontroller unit and a programmable logic unit.

[0031] In this embodiment, for the microcontroller unit, an MCU is selected, which is the STM32F407VGT6 of STMicroelectronics. It uses a Cortex-M4 core, has a main frequency of 168 MHz, 1 MB of Flash, 192 KB of RAM, and integrates USB OTG and Ethernet MAC, and is suitable for industrial control.

[0032] For the programmable logic unit, a CPLD is selected, which is the MAXV5M80ZE64C5N of Intel. It contains 40 macro cells, 80 I / Os, supports 1.8V to 3.3V levels, and is suitable for interface expansion and logic integration.

[0033] Compared with other microprocessors, the MCU has the characteristics of low power consumption, real-time response, high reliability, and hardware-level security, and is suitable for the server's requirements for stable, reliable, and low-power operation. It is an ideal choice to assist the server in managing the multi-way CPU cascading mode; compared with other programmable logic units, the CPLD has the characteristics of low latency, high reliability, and non-volatility, and is an ideal choice to assist the server in power-on timing control.

[0034] The PCIe bus is suitable for scenarios with high bandwidth, low latency, and reliable transmission. Therefore, in the embodiments of this application, the MCU conducts data interaction with each Feiteng CPU through the PCIe bus; the I2C bus is suitable for scenarios with simple control, low cost, and low power consumption. Therefore, in the embodiments of this application, the MCU conducts data interaction with the CPLD and server power supply through the I2C bus.

[0035] As Figure 2 shown is the process of the MCU in the embodiments of this application for cascade mode management according to the operating states of multiple CPUs, which is specifically as follows: The MCU uses an answering method to inquire about the operating states of each CPU. The MCU, in accordance with the communication protocol of the Feiteng CPU, sends an operating state inquiry command to multiple Feiteng CPUs at a preset time interval, such as every 1 second. After receiving the operating state inquiry command, each Feiteng CPU returns its own operating state information to the MCU. The MCU analyzes the received CPU operating state information and identifies the fault information through the keywords of the fault code, such as temperature anomaly, power supply anomaly, cache error, instruction execution anomaly, etc. In the embodiments of this application, bytes such as "Error", "Fault", "Bug", and "Shutdown" in the operating state information are used as keywords for fault identification.

[0036] After the MCU receives the operating state information of each CPU, it identifies these keywords in the operating state information. After identifying the keywords, it further identifies the specific fault category. These keywords can be set according to specific requirements and the model of the Feiteng CPU.

[0037] The data interaction between the MCU and each CPU is relatively frequent, and the amount of interaction data is also relatively large. Therefore, in the embodiments of this application, the method of locating faults by identifying keywords can effectively reduce the operating load of the MCU.

[0038] If the MCU identifies a specific fault category, for example, it identifies that the operating state information of a CPU contains the fault information of "power supply anomaly", it issues an interrupt signal to pause the current task to prevent the fault from further developing and causing the server to crash. Subsequently, the MCU controls the power supply to isolate the faulty CPU. The MCU uses this method of interrupting data frames to monitor the output information of each CPU, giving the CPU fault handling the highest priority, and can isolate the faulty CPU at the first time when the fault occurs, thereby improving the high availability of the server.

[0039] The MCU has a mapping table of fault information and CPU cascade mode built in. There are CPU cascade modes for dealing with various faults in the mapping table, which are used to guide the response to various CPU faults. If the MCU discovers the fault information of the CPU, it searches for the CPU cascade mode corresponding to the fault information from the reference mapping table and switches the remaining available multiple CPUs to the cascade mode of this CPU.

[0040] For some content in the mapping table in the embodiments of this application, see Table 1: Table 1

[0041] As can be seen from the mapping table, in this embodiment, if a CPU temperature anomaly fault is detected, the faulty CPU is isolated, the cascade mode of the remaining available CPUs is switched to the low-rate mode, the operating rate of the multi-way CPUs is reduced, the energy consumption is reduced, and the temperature is decreased.

[0042] A Web server is deployed inside the MCU. Through the Web server, network communication with a remote monitoring unit is achieved, the cascade mode switching command of the monitoring unit is received, and the received CPU fault information is uploaded to the monitoring unit. In this embodiment, an Nginx server is deployed inside the MCU as the Web server. Nginx is a high-performance open-source Web server, known for its lightweight, high concurrency processing ability, and low memory consumption. Based on this, the MCU can achieve network communication and realize remote control of the CPU cascade mode and remote monitoring of the CPU operating status through the network.

[0043] The MCU uploads the received CPU operating status and fault information to the remote monitoring unit through the Nginx server. At the same time, the monitoring unit issues a switching command for the CPU cascade mode through the Nginx server. In the embodiments of this application, a user interface is locally deployed on the monitoring unit. The operating status of each CPU can be displayed in the user interface, and there is also a function for switching the CPU cascade mode. By selecting the CPU cascade mode on the user interface, the cascade mode of the multi-way Feiteng CPUs in the server can be switched.

[0044] When the MCU receives a switching command for the CPU cascade mode, for example, when it receives a cascade mode switching command and switches the cascade mode of the multi-way CPUs to the performance mode, it starts the CPU cascade mode switching process, as Figure 3 shown. The process is as follows: The MCU interrupts the task execution of each CPU and updates the operating parameters and metrics of the CPUs in the performance mode to the firmware of each CPU.

[0045] The MCU sends the power-on sequence of each CPU in the performance mode to the CPLD. For example, 4 CPUs are powered on in sequence with a power-on interval of 500 milliseconds.

[0046] The CPLD adjusts the power-on sequence of each CPU and restarts each CPU in sequence according to the sequence.

[0047] The MCU adjusts the power output of the server power supply to each CPU according to the performance mode. Since it is the performance mode, the power output of the server power supply to each CPU is the maximum voltage of each CPU.

[0048] Based on the above process, the online switching of the multi-CPU cascade mode is realized. The embodiment of the present application discloses a CPU cascade management system, which reduces the operation difficulty of switching the CPU cascade mode. A CPU cascade mode for dealing with various CPU faults is also preset to ensure that the fault is isolated at the first moment of the fault occurrence and the cascade mode for dealing with the fault is switched, improving the high availability of the server.

[0049] In the embodiment of the present application, the cascade modes in the mapping table preset in the MCU include various rate modes, balanced modes, performance modes, energy-saving modes, etc., specifically: In the performance mode, all CPUs run at the highest rate; In the energy-saving mode, one CPU works and the other CPUs sleep; In the balanced mode, all CPUs run at the rated rate; In the low-rate mode, each CPU runs at half of the rated rate.

[0050] Presetting the cascade modes of different CPUs can meet different task requirements, facilitating the online switching of the CPU cascade mode. It can also deal with various different CPU faults.

[0051] Those skilled in the art can easily understand that the above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-way Feiteng CPU cascade management system applied to a server, characterized in that It includes a microcontroller unit and a programmable logic unit; The microcontroller unit is connected to each CPU, and is used to monitor the output information of each CPU in real time. If fault information is parsed from the output information, it isolates the faulty CPU and switches the cascade mode of the CPU; it is also used to switch the cascade mode of the CPU according to the received cascade mode switching command; The microcontroller unit is also connected to the server power supply, and adjusts the power output of the server power supply to each CPU according to the cascade mode of the CPU; The programmable logic unit is connected to the microcontroller unit, and is used to adjust the power-on timing of each CPU according to the cascade mode of the CPU selected by the microcontroller unit.

2. The multi-FeiTeng CPU cascade management system according to claim 1, wherein The microcontroller unit monitors the output information of each CPU by using the interrupt data frame. If fault information is parsed from the output information, it triggers an interrupt signal, pauses the current task, isolates the faulty CPU, and switches the cascade mode of the CPU.

3. The multi-FeiTeng CPU cascading management system according to claim 1 or 2, characterized in that, A mapping table of fault information and CPU cascade mode is preset inside the microcontroller unit. If the microcontroller unit parses fault information from the output information, it finds the CPU cascade mode corresponding to the fault information from the mapping table by looking up the table, and switches the remaining normal CPUs to the corresponding CPU cascade mode.

4. The multi-FeiTeng CPU cascading management system according to claim 1, wherein A Web server is deployed inside the microcontroller unit, and network communication with the remote monitoring unit is realized through the Web server. The cascade mode switching command of the monitoring unit is received, and the fault information is uploaded to the monitoring unit.

5. The multi-FeiTeng CPU cascade management system according to claim 1, wherein Switching the cascade mode of the CPU is specifically as follows: the microcontroller unit interrupts the task execution of each CPU, updates the cascade mode to be switched to the firmware of each CPU; the programmable logic unit adjusts the power-on timing of each CPU according to the cascade mode to be switched, and restarts each CPU; the microcontroller unit adjusts the power output of the server power supply to each CPU according to the cascade mode of the CPU.

6. The multi-FeiTeng CPU cascading management system according to claim 1, wherein The microcontroller unit communicates with other units in an answering mode.

7. The multi-FeiTeng CPU cascade management system according to claim 1, wherein The cascade mode includes a performance mode and an energy-saving mode; in the performance mode, all current normal CPUs run at the highest speed; in the energy-saving mode, one CPU works and the other CPUs are in a sleep state.

8. The multi-FeiTeng CPU cascading management system according to claim 1, characterized in that, The microcontroller unit communicates with each CPU, the programmable logic unit, and the server power supply through a bus.

9. The multi-FeiTeng CPU cascading management system according to claim 1, wherein The microcontroller unit is an MCU.

10. The multi-way Feiteng CPU cascade management system according to claim 1, characterized in that, The programmable logic unit is a CPLD.

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