Wafer bonding structure and forming method thereof

Abstract

The invention discloses a wafer bonding structure and a forming method thereof, and the structure comprises a first wafer which comprises a first substrate and a first device layer located on the surface of the first substrate; a plurality of first bonding grooves located in the first device layer, wherein each first bonding groove comprises a first region and a second region located at the top of the first region; the first protection layer is located on the side wall surface of the second region and the top surface of the first device layer; the first conductive structure is located in the first bonding groove, and the first conductive structure is located on the surface of the side wall of the first protection layer and fills the first bonding groove. And the first protection layer is located on the side wall surface of the second region in the first bonding groove and the top surface of the first device layer, so that when the first bonding groove is formed through etching, etching stops at the first protection layer, the first device layer adjacent to the first protection layer is protected, and the integrity of the wafer bonding structure is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a wafer bonding structure and a method for forming the same. Background Art

[0002] With the continuous advancement of the construction of new infrastructure such as 5G and artificial intelligence, the improvement of system functions and performance brought about by simply reducing the process size and increasing the single-chip area has become difficult to meet the needs of future development. Chip miniaturization has become increasingly difficult, while the market's pursuit of high-performance chips remains unabated. The industry has begun to explore breakthroughs in the packaging field. Among them, three-dimensional packaging technology is becoming an important means to improve chip performance. In three-dimensional packaging, hybrid bonding technology, as a technology that can bond both conductive regions and dielectric regions simultaneously to achieve bonding between chips, between chips and wafers, and between two wafers, the achievable bonding strength is directly related to the reliability of the entire packaging system.

[0003] However, in the existing wafer bonding technology, the accuracy of bonding alignment between two wafers and the bonding strength are reduced, affecting the reliability of the packaging system. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a wafer bonding method and a method for forming the same, which improve the accuracy of bonding alignment and the bonding strength between wafers.

[0005] To solve the above technical problem, an embodiment of the present invention provides a wafer bonding structure, including: a first wafer, including a first substrate and a first device layer located on the surface of the first substrate; a plurality of first bonding trenches located in the first device layer, the first bonding trenches including a first region and a second region located on top of the first region; a first protective layer located on the sidewall surface of the second region and the top surface of the first device layer; a first conductive structure located in the first bonding trench, the first conductive structure being located on the sidewall surface of the first protective layer and filling the first bonding trench.

[0006] Optionally, the first device layer includes: a plurality of stacked first composite layers located on the first substrate, the first composite layer including a first barrier layer and a first dielectric layer located on the first barrier layer; the first bonding trench penetrates at least one layer of the first dielectric layer.

[0007] Optionally, the material of the first dielectric layer is different from the material of the first protective layer.

[0008] Optionally, the material of the first barrier layer includes one or more combinations of silicon nitride, silicon oxide, and silicon dioxide, and the material of the first dielectric layer includes one or more combinations of silicon nitride, silicon oxynitride, and silicon carbonitride; the material of the first protective layer includes one or more combinations of silicon nitride compounds, silicon carbide, silicon oxynitride silicon dioxide, aluminum oxide, and titanium nitride compounds.

[0009] Optionally, the first device layer further includes: a second dielectric layer located between the first substrate and the plurality of first composite layers, and a first electrical interconnection structure is provided in the second dielectric layer; at least one of the first conductive structures is connected to the first electrical interconnection structure.

[0010] Optionally, the first device layer further includes: a first device structure located in the second dielectric layer, and the first device structure is electrically connected to the first electrical interconnection structure.

[0011] Optionally, the first electrical interconnection structure includes a plurality of first conductive layers and first conductive plugs, and the first conductive plugs are located between adjacent first conductive layers and between the first conductive layer and the first substrate.

[0012] Optionally, the first device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

[0013] Optionally, the plurality of first bonding grooves include a plurality of first grooves and a plurality of second grooves, and the depth of the first grooves is greater than the depth of the second grooves.

[0014] Optionally, the wafer bonding structure further includes: a second wafer bonded to the first wafer, including a second substrate and a second device layer on the surface of the second substrate, and the second device layer is in contact with the first device layer; a plurality of second bonding grooves in the second device layer and a plurality of second conductive structures in the plurality of second bonding grooves, and the second conductive structures are in contact with the first conductive structures.

[0015] Optionally, the second bonding groove includes a third region and a fourth region on top of the third region, and a second protective layer on the sidewall surface of the fourth region and on the top surface of the second device layer.

[0016] Optionally, the second device layer includes: a plurality of stacked second composite layers on the second substrate, the second composite layer includes a second barrier layer and a third dielectric layer on the second barrier layer; the second bonding groove penetrates at least one of the third dielectric layers.

[0017] Optionally, the second device layer further includes: a fourth dielectric layer located between the second substrate and the plurality of second composite layers, the fourth dielectric layer having a second electrical interconnect structure therein; at least one of the second conductive structures is connected to the second electrical interconnect structure.

[0018] Optionally, the second device layer further includes: a second device structure located within the fourth dielectric layer, the second device structure being electrically connected to the second electrical interconnect structure.

[0019] Optionally, the second electrical interconnect structure includes a plurality of second conductive layers and second conductive plugs, the second conductive plugs being located between adjacent second conductive layers, and between the second conductive layers and the second substrate.

[0020] Optionally, the second device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

[0021] Optionally, the plurality of second bonding trenches includes a plurality of third trenches and a plurality of fourth trenches, the depth of the third trenches being greater than the depth of the fourth trenches.

[0022] Correspondingly, the technical solution of the present invention further provides a method for forming a wafer bonding structure, including: providing a first wafer, the first wafer including a first substrate and a first device layer on the surface of the first substrate; forming a plurality of initial first bonding trenches in the first device layer; forming an initial first protective layer on the sidewall surface, bottom surface of the initial first bonding trenches, and the top surface of the first device layer; after forming the initial first protective layer, etching the initial first protective layer and the first device layer at the bottom of the initial first bonding trenches to form a first bonding trench in the first device layer, the first bonding trench including a first region and a second region located on top of the first region, and forming a first protective layer on the sidewall surface of the second region and the top surface of the first device layer; forming a first conductive structure in the first bonding trench, the first conductive structure being located on the sidewall surface of the first protective layer and filling the first bonding trench.

[0023] Optionally, the method for forming the first device layer includes: forming a plurality of stacked first composite layers on the surface of the first substrate, the first composite layer including a first barrier layer and a first dielectric layer on the first barrier layer; the first bonding trench penetrates at least one of the first dielectric layers.

[0024] Optionally, the etching process for forming the initial first bonding trench has a ratio of the etching rate of the first dielectric layer to the first protective layer in the range of: 5:1 to 20:1.

[0025] Optionally, the method for forming the first device layer further includes: forming a second dielectric layer between the first substrate and the plurality of first composite layers, the second dielectric layer having a first electrical interconnection structure therein; connecting at least one of the first conductive structures to the first electrical interconnection structure.

[0026] Optionally, the first electrical interconnection structure includes a plurality of first conductive layers and first conductive plugs, the first conductive plugs being located between adjacent first conductive layers and between the first conductive layer and the first substrate.

[0027] Optionally, the method for forming the first device layer further includes: forming a first device structure in the second dielectric layer, the first device structure being electrically connected to the first electrical interconnection structure.

[0028] Optionally, the plurality of first bonding grooves include a plurality of first grooves and a plurality of second grooves, the depth of the first grooves being greater than the depth of the second grooves.

[0029] Optionally, the method for forming the wafer bonding structure further includes: providing a second wafer, the second wafer including a second substrate and a second device layer on the surface of the second substrate, the second device layer being in contact with the first device layer; forming a plurality of second bonding grooves in the second device layer; forming a plurality of second conductive structures in the plurality of second bonding grooves, the second conductive structures being in contact with the first conductive structures.

[0030] Optionally, the method for forming the second bonding grooves further includes: forming a plurality of initial second bonding grooves in the second device layer; forming an initial second protective layer on the sidewall surface, bottom surface of the initial second bonding grooves, and the top surface of the second device layer; after forming the initial second protective layer, etching the initial second protective layer and the second device layer at the bottom of the initial second bonding grooves to form second bonding grooves in the second device layer, the second bonding grooves including a third region and a fourth region on top of the third region, and forming a second protective layer on the sidewall surface of the fourth region and the top surface of the second device layer.

[0031] Optionally, the method for forming the second device layer includes: forming a plurality of stacked second composite layers on the second substrate, the second composite layers including a third dielectric layer, a second barrier layer, and a third dielectric layer on the second barrier layer; the second bonding grooves penetrate at least one of the third dielectric layers.

[0032] Optionally, the method for forming the second device layer further includes: forming a fourth dielectric layer between the second substrate and the plurality of second composite layers; forming a second electrical interconnection structure in the fourth dielectric layer; connecting at least one of the second conductive structures to the second electrical interconnection structure.

[0033] Optionally, the method for forming the second electrical interconnection structure includes: forming a plurality of layers of second conductive layers and second conductive plugs in the fourth dielectric layer, where the second conductive plugs are located between adjacent second conductive layers, and between the second conductive layer and the second substrate.

[0034] Optionally, the method for forming the second device layer further includes: forming a second device structure in the fourth dielectric layer, where the second device structure is electrically connected to the second electrical interconnection structure.

[0035] Optionally, the plurality of second bonding grooves include a plurality of third grooves and a plurality of fourth grooves, and the depth of the third grooves is greater than the depth of the fourth grooves.

[0036] Optionally, the method for forming the wafer bonding structure further includes: performing a bonding process on the first wafer and the second wafer, where the first conductive structure is bonded to the second conductive structure.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0038] For the wafer bonding structure provided by the technical solution of the present invention, the first protective layer is located on the sidewall surface of the second region in the first bonding groove and the top surface of the first device layer, so that when etching to form the first bonding groove, the etching stops at the first protective layer, protecting the adjacent first device layer, ensuring the integrity of the wafer bonding structure, and further making the size of the first bonding groove in the direction parallel to the first substrate unchanged. And because the shape of the first conductive structure matches the first bonding groove, the integrity of the first conductive structure is ensured, improving the accuracy and bonding strength of the bonding alignment between wafers, and further improving the performance and yield of the bonding structure.

[0039] Furthermore, the material of the first dielectric layer in the technical solution of the present invention is different from the material of the first protective layer, so that when etching to form the first bonding groove, the etching stops at the first protective layer, protecting the adjacent first device layer, and ensuring the integrity of the wafer bonding structure.

[0040] Furthermore, the first bonding groove in the technical solution of the present invention includes a first groove and a plurality of second grooves, and the first conductive structure is respectively located in the first groove and the second grooves; the plurality of second bonding grooves include a plurality of third grooves and a plurality of fourth grooves, and the second conductive structure is respectively located in the third grooves and the fourth grooves, and the first conductive structure is bonded to the second conductive structure, increasing the bonding area, enhancing the bonding strength between the first wafer and the second wafer, and ensuring the uniformity of the first device layer and the second device layer.

[0041] Furthermore, the second protective layer is located on the sidewall surfaces of the fourth region in the second bonding trench and the top surface of the second device layer, such that when etching to form the second bonding trench, the etching stops at the second protective layer, protecting the adjacent second device layer, ensuring the integrity of the wafer bonding structure. Furthermore, the size of the second bonding trench in the direction parallel to the second substrate remains unchanged. Since the shape of the second conductive structure matches that of the second bonding trench, the integrity of the second conductive structure is ensured, improving the precision of wafer bonding alignment and the bonding strength, and further enhancing the performance and yield of the bonding structure.

[0042] In the method for forming a wafer bonding structure provided by the technical solution of the present invention, by forming the first protective layer on the sidewall surfaces of the second region in the first bonding trench and the top surface of the first device layer, when etching to form the first bonding trench, the etching stops at the first protective layer, protecting the adjacent first device layer, ensuring the integrity of the wafer bonding structure. Furthermore, the size of the first bonding trench in the direction parallel to the first substrate remains unchanged. Since the shape of the first conductive structure matches that of the first bonding trench, the integrity of the first conductive structure is ensured, improving the precision of wafer bonding alignment and the bonding strength, and further enhancing the performance and yield of the bonding structure.

[0043] Furthermore, the etching rate of the first protective layer in the technical solution of the present invention is less than that of the first dielectric layer, such that when etching to form the first bonding trench, the etching stops at the first protective layer, protecting the adjacent first device layer to prevent damage to the bonded wafers, and further ensuring the performance of the bonded wafers.

[0044] Furthermore, in the technical solution of the present invention, the first bonding trench includes a first trench and a plurality of second trenches, and the first conductive structure is formed in the first trench and the plurality of second trenches respectively; the plurality of second bonding trenches include a plurality of third trenches and a plurality of fourth trenches, and the second conductive structure is formed in the third trenches and the fourth trenches respectively, and the first conductive structure is bonded to the second conductive structure, increasing the bonding area, enhancing the bonding strength between the first wafer and the second wafer, and ensuring the uniformity of the first device layer and the second device layer.

[0045] Further, by forming a second protective layer on the sidewall surface of the fourth region in the second bonding trench and on the top surface of the second device layer, when the second bonding trench is etched, the etching stops at the second protective layer, protecting the adjacent second device layer, ensuring the integrity of the wafer bonding structure. Furthermore, the dimension of the second bonding trench in the direction parallel to the second substrate remains unchanged. Since the shape of the second conductive structure matches that of the second bonding trench, the integrity of the second conductive structure is ensured, improving the accuracy of wafer bonding alignment and the bonding strength, and further enhancing the performance and yield of the bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figures 1 to 5 is a schematic structural diagram of a wafer bonding structure;

[0047] Figures 6 to 22 is a schematic structural diagram of the formation process of the wafer bonding structure in an embodiment of the present invention;

[0048] Figures 23 to 29 is a schematic structural diagram of the formation process of the wafer bonding structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0049] As described in the background art, the accuracy of wafer bonding alignment and the bonding strength between two wafers in the current wafer bonding structure need to be further improved.

[0050] Figure 1 is a schematic structural diagram of a bonding structure Figure 1 .

[0051] Please refer to Figure 1 , Figure 1 which only shows the structure of the bottom wafer in the bonding structure. The bonding structure includes: a wafer, including a substrate 100 and a device layer 101 located on the surface of the substrate 100;; a bonding trench located in the device layer 101, and the bonding trench includes a first region and a second region located on top of the first region.

[0052] The bonding trench includes a first trench 102 and a second trench 103.

[0053] In the above solution, the first region and the second region of the bonding trench are made of the same material and have the same etching rate. When etching to form the trench, the etching time of the second region is longer than that of the first region, that is, the etching time of the second region increases, which easily forms Figure 1 the "flare" shape at the opening of the trench.

[0054] Figure 2 is a schematic structural diagram of a bonding structure Figure 2 .

[0055] Please refer to Figure 2, Figure 2 It is a bonding schematic diagram of a conductive structure in a bonding structure, including: a first conductive structure 104 and a second conductive structure 105 that are bonded.

[0056] Among them, there is a hemming width L1 at the bonding surface connection of the first conductive structure 104 and the second conductive structure 105.

[0057] Figures 3 to 5 It is a structural schematic of a bonding structure Figure 3 .

[0058] Figures 3 to 5 Same as Figure 2 the conductive structure in, the difference is that the shape of the second conductive structure 106 is different.

[0059] Please refer to Figure 1 on the basis of Figure 3 , Figure 4 and Figure 5 , because Figure 3 the shape of the second conductive structure 106 in is matched with the shape in the trench, that is, Figure 3 there is also a "flare" at the top of the second conductive structure 106 in, which further reduces the hemming width L1 at the bonding surface connection of the first conductive structure 104 and the second conductive structure 106, resulting in a decrease in the alignment accuracy between the two wafers as shown in Figure 4 , and further reduces the bonding strength between the two wafers, affecting the reliability of the packaging system; in addition, when the alignment accuracy between the two wafers decreases, the first conductive structure is likely to diffuse into the second device layer 107, resulting in problems such as short - circuit risk and large resistance, affecting the yield of the bonded devices.

[0060] To solve the above - mentioned technical problems, the technical solution of the present invention provides a wafer bonding structure and a method for forming the same. By forming the first protective layer on the side wall surface of the second region and the top surface of the first device layer in the first bonding trench, when etching to form the first bonding trench, the etching stops at the first protective layer, protecting the adjacent first device layer, ensuring the integrity of the wafer bonding structure. Furthermore, the size of the first bonding trench in the direction parallel to the first substrate remains unchanged, and since the shape of the first conductive structure matches the first bonding trench, the integrity of the first conductive structure is ensured, improving the alignment accuracy and bonding strength between the wafers, and further enhancing the performance and yield of the bonding structure.

[0061] To make the above - mentioned objects, features, and beneficial effects of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0062] Figures 6 to 22It is a schematic structural diagram of the formation process of a wafer bonding structure in an embodiment of the present invention.

[0063] Please refer to Figure 6 , a first wafer is provided, and the first wafer includes a first substrate 200.

[0064] The first wafer includes a semiconductor thin sheet for manufacturing integrated circuits. Common wafer sizes include: 4 inches, 6 inches, 8 inches, 12 inches, etc.

[0065] In this embodiment, a first device layer is subsequently formed on the surface of the first substrate 200. The first device layer includes a plurality of stacked first composite layers on the first substrate 200. The first composite layer includes a first barrier layer and a first dielectric layer on the first barrier layer; the first bonding trench penetrates at least one layer of the first dielectric layer; a first device structure within the second dielectric layer, and the first device structure is electrically connected to the first electrical interconnection structure.

[0066] Please refer to Figure 7 , a second dielectric layer 201 is formed on the surface of the first substrate 200, and a first electrical interconnection structure 202 is provided within the second dielectric layer 201.

[0067] The method for forming the first electrical interconnection structure 202 includes: forming a plurality of first conductive layers (not shown in the figure) within the second dielectric layer 201 and first conductive plugs (not shown in the figure) between adjacent first conductive layers and between the first conductive layer and the first substrate 200.

[0068] In this embodiment, the method for forming the first device layer further includes: forming a first device structure (not shown in the figure) within the second dielectric layer 201, and the first device structure is electrically connected to the first electrical interconnection structure 202.

[0069] The first device structure (not shown in the figure) includes one or more of: transistors, memory cells, resistors, capacitors, and inductors.

[0070] The material of the first electrical interconnection structure 202 includes metals such as copper, silver, aluminum, and tungsten.

[0071] The material of the second dielectric layer 201 includes one or a combination of more of: silicon nitride, silicon oxynitride, and silicon carbonitride.

[0072] Please refer to Figure 8 , the method for forming the first device layer includes: forming a plurality of stacked first composite layers 203 on the surface of the first substrate 200. The first composite layer 203 includes a first barrier layer 2031 and a first dielectric layer 2032 on the first barrier layer 2031.

[0073] The material of the first barrier layer 2031 includes one or more combinations of silicon nitride, silicon oxide, and silicon dioxide.

[0074] The material of the first dielectric layer 2032 includes one or more combinations of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0075] Please refer to Figure 9 , and a plurality of initial first bonding trenches are formed in the first device layer.

[0076] The initial first bonding trenches include: a first initial first trench 205 and a first initial second trench 206.

[0077] The method of forming the initial first bonding trenches includes: a dry etching process.

[0078] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is 0 mL / min to 2000 mL / min, the reaction pressure range is 0 mT to 3000 mT, the reaction temperature range is 0 degrees Celsius to 250 degrees Celsius, and the etching power range is 0 W to 1000 W.

[0079] The method of forming the initial first bonding trenches includes: forming a first mask layer 204 on the top of the first device layer, and the first mask layer 204 exposes a part of the surface of the first device layer; using the first mask layer 204 as a mask, etching the first device layer to form a first initial first trench 205 and a first initial second trench 206; removing the first mask layer 204.

[0080] The dimension range of the width of the first initial first trench 205 in the direction parallel to the first substrate 200 is: 0.6 micrometers to 20.56 micrometers.

[0081] Specifically, the width dimension of the first initial first trench 205 is CD + 2*M, where CD is the critical dimension and M is the thickness dimension of the initial first protective layer.

[0082] In this embodiment, the critical dimension is 0.56 micrometers.

[0083] The dimension range of the depth of the first initial first trench 205 in the direction perpendicular to the first substrate 200 is: 0.1 micrometers to 30 micrometers.

[0084] In this embodiment, the depth of the first initial first trench 205 is 0.7 micrometers.

[0085] Please refer to Figure 10, an initial first protective layer 207 is formed on the sidewall surface, bottom surface of the initial first bonding trench, and the top surface of the first device layer.

[0086] The method for forming the initial first protective layer includes: forming a first initial first protective layer 207 on the surface of the first initial first trench 205, the surface of the first initial second trench 206, and the top surface of the first device layer.

[0087] The material of the first initial first protective layer 207 includes one or a combination of more of silicon nitride compound, silicon carbide, silicon oxynitride silicon dioxide, aluminum oxide, and titanium nitride compound.

[0088] In this embodiment, the material of the first initial first protective layer 207 is a silicon nitride compound.

[0089] The etching rate ratio of the first dielectric layer 2032 to the first protective layer in the etching process for forming the initial first bonding trench ranges from 5:1 to 20:1.

[0090] The thickness dimension range of the first initial first protective layer 207 is from 0.02 micrometers to 10 micrometers.

[0091] In this embodiment, the thickness dimension of the first initial first protective layer 207 is 0.08 micrometers.

[0092] In the above solution, the etching rate of the first protective layer is less than that of the first dielectric layer 2032, so that when etching to form the first bonding trench, the etching stops at the first protective layer to protect the adjacent first device layer, protecting the bonding wafer from being damaged, and thus ensuring the performance of the bonding wafer.

[0093] Please refer to Figure 11 , after forming the first initial first protective layer 207, a second mask layer 208 is formed on the surface of the first initial second trench 206 and the top surface of the first device layer, and the second mask layer 208 exposes the bottom surface of the first initial first trench 205; using the second mask layer 208 as a mask to etch the first initial first protective layer 207 on the bottom surface of the first initial first trench 205 and the first device layer to form a second initial first trench 209 and a second initial first protective layer 210; removing the second mask layer 208.

[0094] In this embodiment, the critical dimension for etching the first initial first protective layer 207 on the bottom surface of the first initial first trench 205 and the first device layer is 0.4 micrometers.

[0095] Please refer to Figure 12, a first anti-reflection layer 212 is formed in the second initial first trench 209; a third mask layer 211 is formed on the top surface of the first device layer, and the third mask layer 211 exposes the surfaces of the second initial first trench 209 and the first initial second trench 206; using the third mask layer 211 as a mask, the second initial first protective layer 210 on the bottom surface of the first initial second trench 206 and the first device layer are etched to form the first protective layer 214 and the second initial second trench 213; the first anti-reflection layer 212 is removed.

[0096] In this embodiment, the first anti-reflection layer 212 is used to control the etching accuracy of the second initial second trench 213.

[0097] In this embodiment, the top surface of the first anti-reflection layer 212 is flush with the bottom surface of the second initial second trench 213.

[0098] Please refer to Figure 13 , using the first protective layer 214 as a mask, the second initial first trench 209 and the second initial second trench 213 are etched to form a first bonding trench.

[0099] The first bonding trench includes a first trench 215 and a second trench 216, and the depth of the first trench 215 is greater than the depth of the second trench 216.

[0100] The first trench 215 exposes the surface of the first electrical interconnect structure 202.

[0101] The first bonding trench penetrates at least one layer of the first dielectric layer 2032.

[0102] The first bonding trench includes a first region and a second region located on top of the first region, and a first protective layer is formed on the sidewall surface of the second region and the top surface of the first device layer.

[0103] Please refer to Figure 14 , a first conductive structure is formed in the first bonding trench, and the first conductive structure is located on the sidewall surface of the first protective layer 214 and fills the first bonding trench.

[0104] The method of forming the first conductive structure includes: forming a first bonding structure 217 in the first trench; forming a second bonding structure 218 in the second trench.

[0105] In this embodiment, at least one of the first conductive structures is connected to the first electrical interconnect structure 202.

[0106] The material of the first conductive structure includes one or a combination of tungsten, nickel, copper, and gold.

[0107] Please refer to Figure 15 to provide a second wafer 300, which includes a second substrate 300.

[0108] The second wafer 300 includes a semiconductor thin slice for manufacturing integrated circuits. Common wafer sizes include: 4 inches, 6 inches, 8 inches, 12 inches, etc.

[0109] In this embodiment, subsequently, a second device layer is formed on the surface of the second substrate 300. The second device layer includes a plurality of stacked second composite layers 303 on the second substrate 300. The second composite layer 303 includes a third dielectric layer 3032, a second barrier layer 3031, and a third dielectric layer 3032 on the second barrier layer 3031; the second bonding trench penetrates at least one of the third dielectric layers 3032; a fourth dielectric layer 301 between the second substrate 300 and the plurality of second composite layers 303, with a second electrical interconnection structure 302 therein; at least one of the second conductive structures is connected to the second electrical interconnection structure 302; a second device structure in the fourth dielectric layer 301, which is electrically connected to the second electrical interconnection structure 302.

[0110] Please refer to Figure 16 to form a fourth dielectric layer 301 on the surface of the second substrate 300, with a second electrical interconnection structure 302 therein.

[0111] The method of forming the second electrical interconnection structure 302 includes: forming a plurality of second conductive layers (not shown in the figure) in the fourth dielectric layer 301 and second conductive plugs (not shown in the figure) between adjacent second conductive layers and between the second conductive layer and the second substrate 300.

[0112] In this embodiment, the method of forming the second device layer further includes: forming a second device structure in the fourth dielectric layer 301, which is electrically connected to the second electrical interconnection structure 302.

[0113] The second device structure (not shown in the figure) includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

[0114] The material of the second electrical interconnection structure 302 includes metals such as copper, silver, aluminum, and tungsten.

[0115] The material of the fourth dielectric layer 301 includes one or a combination of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0116] Please refer to Figure 17, the method for forming the second device layer includes: forming a plurality of stacked second composite layers 303 on a second substrate 300, the second composite layer 303 including a second barrier layer 3031 and a third dielectric layer 3032 located on the second barrier layer 3031; the second bonding trench penetrates at least one layer of the third dielectric layer 3032.

[0117] The material of the second barrier layer 3031 includes one or a combination of silicon nitride, silicon oxide, and silicon dioxide.

[0118] The material of the third dielectric layer 3032 includes one or a combination of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0119] Please refer to Figure 18 , forming a plurality of initial second bonding trenches in the second device layer.

[0120] The initial second bonding trench includes an initial third trench 304 and an initial fourth trench 307.

[0121] The method for forming the initial second bonding trench includes: forming a fourth mask layer 303 on the top surface of the second device layer, the fourth mask layer 303 exposing a part of the top surface of the second device layer; using the fourth mask layer 303 as a mask, etching the top surface of the second device layer to form an initial third trench 304; removing the fourth mask layer 303.

[0122] The dimension of the width of the initial third trench 304 in the direction parallel to the first substrate 200 is greater than the width of the first trench.

[0123] Please refer to Figure 19 , forming a fifth mask layer 305 on the top surface of the second device layer, the fifth mask layer 305 exposing a part of the top surface of the second device layer; using the fifth mask layer 305 as a mask, etching the top surface of the second device layer to form an initial fourth trench 307; removing the fifth mask layer 305.

[0124] Before forming the fifth mask layer 305, it further includes: forming a second anti-reflection layer 306 in the initial third trench 304; after forming the initial fourth trench 307, removing the second anti-reflection layer 306.

[0125] In this embodiment, the second anti-reflection layer 306 is used to control the accuracy of the etching of the initial fourth trench 307.

[0126] In this embodiment, the top surface of the second anti-reflection layer 306 is flush with the bottom surface of the initial fourth trench 307.

[0127] Please refer toFigure 20 Using the third dielectric layer 3032 on the top surface of the second device layer as a mask, etch the bottom of the initial third trench and the bottom of the initial fourth trench to form a third trench 308 and a fourth trench 309.

[0128] The third trench 308 exposes the second electrical interconnection structure 302.

[0129] The plurality of second bonding trenches include a plurality of third trenches 308 and a plurality of fourth trenches 309, and the depth of the third trenches 308 is greater than the depth of the fourth trenches 309.

[0130] Please refer to Figure 21 , and form a second conductive structure in the second bonding trench.

[0131] The method of forming the second conductive structure includes: forming a third bonding structure 310 in the third trench; forming a fourth bonding structure 311 in the fourth trench.

[0132] The third bonding structure is electrically connected to the second electrical interconnection structure 302.

[0133] Please refer to Figure 22 , perform a bonding process on the first wafer and the second wafer, and the first conductive structure is bonded and connected to the second conductive structure.

[0134] In the above solution, by forming the first protective layer on the sidewall surface of the second region in the first bonding trench and the top surface of the first device layer, when etching to form the first bonding trench, the etching stops at the first protective layer, protecting the adjacent first device layer, ensuring the integrity of the wafer bonding structure, and further ensuring that the size of the first bonding trench in the direction parallel to the first substrate 200 remains unchanged. And since the shape of the first conductive structure matches the first bonding trench, the integrity of the first conductive structure is ensured, improving the accuracy of wafer bonding alignment and the bonding strength, and further enhancing the performance and yield of the bonding structure.

[0135] In addition, the first bonding trench includes a first trench and a plurality of second trenches, and the first conductive structure is formed in the first trench and the plurality of second trenches respectively; the plurality of second bonding trenches include a plurality of third trenches and a plurality of fourth trenches, and the second conductive structure is formed in the third trenches and the plurality of fourth trenches respectively, and the first conductive structure is bonded and connected to the second conductive structure, increasing the bonding area, enhancing the bonding strength between the first wafer and the second wafer, and ensuring the uniformity of the first device layer and the second device layer.

[0136] Further, since the shapes of the first conductive structure and the second conductive structure match the first bonding trench and the second bonding trench, the edge width at the bonding surface connection of the first conductive structure and the second conductive structure remains unchanged, ensuring the accuracy of the bonding alignment between the first wafer and the second wafer and the yield of the bonded device.

[0137] Correspondingly, please continue to refer to Figure 22 , the technical solution of the present invention further provides a wafer bonding structure, including: a first wafer, including a first substrate 200 and a first device layer located on the surface of the first substrate 200; a plurality of first bonding trenches located in the first device layer, the first bonding trench including a first region and a second region located on top of the first region; a first protective layer located on the sidewall surface of the second region and the top surface of the first device layer; a first conductive structure located in the first bonding trench, the first conductive structure located on the sidewall surface of the first protective layer and filling the first bonding trench.

[0138] In this embodiment, the first device layer includes: a plurality of stacked first composite layers 203 located on the first substrate 200, the first composite layer 203 including a first barrier layer 2031 and a first dielectric layer 2032 located on the first barrier layer 2031; the first bonding trench penetrates at least one of the first dielectric layers 2032.

[0139] In this embodiment, the material of the first dielectric layer 2032 is different from the material of the first protective layer.

[0140] In this embodiment, the material of the first barrier layer 2031 includes: one or more combinations of silicon nitride, silicon oxide, and silicon dioxide, and the material of the first dielectric layer 2032 includes: one or more combinations of silicon nitride, silicon oxynitride, and silicon carbonitride; the material of the first protective layer includes one or more combinations of silicon nitride compounds, silicon carbide, silicon oxynitride silicon dioxide, aluminum oxide, and titanium nitride compounds.

[0141] In this embodiment, the first device layer further includes: a second dielectric layer 201 located between the first substrate 200 and the plurality of first composite layers 203, and a first electrical interconnection structure 202 is provided in the second dielectric layer 201; at least one of the first conductive structures is connected to the first electrical interconnection structure 202.

[0142] In this embodiment, the first device layer further includes: a first device structure located in the second dielectric layer 201, and the first device structure is electrically connected to the first electrical interconnection structure 202.

[0143] In this embodiment, the first electrical interconnect structure 202 includes a plurality of layers of first conductive layers and first conductive plugs, and the first conductive plugs are located between adjacent first conductive layers and between the first conductive layer and the first substrate 200.

[0144] In this embodiment, the first device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

[0145] In this embodiment, the plurality of first bonding trenches include a plurality of first trenches 308 and a plurality of second trenches 309, and the depth of the first trenches 308 is greater than the depth of the second trenches 309.

[0146] In this embodiment, the wafer bonding structure further includes: a second wafer bonded to the first wafer, including a second substrate 300 and a second device layer on the surface of the second substrate 300, the second device layer being in contact with the first device layer; a plurality of second bonding trenches in the second device layer and a plurality of second conductive structures in the plurality of second bonding trenches, the second conductive structures being in contact with the first conductive structures.

[0147] In this embodiment, the second device layer includes: a plurality of stacked second composite layers 303 on the second substrate 300, the second composite layer 303 including a second barrier layer 3031 and a third dielectric layer 3032 on the second barrier layer 3031; the second bonding trenches penetrate at least one of the third dielectric layers 3032.

[0148] In this embodiment, the second device layer further includes: a fourth dielectric layer 301 between the second substrate 300 and the plurality of second composite layers 303, the fourth dielectric layer 301 having a second electrical interconnect structure 302 therein; at least one of the second conductive structures is connected to the second electrical interconnect structure 302.

[0149] In this embodiment, the second device layer further includes: a second device structure in the fourth dielectric layer 301, the second device structure being electrically connected to the second electrical interconnect structure 302.

[0150] In this embodiment, the second electrical interconnect structure 302 includes a plurality of layers of second conductive layers and second conductive plugs, and the second conductive plugs are located between adjacent second conductive layers and between the second conductive layer and the second substrate 300.

[0151] In this embodiment, the second device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

[0152] In this embodiment, the plurality of second bonding grooves include a plurality of third grooves 411 and a plurality of fourth grooves 412, and the depth of the third grooves 411 is greater than the depth of the fourth grooves 412.

[0153] Figures 23 to 29 It is a schematic structural diagram of the formation process of a wafer bonding structure in another embodiment of the present invention.

[0154] Please refer to Figure 17 On the basis of Figure 23 , form a sixth mask layer 401 on the top surface of the second device layer, and the sixth mask layer 401 exposes a part of the top surface of the second device layer; using the sixth mask layer 401 as a mask, etch the top surface of the second device layer to form second bonding grooves; remove the sixth mask layer 401.

[0155] The second bonding grooves include: a first initial fifth groove 402 and a first initial sixth groove 403.

[0156] Please refer to Figure 24 , form a first initial second protective layer 404 on the surface of the first initial fifth groove 402, the surface of the first initial sixth groove 403, and the surface of the second device layer.

[0157] The material of the first initial second protective layer 404 includes: one or a combination of more of silicon nitride compounds, silicon carbide, silicon oxynitride silicon dioxide, aluminum oxide, and titanium nitride compounds.

[0158] In this embodiment, the material of the first initial second protective layer 404 is a silicon nitride compound.

[0159] The range of the etching rate ratio of the third dielectric layer 3032 to the second protective layer for forming the initial second bonding grooves is: 5:1 to 20:1.

[0160] In this embodiment, the etching rate ratio of the third dielectric layer 3032 to the second protective layer is 10:1.

[0161] Please refer to Figure 25 , form the seventh mask layer 405 on the top surface of the second device layer and the surface of the first initial second protective layer 404 in the first initial sixth groove 403, and the seventh mask layer 405 exposes the first initial second protective layer 404 on the surface of the first initial fifth groove 402; using the seventh mask layer 405 as a mask, etch the first initial second protective layer 404 on the surface of the first initial fifth groove 402 and the second device layer to form a second initial fifth groove 406 and a second initial second protective layer 407; remove the seventh mask layer 405.

[0162] Please refer to Figure 26 , a third anti-reflection layer 407 is formed in the second initial fifth trench 406; an eighth mask layer 408 is formed on the top surface of the second device layer, and the eighth mask layer 408 exposes the second initial fifth trench 406 and the first initial sixth trench 403; using the eighth mask layer 408 as a mask, the first initial sixth trench 403 is etched to form a second initial sixth trench 409 and a second protective layer 410; the eighth mask layer 408 and the third anti-reflection layer 407 are removed.

[0163] In this embodiment, the third anti-reflection layer 407 is used to control the etching accuracy of the second initial sixth trench 409.

[0164] In this embodiment, the top surface of the third anti-reflection layer 407 is flush with the bottom surface of the second initial sixth trench 409.

[0165] Please refer to Figure 27 , using the second protective layer 410 as a mask, the second initial fifth trench 406 and the second initial sixth trench 409 are etched to form a fifth trench 411 and a sixth trench 412.

[0166] The plurality of second bonding trenches include a plurality of fifth trenches 411 and a plurality of sixth trenches 412, and the depth of the fifth trench 411 is greater than the depth of the sixth trench 412.

[0167] The second bonding trench includes a third region and a fourth region located on top of the third region, and a second protective layer 410 is formed on the sidewall surface of the fourth region and the top surface of the second device layer.

[0168] Please refer to Figure 28 , a second conductive structure is formed in the second bonding trench.

[0169] The method of forming the second conductive structure includes: forming a fifth bonding structure 413 in the fifth trench; forming a sixth bonding structure 414 in the sixth trench.

[0170] The fifth bonding structure is electrically connected to the second electrical interconnection structure 302.

[0171] Please refer to Figure 29 , the first wafer and the second wafer are subjected to a bonding process, and the first conductive structure and the second conductive structure are bonded and connected.

[0172] In the above solution, by forming a second protective layer on the sidewall surface of the fourth region in the second bonding trench and the top surface of the second device layer, when etching to form the second bonding trench, the etching stops at the second protective layer, protecting the adjacent second device layer, ensuring the integrity of the wafer bonding structure. Furthermore, the dimension of the second bonding trench in the direction parallel to the second substrate 300 remains unchanged. Since the shape of the second conductive structure matches that of the second bonding trench, the integrity of the second conductive structure is ensured, improving the accuracy of wafer bonding alignment and the bonding strength, and further enhancing the performance and yield of the bonding structure.

[0173] Correspondingly, please continue to refer to Figure 29 , the technical solution of the present invention further provides a wafer bonding structure, the wafer structure is the same as the Figure 22 wafer bonding structure, which will not be elaborated here. The difference is that Figure 23 the second bonding trench in

[0174] includes a third region and a fourth region located on top of the third region, and a second protective layer 410 on the sidewall surface of the fourth region and the top surface of the second device layer. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A wafer bonding structure, characterized in that, Comprising: A first wafer, including a first substrate and a first device layer on the surface of the first substrate; A plurality of first bonding trenches within the first device layer, the first bonding trenches including a first region and a second region on top of the first region; A first protective layer on the sidewall surface of the second region and on the top surface of the first device layer; A first conductive structure within the first bonding trench, the first conductive structure on the sidewall surface of the first protective layer and filling the first bonding trench.

2. The wafer bonding structure according to claim 1, characterized in that, The first device layer includes: a plurality of stacked first composite layers on the first substrate, the first composite layer including a first barrier layer and a first dielectric layer on the first barrier layer; the first bonding trench penetrates at least one of the first dielectric layers.

3. The wafer bonding structure according to claim 2, wherein The material of the first dielectric layer is different from the material of the first protective layer.

4. The wafer bonding structure according to claim 3, wherein The material of the first barrier layer includes one or more combinations of silicon nitride, silicon oxide, and silicon dioxide, and the material of the first dielectric layer includes one or more combinations of silicon nitride, silicon oxynitride, and silicon carbonitride; the material of the first protective layer includes one or more combinations of silicon nitride compounds, silicon carbide, silicon oxynitride silicon dioxide, aluminum oxide, and titanium nitride compounds.

5. The wafer bonding structure according to claim 2, characterized in that, The first device layer further includes: a second dielectric layer between the first substrate and the plurality of first composite layers, with a first electrical interconnection structure within the second dielectric layer; at least one of the first conductive structures is connected to the first electrical interconnection structure.

6. The wafer bonding structure according to claim 5, wherein The first device layer further includes: a first device structure within the second dielectric layer, the first device structure being electrically connected to the first electrical interconnection structure.

7. The wafer bonding structure according to claim 6, wherein The first electrical interconnection structure includes a plurality of first conductive layers and first conductive plugs, the first conductive plugs being between adjacent first conductive layers and between the first conductive layer and the first substrate.

8. The wafer bonding structure according to claim 7, wherein, The first device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

9. The wafer bonding structure according to claim 1, wherein The plurality of first bonding trenches include a plurality of first trenches and a plurality of second trenches, and the depth of the first trenches is greater than the depth of the second trenches.

10. The wafer bonding structure according to claim 1, wherein, Also included: A second wafer bonded to the first wafer, including a second substrate and a second device layer on the surface of the second substrate, the second device layer being in contact with the first device layer; A plurality of second bonding trenches within the second device layer and a plurality of second conductive structures within the plurality of second bonding trenches, the second conductive structures being in contact with the first conductive structures.

11. The wafer bonding structure according to claim 10, characterized in that, The second bonding trench includes a third region and a fourth region on top of the third region, and a second protective layer on the sidewall surface of the fourth region and on the top surface of the second device layer.

12. The wafer bonding structure according to claim 10 or 11, wherein The second device layer includes: a plurality of stacked second composite layers on the second substrate, the second composite layer including a second barrier layer and a third dielectric layer on the second barrier layer; the second bonding trench penetrates at least one of the third dielectric layers.

13. The wafer bonding structure according to claim 12, wherein The second device layer further includes: a fourth dielectric layer located between the second substrate and the plurality of second composite layers, the fourth dielectric layer having a second electrical interconnection structure therein; at least one of the second conductive structures is connected to the second electrical interconnection structure.

14. The wafer bonding structure according to claim 13, wherein, The second device layer further includes: a second device structure located within the fourth dielectric layer, the second device structure being electrically connected to the second electrical interconnection structure.

15. The wafer bonding structure according to claim 14, wherein The second electrical interconnection structure includes a plurality of second conductive layers and second conductive plugs, the second conductive plugs being located between adjacent second conductive layers, and between the second conductive layer and the second substrate.

16. The wafer bonding structure according to claim 15, wherein The second device structure includes one or more of a transistor, a memory cell, a resistor, a capacitor, and an inductor.

17. The wafer bonding structure according to claim 16, wherein, The plurality of second bonding trenches include a plurality of third trenches and a plurality of fourth trenches, the depth of the third trenches being greater than the depth of the fourth trenches.

18. A method for forming a wafer bonding structure, characterized in that, Comprising: Providing a first wafer, the first wafer including a first substrate and a first device layer on a surface of the first substrate; Forming a plurality of initial first bonding trenches in the first device layer; Forming an initial first protective layer on sidewall surfaces, bottom surfaces of the initial first bonding trenches, and a top surface of the first device layer; After forming the initial first protective layer, etching the initial first protective layer and the first device layer at the bottom of the initial first bonding trench to form a first bonding trench in the first device layer, the first bonding trench including a first region and a second region on top of the first region, and forming a first protective layer on sidewall surfaces of the second region and the top surface of the first device layer; Forming a first conductive structure in the first bonding trench, the first conductive structure being located on sidewall surfaces of the first protective layer and filling the first bonding trench.

19. The method for forming the wafer bonding structure according to claim 18, wherein The method of forming the first device layer includes: forming a plurality of stacked first composite layers on a surface of the first substrate, the first composite layer including a first barrier layer and a first dielectric layer on the first barrier layer; the first bonding trench penetrates at least one of the first dielectric layers.

20. The method for forming the wafer bonding structure according to claim 19, wherein, The etching process for forming the initial first bonding trench has a ratio of the etching rate of the first dielectric layer to the first protective layer in the range of: 5:1 to 20:

1.

21. The method for forming a wafer bonding structure according to claim 19, wherein The method of forming the first device layer further includes: forming a second dielectric layer between the first substrate and the plurality of first composite layers, the second dielectric layer having a first electrical interconnection structure therein; at least one of the first conductive structures is connected to the first electrical interconnection structure.

22. The method for forming the wafer bonding structure according to claim 21, wherein, The first electrical interconnection structure includes a plurality of first conductive layers and first conductive plugs, the first conductive plugs being located between adjacent first conductive layers, and between the first conductive layer and the first substrate.

23. The method for forming the wafer bonding structure according to claim 22, wherein, The method of forming the first device layer further includes: forming a first device structure in the second dielectric layer, the first device structure being electrically connected to the first electrical interconnection structure.

24. The method for forming a wafer bonding structure according to claim 23, wherein, The plurality of first bonding trenches include a plurality of first trenches and a plurality of second trenches, the depth of the first trenches being greater than the depth of the second trenches.

25. The method for forming a wafer bonding structure according to claim 18, wherein, Further comprising: Provide a second wafer, the second wafer includes a second substrate and a second device layer located on the surface of the second substrate, and the second device layer is in contact with the first device layer; Form a plurality of second bonding trenches in the second device layer; Form a plurality of second conductive structures in the plurality of second bonding trenches, and the second conductive structures are in contact with the first conductive structures.

26. The method for forming a wafer bonding structure according to claim 25, wherein, The method of forming the second bonding trenches further includes: forming a plurality of initial second bonding trenches in the second device layer; forming an initial second protective layer on the side wall surface, bottom surface of the initial second bonding trenches and the top surface of the second device layer; after forming the initial second protective layer, etching the initial second protective layer and the second device layer at the bottom of the initial second bonding trenches to form second bonding trenches in the second device layer, the second bonding trenches include a third region and a fourth region located on top of the third region, and a second protective layer is formed on the side wall surface of the fourth region and the top surface of the second device layer.

27. The method for forming a wafer bonding structure according to claim 25 or 26, characterized in that, The method of forming the second device layer includes: forming a plurality of stacked second composite layers on the second substrate, the second composite layers include a third dielectric layer, a second barrier layer, and a third dielectric layer located on the second barrier layer; the second bonding trenches penetrate at least one of the third dielectric layers.

28. The method for forming the wafer bonding structure according to claim 27, wherein, The method of forming the second device layer further includes: forming a fourth dielectric layer between the second substrate and the plurality of second composite layers; forming a second electrical interconnection structure in the fourth dielectric layer; at least one of the second conductive structures is connected to the second electrical interconnection structure.

29. The method for forming a wafer bonding structure according to claim 28, wherein The method of forming the second electrical interconnection structure includes: forming a plurality of second conductive layers and second conductive plugs in the fourth dielectric layer, the second conductive plugs are located between adjacent second conductive layers, and between the second conductive layer and the second substrate.

30. The method for forming a wafer bonding structure according to claim 29, wherein, The method of forming the second device layer further includes: forming a second device structure in the fourth dielectric layer, and the second device structure is electrically connected to the second electrical interconnection structure.

31. The method for forming a wafer bonding structure according to claim 25, wherein, The plurality of second bonding trenches include a plurality of third trenches and a plurality of fourth trenches, and the depth of the third trenches is greater than the depth of the fourth trenches.

32. The method for forming a wafer bonding structure according to claim 25, wherein, Further include: Perform a bonding process on the first wafer and the second wafer, and the first conductive structure is bonded to the second conductive structure.

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