Overcurrent protection circuit of bidirectional isolation SRC-LLC topology

Abstract

The invention discloses an overcurrent protection circuit for bidirectional isolation SRC-LLC topology, which relates to the technical field of power electronic converter protection and comprises a DSP control chip, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a latch module and an overcurrent signal detection circuit. The latch module comprises a logic gate circuit, the first input end of the logic gate circuit is connected with the output end of the overcurrent signal detection circuit, and the second input end of the logic gate circuit is connected with the reset signal output end of the DSP control chip; wherein the DSP control chip is used for detecting the zero crossing point of the current of the resonant cavity, and when the zero crossing point is detected, the EPWM1A driving signal, the EPWM1B driving signal, the EPWM2A driving signal and the EPWM2B driving signal are cut off through TZPWM1 and TZPWM2 signals output by the OR gate logic, so that the MOS tube is turned off at the zero crossing point, and the current impact caused by non-zero-crossing-point turn-off is avoided.

Description

Technical Field

[0001] This application relates to the technical field of power electronic converter protection, and more particularly, to an overcurrent protection circuit for a bidirectional isolated SRC-LLC topology. Background Art

[0002] Currently, in a bidirectional isolated SRC-LLC topology circuit, traditional overcurrent protection schemes usually directly monitor the current. Once overcurrent is detected, the drive signal is immediately forced to be cut off. However, this direct turn-off scheme has obvious drawbacks. Since the current of the MOS tube in the SRC-LLC topology varies sinusoidally under the action of inductance-capacitance resonance, if the drive signal is cut off directly at a non-zero crossing point, the voltage and current phases at both ends of the MOS tube will not match, resulting in a large current pulse. Such an excessive current pulse is very likely to exceed the current limit specified for the MOS tube, causing overcurrent damage and even tube explosion, seriously affecting the reliability and stability of the circuit. Summary of the Invention

[0003] The purpose of this application is to provide an overcurrent protection circuit for a bidirectional isolated SRC-LLC topology, which has the advantages of turning off the MOS tube at the zero crossing point of the resonant cavity current, effectively avoiding current impact caused by turn-off at non-zero crossing points, and protecting the safety of power devices.

[0004] This application provides an overcurrent protection circuit for a bidirectional isolated SRC-LLC topology, including: a DSP control chip, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a latch module, and an overcurrent signal detection circuit; the latch module includes a logic gate circuit, its first input terminal is connected to the output terminal of the overcurrent signal detection circuit, and its second input terminal is connected to the reset signal output terminal of the DSP control chip; the EPWM1A and EPWM1B signal output terminals of the DSP control chip are respectively connected to the two input terminals of the first OR gate, and the EPWM2A and EPWM2B signal output terminals are respectively connected to the two input terminals of the second OR gate; the output terminal of the first OR gate and the output terminal of the latch module are commonly connected to the two input terminals of the third OR gate, and the output terminal of the second OR gate and the output terminal of the latch module are commonly connected to the two input terminals of the fourth OR gate; the output terminal of the third OR gate is connected to the TZ_PWM1 drive protection port of the DSP control chip, and the output terminal of the fourth OR gate is connected to the TZ_PWM2 drive protection port of the DSP control chip; wherein, the DSP control chip is used to detect the zero crossing point of the resonant cavity current, and when the zero crossing point is detected, cut off the EPWM1A, EPWM1B, EPWM2A, and EPWM2B drive signals through the TZ_PWM1 and TZ_PWM2 signals to turn off the MOS tube at the zero crossing point and avoid current impact caused by turn-off at non-zero crossing points.

[0005] In some embodiments, EPWM1A and EPWM1B are a set of complementary symmetric pulse-width modulation signals, and EPWM2A and EPWM2B are another set of complementary symmetric pulse-width modulation signals. The phase difference between the two sets of signals is 180°, which is used to drive the alternating conduction of MOS transistors in the bidirectional isolated SRC-LLC topology.

[0006] In some embodiments, the DSP control chip is built-in with a zero-crossing detection module. The zero-crossing detection module determines a zero-crossing point when the following conditions are met by collecting the instantaneous amplitude and phase angle of the resonant cavity current waveform in real time: the instantaneous current amplitude is less than 5% of the rated current; the phase angle change rate exceeds 50° / μs.

[0007] In some embodiments, the latch module includes a combination logic circuit of an AND gate and an OR gate. When the overcurrent signal is at a high level and the reset signal is at a low level, a low-level latch control signal is output, triggering the third OR gate and the fourth OR gate to output low-level TZ_PWM1 and TZ_PWM2 signals.

[0008] In some embodiments, the overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator. The voltage comparator compares the collected current signal with a threshold value of 420A and outputs a high-level overcurrent trigger signal to the latch module.

[0009] In some embodiments, the current sampling frequency of the zero-crossing detection module is not less than 200kHz to ensure real-time performance.

[0010] In some embodiments, the latch module further includes an inverter, which is used to convert the high level of the reset signal into a low level to match the input requirements of the AND gate logic.

[0011] In some embodiments, the TZ_PWM1 and TZ_PWM2 signals are low-level effective signals. When the latch module outputs a low level, the drive protection ports of the DSP control chip immediately disable the output of the EPWM1A, EPWM1B, EPWM2A, and EPWM2B signals.

[0012] In some embodiments, an RC delay circuit is further included, which is used to delay for 10ms to 100ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the turn-off operation.

[0013] In some embodiments, the circuit is applicable to a bidirectional isolated power supply system with a working current range of 300A to 600A and a resonant frequency of 100kHz.

[0014] As can be seen from the above, an overcurrent protection circuit for a bidirectional isolation SRC-LLC topology provided by the present application accurately detects the zero-crossing point of the resonant cavity current through a DSP control chip and triggers a protection signal. By combining a latching module and a logic gate circuit, it realizes a fast and reliable cut-off of the drive signal, turns off the MOS transistor at the zero-crossing point of the resonant cavity current, effectively avoids current impact caused by turning off at non-zero-crossing points, and protects the safety of power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings are used to provide a further understanding of the technical solutions of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solutions of the present invention, and do not constitute a limitation to the technical solutions of the present invention.

[0016] The present invention will be further described below in conjunction with the drawings and embodiments; Figure 1 FIG. is a schematic diagram of an overcurrent protection circuit for a bidirectional isolation SRC-LLC topology provided by an embodiment of the present invention; Figure 2 FIG. is a timing diagram of each signal in the overcurrent protection circuit for a bidirectional isolation SRC-LLC topology provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The technical solutions in the present application will be clearly and completely described below in conjunction with the drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided in the drawings below is not intended to limit the scope of the present application claimed, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for descriptive distinction, and cannot be understood as indicating or implying relative importance.

[0018] In the prior art, in a bidirectional isolation SRC-LLC topology circuit, traditional overcurrent protection schemes directly monitor the current and forcibly cut off the drive signal when overcurrent is detected. Since the resonant cavity current exhibits a sinusoidal wave characteristic, turning off at a non-zero crossing point will cause a phase mismatch between the voltage and current at both ends of the MOS transistor, generating an instantaneous large current pulse, which may exceed the device tolerance limit and cause device damage. Such problems are particularly prominent in application scenarios that require fast response and frequent current fluctuations. For example, when a high-power density power supply system is operating, sudden load changes are likely to trigger false turn-off or non-ideal turn-off actions.

[0019] Therefore, this application proposes an overcurrent protection scheme that includes a DSP control chip, four OR gates, a latch module, and an overcurrent signal detection circuit. The EPWM1A and EPWM1B signals of the DSP control chip are connected to the input terminals of the first OR gate, and the EPWM2A and EPWM2B signals are connected to the input terminals of the second OR gate. The output terminal of the first OR gate and the output terminal of the latch module are connected to the third OR gate, and the output terminal of the second OR gate and the output terminal of the latch module are connected to the fourth OR gate. The output of the third OR gate is connected to the TZ_PWM1 drive protection port, and the output of the fourth OR gate is connected to the TZ_PWM2 drive protection port. The latch module receives the overcurrent signal and the reset signal, and controls the output of the protection signal through logical combination.

[0020] The following describes the solution of this application in conjunction with the accompanying drawings.

[0021] Refer to Figure 1 , Figure 1 which is a schematic diagram of the overcurrent protection circuit for the bidirectional isolation SRC-LLC topology provided by the embodiment of the present invention; among them, the DSP control chip is located on the left side of the figure, marked with "DSP", and is used to generate pulse width modulation (PWM) signals (EPWM1A, EPWM1B, EPWM2A, EPWM2B) and a reset signal (RESET), and is also used to detect the zero crossing point of the resonant cavity current, and when the zero crossing point is detected, cut off the drive signal through the TZ_PWM1 and TZ_PWM2 signals.

[0022] The first OR gate (OR1): Receives the EPWM1A and EPWM1B signals from the DSP and outputs them to the third OR gate (OR3).

[0023] The second OR gate (OR2): Receives the EPWM2A and EPWM2B signals from the DSP and outputs them to the fourth OR gate (OR4).

[0024] The third OR gate (OR3): Receives the signals from the first OR gate (OR1) and the latch module (LOCK), and outputs the TZ_PWM1 signal to the drive protection port of the DSP.

[0025] Fourth OR gate (OR4): Receives signals from the second OR gate (OR2) and the latch module (LOCK), and outputs the TZ_PWM2 signal to the drive protection port of the DSP.

[0026] Latch module (LOCK): Includes logic gate circuits for processing overcurrent signals and reset signals.

[0027] The first input terminal is connected to the overcurrent signal detection circuit (LLC_OCP), the second input terminal is connected to the RESET signal of the DSP, and the output signal LOCK_OCP is connected to the third OR gate (OR3) and the fourth OR gate (OR4).

[0028] Overcurrent signal detection circuit: Used to detect overcurrent conditions in the SRC-LLC topology. When the current exceeds the set threshold, it outputs an overcurrent signal (LLC_OCP) to the latch module (LOCK).

[0029] It can be understood that during normal operation, the EPWM signal output by the DSP is transmitted to the third OR gate (OR3) and the fourth OR gate (OR4) through the OR gates (OR1 and OR2), and then output to the drive protection ports (TZ_PWM1 and TZ_PWM2) of the DSP to control the normal switching action of the MOS transistors; when the overcurrent signal detection circuit detects overcurrent, it outputs the LLC_OCP signal to the latch module (LOCK), and the latch module (LOCK) performs logical processing based on the LLC_OCP signal and the RESET signal, and outputs a signal to the third OR gate (OR3) and the fourth OR gate (OR4). The third OR gate (OR3) and the fourth OR gate (OR4) forcibly turn off the TZ_PWM1 and TZ_PWM2 signals according to the received signals, cut off the drive signal, and protect the MOS transistors. When the DSP control chip detects the zero crossing point, it cuts off the EPWM signal through the TZ_PWM1 and TZ_PWM2 signals to ensure that the MOS transistors are turned off at the zero crossing point and avoid current shock caused by turning off at non-zero crossing points.

[0030] In some embodiments, the DSP control chip refers to a microcontroller with digital signal processing capabilities, which collects current signals in real time through a built-in ADC module and calculates phase information. The first OR gate and the second OR gate constitute a drive signal preprocessing unit, which can be specifically implemented by an integrated circuit and is used to combine complementary PWM signals into a single control signal. The latch module is composed of a combination of AND gates and OR gates, such as implemented by combining SN74HC08 and SN74HC32, and is used to maintain the protection state during the effective period of the overcurrent signal until the reset signal is triggered. The overcurrent signal detection circuit includes a current sensing element and a comparison circuit, which can be specifically implemented by combining a Hall sensor and an LM393 voltage comparator, and is used to convert the analog current signal into a digital trigger signal.

[0031] Specifically, the DSP control chip continuously monitors the phase change of the resonant cavity current, and when the current is detected to cross the zero point, it sends a shutdown command to the TZ_PWM1 and TZ_PWM2 ports. At this time, the high-level signal output by the overcurrent signal detection circuit and the reset signal state of the latch module jointly determine the output of the OR gate. When an overcurrent event occurs, the latch module will maintain a low-level output state, forcing the third and fourth OR gates to output a low level, thereby triggering the drive protection port to turn off the EPWM signal output. This logic design ensures that the MOS tube shutdown operation will only be performed under the dual conditions of the overcurrent signal being valid and the DSP detecting the zero point, thereby avoiding the current shock caused by the non-zero-crossing shutdown.

[0032] It is understandable that the traditional solution only relies on the current amplitude comparison to trigger the shutdown, and cannot consider the phase characteristics of the resonant current. This solution introduces a zero-crossing detection mechanism to synchronize the shutdown action with the natural zero-crossing moment of the current, eliminating the voltage and current phase mismatch problem. At the same time, a combination of logic gates is used to realize signal latching and conditional triggering, which not only ensures the real-time performance of overcurrent protection, but also avoids the risk of misoperation. Compared with the extensive protection of directly cutting off the drive, this solution achieves precise matching of protection action and circuit dynamic characteristics.

[0033] In some embodiments, in the overcurrent protection circuit of the bidirectional isolated SRC-LLC topology, EPWM1A and EPWM1B are a set of complementary and symmetrical pulse width modulation signals, EPWM2A and EPWM2B are another set of complementary and symmetrical pulse width modulation signals, and the phase difference between the two sets of signals is 180°, which are used to drive the alternating conduction of the MOS tubes in the bidirectional isolated SRC-LLC topology.

[0034] Among them, the complementary symmetrical pulse width modulation signal refers to the driving signal with two sets of waveforms that do not overlap each other on the time axis and have opposite polarities. It can be implemented by using the built-in PWM generation module of the DSP control chip, and the on and off states of the two MOS tubes on the same bridge arm are controlled by the logic circuit. The phase difference of 180° means that the rising edge and the falling edge of the two sets of driving signals are separated by half a cycle on the time axis. It can be implemented by adjusting the PWM phase register parameters of the DSP control chip so that the two sets of MOS tubes are alternately turned on at different time periods.

[0035] Specifically, the complementary and symmetrical pulse width modulation signals are configured to allow only one MOS tube in the same bridge arm to be turned on at the same time, avoiding the risk of short circuit caused by overlapping driving signals. The setting of a phase difference of 180° makes the turn-on time of the two groups of bridge arms staggered. For example, when the first group of signals drives the primary side bridge arm to turn on, the second group of signals remains in the off state. The secondary side bridge arm is driven to turn on only after the primary side is turned off. This alternating driving mechanism allows the resonant cavity current to be provided with paths by different bridge arms in the positive and negative half cycles, thereby maintaining the continuity of the current waveform.

[0036] It is understandable that in the traditional scheme, the single - group PWM signal or the phase - synchronous driving method may cause the upper and lower transistors of the same bridge arm to conduct simultaneously, generating a through - current. The combination of complementary - symmetric signals and phase - difference design not only eliminates the risk of bridge - arm through - conduction but also maintains the resonant characteristics of the current through alternating conduction, ensuring that the voltage stress borne by the MOS transistor is minimized when switching at the zero - crossing point.

[0037] In some embodiments, the DSP control chip is built - in with a zero - crossing detection module. The zero - crossing detection module determines a zero - crossing point when the following conditions are met by collecting the instantaneous amplitude and phase angle of the resonant - cavity current waveform in real time: the instantaneous current amplitude is less than 5% of the rated current; the phase - angle change rate exceeds 50° / μs.

[0038] Among them, the zero - crossing detection module refers to the circuit unit integrated inside the DSP chip for identifying the zero - crossing state of the resonant current. Specifically, it can be implemented by high - speed ADC sampling and digital filtering algorithms for real - time tracking of the current - waveform change. Among them, the instantaneous current amplitude being less than 5% of the rated current means comparing the current value at the current sampling point with the nominal current value of the system, which can be specifically realized through proportional - coefficient calculation for determining whether the current is in a low - amplitude interval close to zero. Among them, the phase - angle change rate exceeding 50° / μs means calculating the phase - angle difference between adjacent sampling points and converting it into a time - change rate, which can be specifically realized by differential operation or difference algorithm for capturing the fast phase - flip characteristic at the moment of current - direction switching.

[0039] Specifically, the zero - crossing detection module collects the resonant - cavity current signal through a current sensor. After being converted into digital quantity by ADC, the DSP internal algorithm synchronously calculates the instantaneous current amplitude and phase angle. When it is detected that the current amplitude drops below 5% of the rated value and the phase - angle change rate exceeds 50° / μs, it is determined that the current has passed through the zero - crossing point. At this time, the DSP immediately triggers a protection signal to turn off the MOS transistor driving signal at the zero - crossing point to avoid the impact caused by current mutation.

[0040] It is understandable that the traditional scheme relies only on a single condition of current amplitude to judge the zero - crossing point, which is prone to misjudgment due to noise interference or transient fluctuations. This scheme significantly improves the judgment accuracy by superimposing the dual - condition detection of amplitude and phase - change rate and utilizing the unique minimum - amplitude value and fast - phase - flip characteristic of the current zero - crossing point.

[0041] Through the above - mentioned technical solution, this application effectively solves the problem of current impact caused by non - zero - crossing turn - off. By accurately identifying the current zero - crossing moment to implement the protection action, it ensures that the MOS transistor is turned off when the current is close to zero, avoiding voltage spikes caused by current mutation, thereby improving the system reliability and reducing the risk of device damage.

[0042] In some embodiments, the latch module includes an AND gate and an OR gate combination logic circuit, which outputs a low-level latch control signal when the overcurrent signal is high and the reset signal is low, triggering the third OR gate and the fourth OR gate to output low-level TZ_PWM1 and TZ_PWM2 signals.

[0043] Among them, the AND gate and OR gate combination logic circuit refers to a signal processing unit composed of standard logic gates, which can be specifically implemented by combining the AND gate and OR gate in the 74 series integrated circuit, and is used to generate a latch control signal according to the input signal state. Among them, the high-level overcurrent signal refers to the overcurrent trigger state signal output by the voltage comparator, which can be specifically implemented by collecting the current signal through the Hall sensor and comparing it with the set threshold, and is used to indicate that the system is in an overload condition. Among them, the low-level reset signal refers to the reset control signal output by the control chip, which can be specifically implemented by outputting a low-level pulse through the GPIO port, and is used to release the latch state. Among them, the low-level latch control signal refers to the trigger signal of the drive protection port, which can be specifically implemented by outputting a low-level logic value through the logic gate circuit, and is used to immediately disable the output of the pulse width modulation signal.

[0044] Specifically, when the overcurrent detection circuit detects an overcurrent state, the voltage comparator outputs a high-level signal to the first input terminal of the AND gate. At this time, if the reset signal remains at a low level, the AND gate outputs a low level to trigger the OR gate combination circuit, so that the third OR gate and the fourth OR gate output a low-level signal to the drive protection port. This logic control method ensures that the drive signal cut-off function is triggered only when the overcurrent state continues and the reset operation is not performed.

[0045] It is understandable that traditional solutions usually use simple latches to achieve signal retention, which may cause reset response lag and false triggering risks. This solution uses a combination of logic gate circuits to build a dynamic latch mechanism, so that the overcurrent trigger signal and the reset signal form an interlocking relationship, effectively avoiding the false operation problem caused by reset signal delay.

[0046] In some embodiments, the overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator. The voltage comparator compares the collected current signal with a threshold of 420A and outputs a high-level overcurrent trigger signal to the latch module.

[0047] Among them, the Hall current sensor refers to a non-contact sensor that measures current through the magnetoelectric effect. Specifically, it can be implemented by a closed-loop Hall element, which generates a proportional voltage signal by sensing the magnetic field strength generated by the measured current. The voltage comparator refers to a circuit module used to determine whether the input voltage exceeds a preset threshold. Specifically, it can be implemented by combining a high-speed differential amplifier with a reference voltage source, by comparing the voltage signal output by the Hall sensor with the reference voltage corresponding to the 420A current in real time.

[0048] Specifically, the Hall current sensor is configured in the power loop to collect the resonant cavity current flowing through the MOS transistor in real time and convert it into a voltage signal. This voltage signal is input to the non-inverting terminal of the voltage comparator, while the inverting terminal is connected to a reference level set to the voltage value corresponding to 420A. When the current exceeds the threshold, the voltage comparator outputs a logic high level to trigger the latch module. For example, a hysteresis comparator can be used to prevent false triggering caused by noise. The comparison process between the current detection signal and the reference threshold is completed within the microsecond level, ensuring that the overcurrent state is captured in a timely manner.

[0049] It can be understood that the traditional scheme uses resistor sampling combined with a fixed-threshold comparator, which is susceptible to temperature drift and has limited response speed. The Hall current sensor does not require a series sampling resistor, which can avoid power loss and improve the detection accuracy. At the same time, its broadband characteristic can accurately track the high-frequency resonant current waveform. The voltage comparator uses a preset threshold instead of a dynamic adjustment mode, which simplifies the circuit structure and enhances the anti-interference ability.

[0050] In some embodiments, the current sampling frequency of the zero-crossing detection module is not less than 200 kHz to ensure real-time performance.

[0051] Among them, the current sampling frequency refers to the number of times of collecting current signals per unit time, which can be specifically implemented by a high-speed ADC module. For example, a 12-bit analog-to-digital conversion unit integrated in a DSP chip controls the data capture rate by setting the value of its sampling period register. Real-time performance refers to the synchronization degree between the system response speed and the change of the physical process. Specifically, by shortening the sampling interval to within 5 microseconds, the detection lag time of the current waveform change is compressed within the allowable range of the resonant period.

[0052] Specifically, the zero-crossing detection module digitally samples the resonant cavity current at a fixed time interval. When the sampling frequency reaches 200 kHz, more than 400 data points can be obtained within each power frequency cycle. This high-density sampling enables the zero-crossing mutation of the current waveform to be quickly captured. The system can complete the judgment logic operation within three sampling periods before the current amplitude drops to the threshold, so as to ensure that the deviation between the moment of generating the turn-off instruction and the current zero-crossing does not exceed 1.5 degrees of phase angle.

[0053] It can be understood that the traditional overcurrent protection scheme usually uses a sampling frequency below 100 kHz, resulting in a delay of more than 10 microseconds in the detection of the current zero-crossing. This scheme improves the sampling rate, doubles the speed of obtaining the phase information of the current change, effectively eliminates the problem of misjudgment or missed judgment of the zero-crossing caused by too long sampling interval, and avoids the MOS transistor being forcibly turned off in a non-zero-crossing state of the current.

[0054] In some embodiments, the latching module includes an inverter, which is used to convert the high level of the reset signal into a low level to match the input requirements of the AND gate logic.

[0055] Among them, an inverter refers to a circuit unit that logically negates the input signal. Specifically, it can be implemented by a NOT gate circuit built with transistors or an integrated logic chip. Its function is to convert a high-level signal into a low-level signal to ensure that the input level of the logic gate matches. Among them, the input requirements of the AND gate logic refer to the voltage threshold conditions that the logic gate needs to meet when receiving different level signals. Specifically, it can be implemented using standard TTL or CMOS level specifications. Its function is to avoid logical misjudgment through level matching.

[0056] Specifically, when the reset signal is at a high level, the inverter converts it into a low-level signal and inputs it to the AND gate. At this time, if the overcurrent signal is also at a high level, the AND gate will output a low-level latching control signal, thereby triggering the drive protection port to cut off the pulse width modulation signal output. When the reset signal is at a low level, the inverter outputs a high level, enabling the AND gate logic to make a judgment based on the overcurrent signal state, thereby realizing the logical synchronization processing of the reset signal and the overcurrent signal.

[0057] It can be understood that the traditional overcurrent protection circuit does not consider the compatibility issue between the control chip reset signal and the logic gate level specification. When the reset signal level does not match the input requirements of the logic gate, it may cause the latching module to fail to respond correctly. By adding an inverter, the contradiction between the high level of the reset signal and the low-level trigger condition of the logic gate can be eliminated, ensuring the effectiveness of the overcurrent protection mechanism.

[0058] In some embodiments, an RC delay circuit is further included, which is used to delay for 10 ms to 100 ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the turn-off operation.

[0059] Among them, the RC delay circuit refers to a delay circuit composed of a resistor and a capacitor. Specifically, it can be implemented by connecting a fixed resistor in parallel with a variable capacitor, and the delay time can be changed by adjusting the capacitance or resistance value. This circuit forms a time window in the overcurrent signal transmission path to filter out instantaneous interference signals. Among them, the delay after the overcurrent signal is triggered refers to the waiting time between detecting the overcurrent signal and performing the turn-off operation. Specifically, it can be achieved by setting the RC time constant. For example, setting the resistor to 10 kΩ and the capacitor to 1 μF to form a delay of about 10 ms. This delay is used to distinguish between instantaneous overcurrent and continuous overcurrent to avoid mis-triggering the protection action.

[0060] Specifically, when the overcurrent signal detection circuit outputs a high-level trigger signal, the RC delay circuit starts to work. Within a preset delay time, for example, within the range of 10 ms to 100 ms, the state of the overcurrent signal is continuously monitored. If the overcurrent signal disappears during this period, it is determined as an instantaneous interference and the turn-off operation is not triggered; if the overcurrent signal persists, it is confirmed that the overcurrent state is valid, and then a low-level signal is output through the latching module to trigger the drive protection port to cut off the MOS transistor drive signal.

[0061] It can be understood that the traditional scheme immediately cuts off the drive signal after detecting overcurrent, unable to distinguish between instantaneous interference and real faults, and is prone to frequent turn-off due to misjudgment. However, this scheme effectively avoids misoperation caused by instantaneous interference and the risk of protection failure due to excessive delay by introducing a delay confirmation mechanism while maintaining real-time protection capabilities.

[0062] In some embodiments, an RC delay circuit is further included, which is used to delay for 10 ms to 100 ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the turn-off operation.

[0063] Among them, the RC delay circuit refers to a delay trigger circuit composed of a resistor and a capacitor, which can be specifically implemented by a series-connected metal film resistor and an electrolytic capacitor. Different delay times can be set by adjusting the resistance value of the resistor and the capacitance value of the capacitor. Among them, the confirmation of the persistence of the overcurrent state refers to judging whether the current continuously exceeds the threshold through a preset time window, which can be specifically implemented by the cooperation of a timer module and a comparator to distinguish between instantaneous interference and real faults.

[0064] Specifically, when the Hall current sensor detects that the current exceeds 420 A, the overcurrent signal detection circuit outputs a high-level trigger signal to the RC delay circuit. At this time, the RC circuit starts to charge and starts the delay. For example, the resistor can be selected from 1 kΩ to 10 kΩ, and the capacitor can be selected from 10 μF to 100 μF to make the delay time reach the range of 10 ms to 100 ms. If the overcurrent signal persists during the delay period, it is determined as a real overcurrent fault, and the latching module outputs a low-level signal to trigger the drive protection port to cut off the MOS transistor drive signal; if the overcurrent signal disappears during the delay period, it is determined as an instantaneous interference and the RC circuit is automatically reset.

[0065] In some specific embodiments, the resistor and the capacitor are surface-mounted devices connected in parallel to the input end of the latching module, and the delay parameters can be finely adjusted by changing the wiring length of the RC components in the PCB layout.

[0066] It can be understood that the traditional overcurrent protection scheme immediately cuts off the drive signal after detecting that the current exceeds the standard, unable to distinguish between instantaneous current spikes and continuous overloads. By introducing a delay judgment mechanism, mis-triggering caused by instantaneous fluctuations of resonant current can be effectively avoided, and at the same time, accurate protection actions can be ensured when real overcurrent occurs.

[0067] In some embodiments, the circuit is applicable to a bidirectional isolated power supply system with an operating current range of 300 A to 600 A and a resonant frequency of 100 kHz.

[0068] Among them, the operating current range of 300 A to 600 A refers to the current range that the circuit can carry in the bidirectional energy transfer scenario. Specifically, MOS transistors with a current-carrying capacity exceeding 600 A and low-loss magnetic components can be used to achieve this. This parameter range enables the circuit to meet the requirements of high-power density power supply systems. The resonant frequency of 100 kHz refers to the natural oscillation frequency formed by the inductor and capacitor in the resonant cavity. Specifically, it can be achieved by adjusting the parameter combination of the resonant components with an inductance of 3 μH and a capacitance value of 0.25 μF. This frequency setting is beneficial to achieving a balance between the switching loss of silicon-based devices and the system efficiency.

[0069] Specifically, when the circuit operates in the current range of 300 A to 600 A, the Hall sensor in the overcurrent signal detection circuit will collect the current signal in real time. For example, the CASR series sensors of LEM Company can meet the linear detection requirements of a 600 A range. When an overcurrent event is detected, the latching module and the DSP control chip work together, combined with the zero-crossing detection mechanism at a resonant frequency of 100 kHz, to ensure that the MOS transistor drive signal is cut off at the zero-crossing point of the current sine wave. The resonant period at this frequency is 10 μs, which requires the zero-crossing detection module to complete signal sampling, processing, and response actions within 5 μs. For example, an AD7606 type 16-bit ADC can achieve a sampling rate of 200 kSPS to meet the real-time requirements.

[0070] It can be understood that the traditional overcurrent protection scheme is only designed for low-voltage and low-power scenarios below 200 A. Its current detection accuracy and response speed cannot adapt to high-current working conditions above 300 A, and there is a risk of zero-crossing misjudgment in resonant systems above 50 kHz. This scheme can accurately capture the zero-crossing point of the 100 kHz high-frequency resonant current by optimizing the detection circuit bandwidth and logic control timing, and avoid voltage spikes caused by high-current turn-off.

[0071] Reference Figure 2 , Figure 2 is the timing diagram of each signal in the overcurrent protection circuit of the bidirectional isolated SRC-LLC topology provided by the embodiment of the present invention. Among them, EPWM1A and EPWM1B are complementary to each other during normal operation. When one is at a high level, the other must be at a low level. For example, at the initial moment, EPWM1A is at a high level and EPWM1B is at a low level. After a period of time, their levels are reversed, EPWM1A becomes low, and EPWM1B becomes high, alternating. When shutting down, when an overcurrent signal appears, both of them may be forced to be set low to stop outputting the drive signal.

[0072] EPWM2A and EPWM2B are also complementary to each other during normal operation, alternating and cooperating with EPWM1A and EPWM1B to control the bidirectional isolated SRC-LLC topology; when turned off and an overcurrent signal appears, they may also be forced to go low.

[0073] LLC_OCP is normally low. When the detected current exceeds the set threshold, it becomes high and remains high, triggering subsequent protection actions as an overcurrent signal; LOCK_OCP is normally low. After LLC_OCP becomes high, LOCK_OCP becomes high and remains high after a certain delay, realizing the locking of the overcurrent signal and ensuring that the protection mechanism can continue to function to prevent the protection from being interrupted due to the short disappearance of the overcurrent signal.

[0074] TZ_PWM2 and TZ_PWM1 are controlled by the EPWM signal and follow the EPWM signal during normal operation. For example, when EPWM1A and EPWM1B output normal complementary signals, TZ_PWM1 changes accordingly to drive devices such as MOS transistors; during overcurrent shutdown, after LOCK_OCP becomes high, the TZ_PWM1 and TZ_PWM2 signals are forced to go low, cutting off the drive signal for the MOS transistor to achieve shutdown protection; in addition, after the overcurrent signal is eliminated and certain conditions are met, TZ_PWM1 and TZ_PWM2 may resume outputting normal signals.

[0075] The above are only embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. An overcurrent protection circuit for a bidirectional isolated SRC-LLC topology, characterized in that, Comprising: A DSP control chip, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a latch module, and an overcurrent signal detection circuit; the latch module includes a logic gate circuit, its first input terminal is connected to the output terminal of the overcurrent signal detection circuit, and its second input terminal is connected to the reset signal output terminal of the DSP control chip; the EPWM1A and EPWM1B signal output terminals of the DSP control chip are respectively connected to the two input terminals of the first OR gate, and the EPWM2A and EPWM2B signal output terminals are respectively connected to the two input terminals of the second OR gate; the output terminal of the first OR gate and the output terminal of the latch module are commonly connected to the two input terminals of the third OR gate, and the output terminal of the second OR gate and the output terminal of the latch module are commonly connected to the two input terminals of the fourth OR gate; the output terminal of the third OR gate is connected to the TZ_PWM1 drive protection port of the DSP control chip, and the output terminal of the fourth OR gate is connected to the TZ_PWM2 drive protection port of the DSP control chip; Wherein, the DSP control chip is used to detect the zero crossing point of the resonant cavity current, and when the zero crossing point is detected, cut off the EPWM1A, EPWM1B, EPWM2A, and EPWM2B drive signals through the TZ_PWM1 and TZ_PWM2 signals, so as to turn off the MOS tube at the zero crossing point and avoid the current impact caused by turning off at non-zero crossing points.

2. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, wherein The EPWM1A and EPWM1B are a set of complementary symmetric pulse width modulation signals, and the EPWM2A and EPWM2B are another set of complementary symmetric pulse width modulation signals. The phase difference between the two sets of signals is 180°, which is used to drive the alternating conduction of the MOS tubes in the bidirectional isolation SRC-LLC topology.

3. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, wherein The DSP control chip is built-in with a zero crossing detection module. The zero crossing detection module determines it as a zero crossing point when the following conditions are met by real-time collecting the instantaneous amplitude and phase angle of the resonant cavity current waveform: the instantaneous current amplitude is less than 5% of the rated current; the phase angle change rate exceeds 50° / μs.

4. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, wherein The latch module includes an AND gate and an OR gate combined logic circuit. When the overcurrent signal is high level and the reset signal is low level, it outputs a low-level latch control signal to trigger the third OR gate and the fourth OR gate to output low-level TZ_PWM1 and TZ_PWM2 signals.

5. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, characterized in that, The overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator. The voltage comparator compares the collected current signal with a threshold value of 420A and outputs a high-level overcurrent trigger signal to the latch module.

6. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 3, characterized in that, The current sampling frequency of the zero crossing detection module is not less than 200kHz to ensure real-time performance.

7. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 4, wherein The latch module further includes an inverter for converting the high level of the reset signal into a low level to match the input requirements of the AND gate logic.

8. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, characterized in that, The TZ_PWM1 and TZ_PWM2 signals are low-level effective signals. When the latch module outputs a low level, the drive protection ports of the DSP control chip immediately disable the output of the EPWM1A, EPWM1B, EPWM2A, and EPWM2B signals.

9. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, characterized in that, It also includes an RC delay circuit, which is used to delay for 10 ms to 100 ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the turn-off operation.

10. The overcurrent protection circuit of the bidirectional isolation SRC-LLC topology according to claim 1, characterized in that, The circuit is applicable to a bidirectional isolated power supply system with a working current range of 300 A to 600 A and a resonance frequency of 100 kHz.

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