A THD optimization circuit and control method

Abstract

The present invention discloses a THD optimization circuit and control method, comprising a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4, and an AND gate G5. The inverting input of the comparator CMP3 is connected to a reference voltage Reference2, the non-inverting input is connected to the output of a ramp generating circuit, the non-inverting input of the comparator CMP4 is connected to a signal VCS, the inverting input is connected to the reference voltage Reference3, the output of the comparator CMP4 is connected to the input of the inverter G2, the outputs of the inverter G2 and the comparator CMP3 are connected to the input of the NAND gate G3, the outputs of the inverter G2 and the NAND gate G3 are connected to the input of the NAND gate G4, and the output of the NAND gate G4 is connected to the second input of the AND gate G5. The present invention reduces the THD of an AC / DC power supply and improves power supply efficiency.

Description

Technical Field

[0001] The present invention relates to an optimization circuit and a control method, in particular to a THD optimization circuit and a control method, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] An increasing number of electrical devices are connected to the power grid, and most of these devices utilize efficient switching power supply architectures rather than purely resistive power supplies. This results in the input current not accurately tracking input voltage variations. Since the input AC voltage is a periodic sinusoidal waveform, harmonic currents are used to characterize the deviation of the input current from the sinusoidal waveform. Harmonic currents generate reactive power, increase grid losses, accelerate the aging of the grid and electrical devices, and interfere with communications and audio / video equipment on the grid. Total harmonic distortion (THD) is the sum of all additional harmonic levels. As the scale of electrical devices and the power of individual devices continue to increase, the requirements for power supply THD parameters are becoming increasingly stringent.

[0003] like Figure 5 As shown, the AC / DC power supply system of the COT control mode of the prior art includes a rectifier bridge B1, a capacitor C1, a capacitor C2, a capacitor C3, a freewheeling diode D1, a resistor RO, a resistor RS, an inductor L1, a power switch M1 and a power controller U1. The first input end of the rectifier bridge B1 is connected to the AC power line L, the second input end of the rectifier bridge B1 is connected to the AC power line N, the first output end of the rectifier bridge B1 is connected to one end of the capacitor C1, the VIN pin of the power controller U1, the cathode of the freewheeling diode D1, one end of the capacitor C2 and one end of the resistor R0 to generate a signal VIN, and the second output end of the rectifier bridge B1 is connected to the AC power line N. The end and the other end of the capacitor C1 are grounded, the VCC pin of the power controller U1 is connected to one end of the capacitor C3, the other end of the capacitor C3 and the GND pin of the power controller U1 are grounded, the GATE pin of the power controller U1 is connected to the gate of the power switch M1, the CS pin of the power controller U1 is connected to one end of the power switch M1 and one end of the resistor RS, the other end of the resistor RS is grounded, the other end of the power switch M1 is connected to the anode of the freewheeling diode D1 and one end of the inductor L1 to generate a signal VDRAIN, and the other end of the inductor L1 is connected to the other end of the capacitor C2 and the other end of the resistor R0.

[0004] like Figure 6As shown, the COT control circuit of the prior art is included in the power supply controller U1, and the COT control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver, the input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected to the reference voltage Reference1, the output end of the error amplifier EA is connected to the inverting input end of the comparator CMP1, the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1 and generates a signal ZCD, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates a signal PWM, and the output end of the driving circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates a signal GATE.

[0005] like Figure 7Figure 2 shows a schematic waveform diagram of a conventional AC / DC power supply system. Signal VIN represents the voltage at the VIN pin of power controller U1, signal GATE represents the voltage at the GATE pin of power controller U1, signal VDRAIN represents the drain voltage of power switch M1, signal VCS represents the voltage at the CS pin of power controller U1, and signal VOUT represents the voltage across second capacitor C2. At time T0, signal VIN enters the AC valley region. As signal VIN decreases, the rising slope of signal VCS gradually decreases during the on-time of power switch M1 (i.e., the time when signal GATE is high). Until time T1, controlled by the COT control method, the on-time of power switch M1 remains at a first fixed time, TON, while the off-time gradually decreases. At time T1, the off-time of power switch M1 reaches its minimum. Simultaneously, the voltage of signal VIN approaches the level of signal VOUT. During this period, the on-time of power switch M1 remains fixed at or near the first fixed time, TON, while the off-time remains at its minimum until time T3. During the period from T1 to T3, including time T2, the first fixed TON time, derived from the COT loop, can be relatively short under certain system parameters and / or operating conditions. This results in very low cycle-by-cycle peaks of signal VCS and a high switching frequency. Due to parasitics and delays, signal VCS generates large, high-frequency, cycle-by-cycle negative current spikes during this period, thereby increasing the THD of the entire power supply. At time T3, the input AC voltage amplitude enters a rising cycle and significantly exceeds signal VOUT. Signal VIN begins to rise in line with the input AC voltage amplitude. The on-time of power switch M1 remains at the first fixed TON time, while its off-time gradually increases until time T4. At time T4, signal VIN exits the AC valley region.

[0006] As can be seen from the above, the existing buck AC / DC converter architecture using COT control is widely used due to its simple control, stable operation, streamlined peripherals, and low cost. However, as power increases and the output voltage (VOUT) rises, the deviation of the input current from the sinusoidal trajectory of the input voltage increases within the input AC voltage estimation region, increasing total harmonic distortion (THD). Furthermore, the switching frequency is higher in the valley region. At this time, due to the minimal inductor excitation energy, the high switching frequency causes the power devices to release more negative current spikes. Because these negative current spikes are unintended, they also increase THD and increase power switching losses. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a THD optimization circuit and a control method to reduce the THD of a step-down AC / DC power supply in a COT control mode.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A THD optimization circuit includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4, and an AND gate G5. The inverting input of the comparator CMP3 is connected to a reference voltage Reference2, the non-inverting input of the comparator CMP3 is connected to the output of a ramp generating circuit Ramp Generator of the COT control circuit, the output of the comparator CMP3 is connected to the first input of the NAND gate G3, the non-inverting input of the comparator CMP4 is connected to a signal VCS, the inverting input of the comparator CMP4 is connected to the reference voltage Reference3, the output of the comparator CMP4 is connected to the input of the inverter G2, the output of the inverter G2 is connected to the second input of the NAND gate G3 and the second input of the NAND gate G4, the output of the NAND gate G3 is connected to the first input of the NAND gate G4, the output of the NAND gate G4 is connected to the second input of the AND gate G5, and the output of the AND gate G5 is connected to the R terminal of an RS trigger G1 of the COT control circuit.

[0010] Furthermore, the COT control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit RampGenerator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver, the input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected to the reference voltage Reference1, the output end of the error amplifier EA is connected to the inverting input end of the comparator CMP1, the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the AND gate G5, the output end of the AND gate G5 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the inverting input end of the comparator CMP2 is connected to the signal VCS, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1 and generates the signal ZCD, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates the signal PWM, and the output end of the driving circuit module Driver generates the signal GATE.

[0011] Furthermore, one and only one of the reference voltage Reference2 and the reference voltage Reference3 is a variable comparison reference voltage.

[0012] Furthermore, the variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage divider and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input end of the voltage divider and peak detection module Divider&Peak Sample is connected to the signal VIN, the output end of the voltage divider and peak detection module Divider&Peak Sample is connected to the input end of the compensation circuit module Compensation and generates a peak sampling voltage VIN_PEAK, and the output end of the compensation circuit module Compensation generates a variable comparison reference voltage.

[0013] Furthermore, when the reference voltage Reference3 is a variable comparison reference voltage, the value of the reference voltage Reference3 decreases as the peak sampling voltage VIN_PEAK increases within the interval [PEAK1, PEAK2] of the peak sampling voltage VIN_PEAK, wherein PEAK1 and PEAK2 are constants.

[0014] Furthermore, when the reference voltage Reference2 is a variable comparison reference voltage, the value of the reference voltage Reference2 increases with the increase of the peak sampling voltage VIN_PEAK within the interval [PEAK1, PEAK2] of the peak sampling voltage VIN_PEAK, wherein PEAK1 and PEAK2 are constants.

[0015] A control method for a THD optimization circuit comprises the following steps:

[0016] The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference3 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the signal of the first section of the GATE pulse width by comparing the signal VCS with the variable comparison reference voltage Reference3. The comparator CMP3 obtains the signal of the first section of the GATE pulse width by comparing the ramp generation circuit Ramp The output signal of the generator and the reference voltage Reference2 are used to obtain the second signal that takes over the GATE pulse width. When the output signal of comparator CMP1 flips to logic high after the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the moment when the output signal of comparator CMP1 flips to logic high. When the output signal of comparator CMP1 flips to logic high before the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the moment when the output signal of comparator CMP4 flips to logic high. When the output signal of comparator CMP3 flips to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse width is determined by the moment when the output signal of comparator CMP3 flips to logic high.

[0017] A control method for a THD optimization circuit comprises the following steps:

[0018] The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference2 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the first section of the GATE pulse width by comparing the signal VCS with the reference voltage Reference3. The comparator CMP3 obtains the first section of the GATE pulse width by comparing the ramp generation circuit Ramp. The output signal of the generator and the variable comparison reference voltage Reference2 are used to obtain a signal for the second section to take over the GATE pulse width. When the output signal of comparator CMP1 flips to logic high after the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP1 flips to logic high. When the output signal of comparator CMP1 flips to logic high before the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP4 flips to logic high. When the output signal of comparator CMP3 flips to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse width is determined by the time when the output signal of comparator CMP3 flips to logic high.

[0019] Compared with the prior art, the present invention has the following advantages and effects:

[0020] 1. The present invention performs a series of compensations on the control method of the input AC voltage valley region, so that the input current can better follow the sinusoidal trajectory of the input AC voltage, thereby improving the PF value of the power supply and reducing the THD value of the power supply;

[0021] 2. The present invention reduces the THD of the COT-controlled buck AC / DC power supply and improves power efficiency by reducing the switching frequency in the valley region and reducing the negative current disturbance caused by switching in the valley region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a schematic diagram of a THD optimization circuit according to embodiment 1 of the present invention.

[0023] Figure 2 2 is a schematic diagram of a THD optimization circuit according to a second embodiment of the present invention.

[0024] Figure 3 It is a waveform diagram of the variable comparison reference voltage of the present invention.

[0025] Figure 4 This is a waveform diagram of an AC / DC power supply system in which a THD optimization circuit of the present invention is located.

[0026] Figure 5 FIG. 1 is a schematic diagram of an AC / DC power supply system using a COT control method in the prior art.

[0027] Figure 6 Schematic diagram of a COT control circuit in the prior art.

[0028] Figure 7 Schematic diagram of the waveform of the AC / DC power supply system in the prior art. DETAILED DESCRIPTION

[0029] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0030] Example 1. Figure 1 As shown, a THD optimization circuit of the present invention includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4 and an AND gate G5, wherein the inverting input terminal of the comparator CMP3 is connected to the reference voltage Reference2, the non-inverting input terminal of the comparator CMP3 is connected to the output terminal of the ramp generating circuit RampGenerator of the COT control circuit, the output terminal of the comparator CMP3 is connected to the first input terminal of the NAND gate G3, and the positive input terminal of the comparator CMP4 is connected to the output terminal of the ramp generating circuit RampGenerator of the COT control circuit. The phase input terminal is connected to the signal VCS, the inverting input terminal of the comparator CMP4 is connected to the reference voltage Reference3, the output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2, the output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4, the output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4, the output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5, and the output terminal of the AND gate G5 is connected to the R terminal of the RS trigger G1 of the COT control circuit.

[0031] The COT control circuit includes a sample and hold module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driver circuit module Driver. The input of the sample and hold module Sample&Hold is connected to the signal VCS, the output of the sample and hold module Sample&Hold is connected to the inverting input of the error amplifier EA, the non-inverting input of the error amplifier EA is connected to the reference voltage Reference1, the output of the error amplifier EA is connected to the inverting input of the comparator CMP1, and the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the AND gate G5, the output end of the AND gate G5 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the inverting input end of the comparator CMP2 is connected to the signal VCS, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1 and generates the signal ZCD, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates the signal PWM, and the output end of the driving circuit module Driver generates the signal GATE.

[0032] Reference voltage Reference3 is a variable comparison reference voltage. This variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage divider and peak detection module, Divider & Peak Sample, and a compensation circuit module, Compensation. The input of the voltage divider and peak detection module, Divider & Peak Sample, is connected to signal VIN. The output of the voltage divider and peak detection module, Divider & Peak Sample, is connected to the input of the compensation circuit module, Compensation, to generate a peak sampling voltage, VIN_PEAK. The output of the compensation circuit module, Compensation, generates the variable comparison reference voltage.

[0033] like Figure 3As shown in (a), Vref1 and Vref2 are constants, with Vref1 > Vref2. When reference voltage Reference3 is a variable comparison reference voltage, the value of reference voltage Reference3 decreases as peak sampling voltage VIN_PEAK increases within the interval [PEAK1, PEAK2], gradually changing from Vref1 to Vref2. PEAK1 and PEAK2 are constants, with PEAK2 > PEAK1. When VIN_PEAK ≤ PEAK1, Reference3 remains constant at Vref1. When VIN ≥ PEAK2, Reference3 remains constant at Vref2.

[0034] A control method for a THD optimization circuit comprises the following steps:

[0035] The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference3 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the signal of the first section of the GATE pulse width by comparing the signal VCS with the variable comparison reference voltage Reference3. The comparator CMP3 obtains the signal of the first section of the GATE pulse width by comparing the ramp generation circuit Ramp The output signal of the generator and the reference voltage Reference2 are used to obtain the second signal that takes over the GATE pulse width. When the output signal of comparator CMP1 flips to logic high after the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the moment when the output signal of comparator CMP1 flips to logic high. When the output signal of comparator CMP1 flips to logic high before the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the moment when the output signal of comparator CMP4 flips to logic high. When the output signal of comparator CMP3 flips to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse width is determined by the moment when the output signal of comparator CMP3 flips to logic high.

[0036] Example 2. Figure 2As shown, a THD optimization circuit of the present invention includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4 and an AND gate G5, wherein the inverting input terminal of the comparator CMP3 is connected to the reference voltage Reference2, the non-inverting input terminal of the comparator CMP3 is connected to the output terminal of the ramp generating circuit RampGenerator of the COT control circuit, the output terminal of the comparator CMP3 is connected to the first input terminal of the NAND gate G3, and the positive input terminal of the comparator CMP4 is connected to the output terminal of the ramp generating circuit RampGenerator of the COT control circuit. The phase input terminal is connected to the signal VCS, the inverting input terminal of the comparator CMP4 is connected to the reference voltage Reference3, the output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2, the output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4, the output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4, the output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5, and the output terminal of the AND gate G5 is connected to the R terminal of the RS trigger G1 of the COT control circuit.

[0037] The COT control circuit includes a sample and hold module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driver circuit module Driver. The input of the sample and hold module Sample&Hold is connected to the signal VCS, the output of the sample and hold module Sample&Hold is connected to the inverting input of the error amplifier EA, the non-inverting input of the error amplifier EA is connected to the reference voltage Reference1, the output of the error amplifier EA is connected to the inverting input of the comparator CMP1, and the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the AND gate G5, the output end of the AND gate G5 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the inverting input end of the comparator CMP2 is connected to the signal VCS, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1 and generates the signal ZCD, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates the signal PWM, and the output end of the driving circuit module Driver generates the signal GATE.

[0038] Reference voltage Reference2 is a variable comparison reference voltage. This variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage divider and peak detection module, Divider & Peak Sample, and a compensation circuit module, Compensation. The input of the voltage divider and peak detection module, Divider & Peak Sample, is connected to signal VIN. The output of the voltage divider and peak detection module, Divider & Peak Sample, is connected to the input of the compensation circuit module, Compensation, to generate a peak sampling voltage, VIN_PEAK. The output of the compensation circuit module, Compensation, generates the variable comparison reference voltage.

[0039] like Figure 3 As shown in (b), Vref3 and Vref4 are constants, with Vref3 > Vref4. When reference voltage Reference2 is a variable comparison reference voltage, the value of reference voltage Reference2 increases with the peak sampling voltage VIN_PEAK within the interval [PEAK1, PEAK2], gradually changing from Vref4 to Vref3. PEAK1 and PEAK2 are constants, and PEAK2 > PEAK1. When VIN_PEAK ≤ PEAK1, Reference2 remains constant at Vref4. When VIN ≥ PEAK2, Reference2 remains constant at Vref3.

[0040] A control method for a THD optimization circuit comprises the following steps:

[0041] The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference2 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the first section of the GATE pulse width by comparing the signal VCS with the reference voltage Reference3. The comparator CMP3 obtains the first section of the GATE pulse width by comparing the ramp generation circuit Ramp. The output signal of the generator and the variable comparison reference voltage Reference2 are used to obtain a signal for the second section to take over the GATE pulse width. When the output signal of comparator CMP1 flips to logic high after the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP1 flips to logic high. When the output signal of comparator CMP1 flips to logic high before the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP4 flips to logic high. When the output signal of comparator CMP3 flips to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse width is determined by the time when the output signal of comparator CMP3 flips to logic high.

[0042] like Figure 4As shown, at time T0, signal VIN enters the AC valley region. As signal VIN decreases, the rising slope of signal VCS gradually decreases during the on-time of power switch M1 (i.e., the time when signal GATE is high). Until time T1, controlled by the COT control method, the on-time of power switch M1 during this phase remains at a first fixed time, TON, while the off-time gradually decreases. At time T1, the peak value of signal VCS reaches the level of reference voltage Reference2. Thereafter, the cycle-by-cycle peak value of signal VCS is locked at the level of reference voltage Reference2 until time T2. During this phase, because the cycle-by-cycle peak value of signal VCS remains constant while the rising slope continues to slow, the TON time of power switch M1 gradually increases. At time T2, the TON time of power switch M1 increases to a second fixed time, TON, and remains fixed at the second fixed time until time T3. Because the second fixed TON time is significantly longer than the first fixed TON time, the cycle-by-cycle peak value of signal VCS remains significantly greater than zero, offsetting the cycle-by-cycle negative current spikes caused by parasitics and delays, thereby reducing THD. Furthermore, the switching frequency during this phase is low, reducing the contribution of harmonic disturbances to THD, further reducing THD. At time T3, the input AC voltage amplitude enters a rising cycle and significantly exceeds signal VOUT. The voltage of signal VIN begins to rise in line with the input AC voltage amplitude. The on-time of power switch M1 remains at the first fixed TON time, while the off-time of power switch M1 gradually increases until time T4. At time T4, signal VIN exits the AC valley region.

[0043] The present invention performs a series of compensations on the control method of the valley region of the input AC voltage, so that the input current better follows the sinusoidal trajectory of the input AC voltage, thereby improving the PF value of the power supply and reducing the THD value of the power supply. The present invention reduces the THD of the step-down AC / DC power supply using the COT control method by reducing the switching frequency in the valley region and reducing the negative current disturbance caused by switching in the valley region, thereby improving the power supply efficiency.

[0044] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A THD optimization circuit, characterized in that: The circuit comprises a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4 and an AND gate G5, wherein the inverting input terminal of the comparator CMP3 is connected to a reference voltage Reference2, the non-inverting input terminal of the comparator CMP3 is connected to the output terminal of a ramp generating circuit Ramp Generator of the COT control circuit, the output terminal of the comparator CMP3 is connected to a first input terminal of the NAND gate G3, the non-inverting input terminal of the comparator CMP4 is connected to a signal VCS, the inverting input terminal of the comparator CMP4 is connected to the reference voltage Reference3, the output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2, the output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4, the output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4, the output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5, and the output terminal of the AND gate G5 is connected to the R terminal of the RS trigger G1 of the COT control circuit; The COT control circuit includes a sampling and holding module Sample&Hold, a ramp generating circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS trigger G1 and a driving circuit module Driver. The input end of the sampling and holding module Sample&Hold is connected to the signal VCS, the output end of the sampling and holding module Sample&Hold is connected to the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected to the reference voltage Reference1, the output end of the error amplifier EA is connected to the inverting input end of the comparator CMP1, and the ramp generating circuit Ramp The output end of the Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the AND gate G5, the output end of the AND gate G5 is connected to the R end of the RS trigger G1, the non-inverting input end of the comparator CMP2 is grounded, the inverting input end of the comparator CMP2 is connected to the signal VCS, the output end of the comparator CMP2 is connected to the S end of the RS trigger G1 and generates the signal ZCD, the Q end of the RS trigger G1 is connected to the input end of the driving circuit module Driver and generates the signal PWM, and the output end of the driving circuit module Driver generates the signal GATE.

2. The THD optimization circuit according to claim 1, wherein: Among the reference voltage Reference2 and the reference voltage Reference3, only one is a variable comparison reference voltage.

3. The THD optimization circuit according to claim 2, wherein: The variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage divider and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input end of the voltage divider and peak detection module Divider&Peak Sample is connected to the signal VIN, the output end of the voltage divider and peak detection module Divider&Peak Sample is connected to the input end of the compensation circuit module Compensation and generates a peak sampling voltage VIN_PEAK, and the output end of the compensation circuit module Compensation generates a variable comparison reference voltage.

4. The THD optimization circuit according to claim 2, wherein: When the reference voltage Reference3 is a variable comparison reference voltage, the value of the reference voltage Reference3 decreases as the peak sampling voltage VIN_PEAK increases within the interval [PEAK1, PEAK2] of the peak sampling voltage VIN_PEAK, wherein PEAK1 and PEAK2 are constants.

5. The THD optimization circuit according to claim 2, wherein: When the reference voltage Reference2 is a variable comparison reference voltage, the value of the reference voltage Reference2 increases as the peak sampling voltage VIN_PEAK increases within the interval [PEAK1, PEAK2], where PEAK1 and PEAK2 are constants.

6. A control method for a THD optimization circuit according to claim 4, characterized in that The following steps are involved: The voltage divider and peak detection module Divider & Peak Sample obtains a peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference3 according to the peak sampling voltage VIN_PEAK. Comparator CMP4 obtains a signal for the first GATE pulse duration by comparing signal VCS with a variable reference voltage Reference3. Comparator CMP3 obtains a signal for the second GATE pulse duration by comparing the output signal of ramp generator Ramp Generator with reference voltage Reference2. When the output signal of comparator CMP1 transitions to logic high after the output signal of comparator CMP4 transitions to logic high, the GATE pulse duration is determined by the time when the output signal of comparator CMP1 transitions to logic high. When the output signal of comparator CMP1 transitions to logic high before the output signal of comparator CMP4 transitions to logic high, the GATE pulse duration is determined by the time when the output signal of comparator CMP4 transitions to logic high. When the output signal of comparator CMP3 transitions to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse duration is determined by the time when the output signal of comparator CMP3 transitions to logic high.

7. A control method for a THD optimization circuit according to claim 5, characterized in that The following steps are involved: The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference2 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the first section of the GATE pulse width by comparing the signal VCS with the reference voltage Reference3. The comparator CMP3 obtains the first section of the GATE pulse width by comparing the ramp generation circuit Ramp. The output signal of the generator and the variable comparison reference voltage Reference2 are used to obtain a signal for the second section to take over the GATE pulse width. When the output signal of comparator CMP1 flips to logic high after the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP1 flips to logic high. When the output signal of comparator CMP1 flips to logic high before the output signal of comparator CMP4 flips to logic high, the GATE pulse width is determined by the time when the output signal of comparator CMP4 flips to logic high. When the output signal of comparator CMP3 flips to logic high and the output signal of comparator CMP4 remains logic low, the GATE pulse width is determined by the time when the output signal of comparator CMP3 flips to logic high.

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